hi655x-pmic.h 2.0 KB

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  1. /*
  2. * Device driver for regulators in hi655x IC
  3. *
  4. * Copyright (c) 2016 Hisilicon.
  5. *
  6. * Authors:
  7. * Chen Feng <puck.chen@hisilicon.com>
  8. * Fei Wang <w.f@huawei.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #ifndef __HI655X_PMIC_H
  15. #define __HI655X_PMIC_H
  16. /* Hi655x registers are mapped to memory bus in 4 bytes stride */
  17. #define HI655X_STRIDE 4
  18. #define HI655X_BUS_ADDR(x) ((x) << 2)
  19. #define HI655X_BITS 8
  20. #define HI655X_NR_IRQ 32
  21. #define HI655X_IRQ_STAT_BASE (0x003 << 2)
  22. #define HI655X_IRQ_MASK_BASE (0x007 << 2)
  23. #define HI655X_ANA_IRQM_BASE (0x1b5 << 2)
  24. #define HI655X_IRQ_ARRAY 4
  25. #define HI655X_IRQ_MASK 0xFF
  26. #define HI655X_IRQ_CLR 0xFF
  27. #define HI655X_VER_REG 0x00
  28. #define PMU_VER_START 0x10
  29. #define PMU_VER_END 0x38
  30. #define RESERVE_INT 7
  31. #define PWRON_D20R_INT 6
  32. #define PWRON_D20F_INT 5
  33. #define PWRON_D4SR_INT 4
  34. #define VSYS_6P0_D200UR_INT 3
  35. #define VSYS_UV_D3R_INT 2
  36. #define VSYS_2P5_R_INT 1
  37. #define OTMP_D1R_INT 0
  38. #define RESERVE_INT_MASK BIT(RESERVE_INT)
  39. #define PWRON_D20R_INT_MASK BIT(PWRON_D20R_INT)
  40. #define PWRON_D20F_INT_MASK BIT(PWRON_D20F_INT)
  41. #define PWRON_D4SR_INT_MASK BIT(PWRON_D4SR_INT)
  42. #define VSYS_6P0_D200UR_INT_MASK BIT(VSYS_6P0_D200UR_INT)
  43. #define VSYS_UV_D3R_INT_MASK BIT(VSYS_UV_D3R_INT)
  44. #define VSYS_2P5_R_INT_MASK BIT(VSYS_2P5_R_INT)
  45. #define OTMP_D1R_INT_MASK BIT(OTMP_D1R_INT)
  46. struct hi655x_pmic {
  47. struct resource *res;
  48. struct device *dev;
  49. struct regmap *regmap;
  50. int gpio;
  51. unsigned int ver;
  52. struct regmap_irq_chip_data *irq_data;
  53. };
  54. #endif