ehci-mem.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2001 by David Brownell
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the
  6. * Free Software Foundation; either version 2 of the License, or (at your
  7. * option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12. * for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software Foundation,
  16. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17. */
  18. /* this file is part of ehci-hcd.c */
  19. /*-------------------------------------------------------------------------*/
  20. /*
  21. * There's basically three types of memory:
  22. * - data used only by the HCD ... kmalloc is fine
  23. * - async and periodic schedules, shared by HC and HCD ... these
  24. * need to use dma_pool or dma_alloc_coherent
  25. * - driver buffers, read/written by HC ... single shot DMA mapped
  26. *
  27. * There's also "register" data (e.g. PCI or SOC), which is memory mapped.
  28. * No memory seen by this driver is pageable.
  29. */
  30. /*-------------------------------------------------------------------------*/
  31. /* Allocate the key transfer structures from the previously allocated pool */
  32. static inline void ehci_qtd_init(struct ehci_hcd *ehci, struct ehci_qtd *qtd,
  33. dma_addr_t dma)
  34. {
  35. memset (qtd, 0, sizeof *qtd);
  36. qtd->qtd_dma = dma;
  37. qtd->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT);
  38. qtd->hw_next = EHCI_LIST_END(ehci);
  39. qtd->hw_alt_next = EHCI_LIST_END(ehci);
  40. INIT_LIST_HEAD (&qtd->qtd_list);
  41. }
  42. static struct ehci_qtd *ehci_qtd_alloc (struct ehci_hcd *ehci, gfp_t flags)
  43. {
  44. struct ehci_qtd *qtd;
  45. dma_addr_t dma;
  46. qtd = dma_pool_alloc (ehci->qtd_pool, flags, &dma);
  47. if (qtd != NULL) {
  48. ehci_qtd_init(ehci, qtd, dma);
  49. }
  50. return qtd;
  51. }
  52. static inline void ehci_qtd_free (struct ehci_hcd *ehci, struct ehci_qtd *qtd)
  53. {
  54. dma_pool_free (ehci->qtd_pool, qtd, qtd->qtd_dma);
  55. }
  56. static void qh_destroy(struct ehci_hcd *ehci, struct ehci_qh *qh)
  57. {
  58. /* clean qtds first, and know this is not linked */
  59. if (!list_empty (&qh->qtd_list) || qh->qh_next.ptr) {
  60. ehci_dbg (ehci, "unused qh not empty!\n");
  61. BUG ();
  62. }
  63. if (qh->dummy)
  64. ehci_qtd_free (ehci, qh->dummy);
  65. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  66. kfree(qh);
  67. }
  68. static struct ehci_qh *ehci_qh_alloc (struct ehci_hcd *ehci, gfp_t flags)
  69. {
  70. struct ehci_qh *qh;
  71. dma_addr_t dma;
  72. qh = kzalloc(sizeof *qh, GFP_ATOMIC);
  73. if (!qh)
  74. goto done;
  75. qh->hw = (struct ehci_qh_hw *)
  76. dma_pool_alloc(ehci->qh_pool, flags, &dma);
  77. if (!qh->hw)
  78. goto fail;
  79. memset(qh->hw, 0, sizeof *qh->hw);
  80. qh->qh_dma = dma;
  81. // INIT_LIST_HEAD (&qh->qh_list);
  82. INIT_LIST_HEAD (&qh->qtd_list);
  83. INIT_LIST_HEAD(&qh->unlink_node);
  84. /* dummy td enables safe urb queuing */
  85. qh->dummy = ehci_qtd_alloc (ehci, flags);
  86. if (qh->dummy == NULL) {
  87. ehci_dbg (ehci, "no dummy td\n");
  88. goto fail1;
  89. }
  90. done:
  91. return qh;
  92. fail1:
  93. dma_pool_free(ehci->qh_pool, qh->hw, qh->qh_dma);
  94. fail:
  95. kfree(qh);
  96. return NULL;
  97. }
  98. /*-------------------------------------------------------------------------*/
  99. /* The queue heads and transfer descriptors are managed from pools tied
  100. * to each of the "per device" structures.
  101. * This is the initialisation and cleanup code.
  102. */
  103. static void ehci_mem_cleanup (struct ehci_hcd *ehci)
  104. {
  105. if (ehci->async)
  106. qh_destroy(ehci, ehci->async);
  107. ehci->async = NULL;
  108. if (ehci->dummy)
  109. qh_destroy(ehci, ehci->dummy);
  110. ehci->dummy = NULL;
  111. /* DMA consistent memory and pools */
  112. dma_pool_destroy(ehci->qtd_pool);
  113. ehci->qtd_pool = NULL;
  114. dma_pool_destroy(ehci->qh_pool);
  115. ehci->qh_pool = NULL;
  116. dma_pool_destroy(ehci->itd_pool);
  117. ehci->itd_pool = NULL;
  118. dma_pool_destroy(ehci->sitd_pool);
  119. ehci->sitd_pool = NULL;
  120. if (ehci->periodic)
  121. dma_free_coherent (ehci_to_hcd(ehci)->self.controller,
  122. ehci->periodic_size * sizeof (u32),
  123. ehci->periodic, ehci->periodic_dma);
  124. ehci->periodic = NULL;
  125. /* shadow periodic table */
  126. kfree(ehci->pshadow);
  127. ehci->pshadow = NULL;
  128. }
  129. /* remember to add cleanup code (above) if you add anything here */
  130. static int ehci_mem_init (struct ehci_hcd *ehci, gfp_t flags)
  131. {
  132. int i;
  133. /* QTDs for control/bulk/intr transfers */
  134. ehci->qtd_pool = dma_pool_create ("ehci_qtd",
  135. ehci_to_hcd(ehci)->self.controller,
  136. sizeof (struct ehci_qtd),
  137. 32 /* byte alignment (for hw parts) */,
  138. 4096 /* can't cross 4K */);
  139. if (!ehci->qtd_pool) {
  140. goto fail;
  141. }
  142. /* QHs for control/bulk/intr transfers */
  143. ehci->qh_pool = dma_pool_create ("ehci_qh",
  144. ehci_to_hcd(ehci)->self.controller,
  145. sizeof(struct ehci_qh_hw),
  146. 32 /* byte alignment (for hw parts) */,
  147. 4096 /* can't cross 4K */);
  148. if (!ehci->qh_pool) {
  149. goto fail;
  150. }
  151. ehci->async = ehci_qh_alloc (ehci, flags);
  152. if (!ehci->async) {
  153. goto fail;
  154. }
  155. /* ITD for high speed ISO transfers */
  156. ehci->itd_pool = dma_pool_create ("ehci_itd",
  157. ehci_to_hcd(ehci)->self.controller,
  158. sizeof (struct ehci_itd),
  159. 32 /* byte alignment (for hw parts) */,
  160. 4096 /* can't cross 4K */);
  161. if (!ehci->itd_pool) {
  162. goto fail;
  163. }
  164. /* SITD for full/low speed split ISO transfers */
  165. ehci->sitd_pool = dma_pool_create ("ehci_sitd",
  166. ehci_to_hcd(ehci)->self.controller,
  167. sizeof (struct ehci_sitd),
  168. 32 /* byte alignment (for hw parts) */,
  169. 4096 /* can't cross 4K */);
  170. if (!ehci->sitd_pool) {
  171. goto fail;
  172. }
  173. /* Hardware periodic table */
  174. ehci->periodic = (__le32 *)
  175. dma_alloc_coherent (ehci_to_hcd(ehci)->self.controller,
  176. ehci->periodic_size * sizeof(__le32),
  177. &ehci->periodic_dma, flags);
  178. if (ehci->periodic == NULL) {
  179. goto fail;
  180. }
  181. if (ehci->use_dummy_qh) {
  182. struct ehci_qh_hw *hw;
  183. ehci->dummy = ehci_qh_alloc(ehci, flags);
  184. if (!ehci->dummy)
  185. goto fail;
  186. hw = ehci->dummy->hw;
  187. hw->hw_next = EHCI_LIST_END(ehci);
  188. hw->hw_qtd_next = EHCI_LIST_END(ehci);
  189. hw->hw_alt_next = EHCI_LIST_END(ehci);
  190. ehci->dummy->hw = hw;
  191. for (i = 0; i < ehci->periodic_size; i++)
  192. ehci->periodic[i] = cpu_to_hc32(ehci,
  193. ehci->dummy->qh_dma);
  194. } else {
  195. for (i = 0; i < ehci->periodic_size; i++)
  196. ehci->periodic[i] = EHCI_LIST_END(ehci);
  197. }
  198. /* software shadow of hardware table */
  199. ehci->pshadow = kcalloc(ehci->periodic_size, sizeof(void *), flags);
  200. if (ehci->pshadow != NULL)
  201. return 0;
  202. fail:
  203. ehci_dbg (ehci, "couldn't init memory\n");
  204. ehci_mem_cleanup (ehci);
  205. return -ENOMEM;
  206. }