mvebu-uart.c 15 KB

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  1. /*
  2. * ***************************************************************************
  3. * Marvell Armada-3700 Serial Driver
  4. * Author: Wilson Ding <dingwei@marvell.com>
  5. * Copyright (C) 2015 Marvell International Ltd.
  6. * ***************************************************************************
  7. * This program is free software: you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the Free
  9. * Software Foundation, either version 2 of the License, or any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. * ***************************************************************************
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/console.h>
  22. #include <linux/delay.h>
  23. #include <linux/device.h>
  24. #include <linux/init.h>
  25. #include <linux/io.h>
  26. #include <linux/iopoll.h>
  27. #include <linux/of.h>
  28. #include <linux/of_address.h>
  29. #include <linux/of_device.h>
  30. #include <linux/of_irq.h>
  31. #include <linux/of_platform.h>
  32. #include <linux/platform_device.h>
  33. #include <linux/serial.h>
  34. #include <linux/serial_core.h>
  35. #include <linux/slab.h>
  36. #include <linux/tty.h>
  37. #include <linux/tty_flip.h>
  38. /* Register Map */
  39. #define UART_RBR 0x00
  40. #define RBR_BRK_DET BIT(15)
  41. #define RBR_FRM_ERR_DET BIT(14)
  42. #define RBR_PAR_ERR_DET BIT(13)
  43. #define RBR_OVR_ERR_DET BIT(12)
  44. #define UART_TSH 0x04
  45. #define UART_CTRL 0x08
  46. #define CTRL_SOFT_RST BIT(31)
  47. #define CTRL_TXFIFO_RST BIT(15)
  48. #define CTRL_RXFIFO_RST BIT(14)
  49. #define CTRL_ST_MIRR_EN BIT(13)
  50. #define CTRL_LPBK_EN BIT(12)
  51. #define CTRL_SND_BRK_SEQ BIT(11)
  52. #define CTRL_PAR_EN BIT(10)
  53. #define CTRL_TWO_STOP BIT(9)
  54. #define CTRL_TX_HFL_INT BIT(8)
  55. #define CTRL_RX_HFL_INT BIT(7)
  56. #define CTRL_TX_EMP_INT BIT(6)
  57. #define CTRL_TX_RDY_INT BIT(5)
  58. #define CTRL_RX_RDY_INT BIT(4)
  59. #define CTRL_BRK_DET_INT BIT(3)
  60. #define CTRL_FRM_ERR_INT BIT(2)
  61. #define CTRL_PAR_ERR_INT BIT(1)
  62. #define CTRL_OVR_ERR_INT BIT(0)
  63. #define CTRL_RX_INT (CTRL_RX_RDY_INT | CTRL_BRK_DET_INT |\
  64. CTRL_FRM_ERR_INT | CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
  65. #define UART_STAT 0x0c
  66. #define STAT_TX_FIFO_EMP BIT(13)
  67. #define STAT_RX_FIFO_EMP BIT(12)
  68. #define STAT_TX_FIFO_FUL BIT(11)
  69. #define STAT_TX_FIFO_HFL BIT(10)
  70. #define STAT_RX_TOGL BIT(9)
  71. #define STAT_RX_FIFO_FUL BIT(8)
  72. #define STAT_RX_FIFO_HFL BIT(7)
  73. #define STAT_TX_EMP BIT(6)
  74. #define STAT_TX_RDY BIT(5)
  75. #define STAT_RX_RDY BIT(4)
  76. #define STAT_BRK_DET BIT(3)
  77. #define STAT_FRM_ERR BIT(2)
  78. #define STAT_PAR_ERR BIT(1)
  79. #define STAT_OVR_ERR BIT(0)
  80. #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR | STAT_FRM_ERR\
  81. | STAT_PAR_ERR | STAT_OVR_ERR)
  82. #define UART_BRDV 0x10
  83. #define MVEBU_NR_UARTS 1
  84. #define MVEBU_UART_TYPE "mvebu-uart"
  85. static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
  86. struct mvebu_uart_data {
  87. struct uart_port *port;
  88. struct clk *clk;
  89. };
  90. /* Core UART Driver Operations */
  91. static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
  92. {
  93. unsigned long flags;
  94. unsigned int st;
  95. spin_lock_irqsave(&port->lock, flags);
  96. st = readl(port->membase + UART_STAT);
  97. spin_unlock_irqrestore(&port->lock, flags);
  98. return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
  99. }
  100. static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
  101. {
  102. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  103. }
  104. static void mvebu_uart_set_mctrl(struct uart_port *port,
  105. unsigned int mctrl)
  106. {
  107. /*
  108. * Even if we do not support configuring the modem control lines, this
  109. * function must be proided to the serial core
  110. */
  111. }
  112. static void mvebu_uart_stop_tx(struct uart_port *port)
  113. {
  114. unsigned int ctl = readl(port->membase + UART_CTRL);
  115. ctl &= ~CTRL_TX_RDY_INT;
  116. writel(ctl, port->membase + UART_CTRL);
  117. }
  118. static void mvebu_uart_start_tx(struct uart_port *port)
  119. {
  120. unsigned int ctl = readl(port->membase + UART_CTRL);
  121. ctl |= CTRL_TX_RDY_INT;
  122. writel(ctl, port->membase + UART_CTRL);
  123. }
  124. static void mvebu_uart_stop_rx(struct uart_port *port)
  125. {
  126. unsigned int ctl = readl(port->membase + UART_CTRL);
  127. ctl &= ~CTRL_RX_INT;
  128. writel(ctl, port->membase + UART_CTRL);
  129. }
  130. static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
  131. {
  132. unsigned int ctl;
  133. unsigned long flags;
  134. spin_lock_irqsave(&port->lock, flags);
  135. ctl = readl(port->membase + UART_CTRL);
  136. if (brk == -1)
  137. ctl |= CTRL_SND_BRK_SEQ;
  138. else
  139. ctl &= ~CTRL_SND_BRK_SEQ;
  140. writel(ctl, port->membase + UART_CTRL);
  141. spin_unlock_irqrestore(&port->lock, flags);
  142. }
  143. static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
  144. {
  145. struct tty_port *tport = &port->state->port;
  146. unsigned char ch = 0;
  147. char flag = 0;
  148. do {
  149. if (status & STAT_RX_RDY) {
  150. ch = readl(port->membase + UART_RBR);
  151. ch &= 0xff;
  152. flag = TTY_NORMAL;
  153. port->icount.rx++;
  154. if (status & STAT_PAR_ERR)
  155. port->icount.parity++;
  156. }
  157. if (status & STAT_BRK_DET) {
  158. port->icount.brk++;
  159. status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
  160. if (uart_handle_break(port))
  161. goto ignore_char;
  162. }
  163. if (status & STAT_OVR_ERR)
  164. port->icount.overrun++;
  165. if (status & STAT_FRM_ERR)
  166. port->icount.frame++;
  167. if (uart_handle_sysrq_char(port, ch))
  168. goto ignore_char;
  169. if (status & port->ignore_status_mask & STAT_PAR_ERR)
  170. status &= ~STAT_RX_RDY;
  171. status &= port->read_status_mask;
  172. if (status & STAT_PAR_ERR)
  173. flag = TTY_PARITY;
  174. status &= ~port->ignore_status_mask;
  175. if (status & STAT_RX_RDY)
  176. tty_insert_flip_char(tport, ch, flag);
  177. if (status & STAT_BRK_DET)
  178. tty_insert_flip_char(tport, 0, TTY_BREAK);
  179. if (status & STAT_FRM_ERR)
  180. tty_insert_flip_char(tport, 0, TTY_FRAME);
  181. if (status & STAT_OVR_ERR)
  182. tty_insert_flip_char(tport, 0, TTY_OVERRUN);
  183. ignore_char:
  184. status = readl(port->membase + UART_STAT);
  185. } while (status & (STAT_RX_RDY | STAT_BRK_DET));
  186. tty_flip_buffer_push(tport);
  187. }
  188. static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
  189. {
  190. struct circ_buf *xmit = &port->state->xmit;
  191. unsigned int count;
  192. unsigned int st;
  193. if (port->x_char) {
  194. writel(port->x_char, port->membase + UART_TSH);
  195. port->icount.tx++;
  196. port->x_char = 0;
  197. return;
  198. }
  199. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  200. mvebu_uart_stop_tx(port);
  201. return;
  202. }
  203. for (count = 0; count < port->fifosize; count++) {
  204. writel(xmit->buf[xmit->tail], port->membase + UART_TSH);
  205. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  206. port->icount.tx++;
  207. if (uart_circ_empty(xmit))
  208. break;
  209. st = readl(port->membase + UART_STAT);
  210. if (st & STAT_TX_FIFO_FUL)
  211. break;
  212. }
  213. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  214. uart_write_wakeup(port);
  215. if (uart_circ_empty(xmit))
  216. mvebu_uart_stop_tx(port);
  217. }
  218. static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
  219. {
  220. struct uart_port *port = (struct uart_port *)dev_id;
  221. unsigned int st = readl(port->membase + UART_STAT);
  222. if (st & (STAT_RX_RDY | STAT_OVR_ERR | STAT_FRM_ERR | STAT_BRK_DET))
  223. mvebu_uart_rx_chars(port, st);
  224. if (st & STAT_TX_RDY)
  225. mvebu_uart_tx_chars(port, st);
  226. return IRQ_HANDLED;
  227. }
  228. static int mvebu_uart_startup(struct uart_port *port)
  229. {
  230. int ret;
  231. writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
  232. port->membase + UART_CTRL);
  233. udelay(1);
  234. writel(CTRL_RX_INT, port->membase + UART_CTRL);
  235. ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, "serial",
  236. port);
  237. if (ret) {
  238. dev_err(port->dev, "failed to request irq\n");
  239. return ret;
  240. }
  241. return 0;
  242. }
  243. static void mvebu_uart_shutdown(struct uart_port *port)
  244. {
  245. writel(0, port->membase + UART_CTRL);
  246. free_irq(port->irq, port);
  247. }
  248. static void mvebu_uart_set_termios(struct uart_port *port,
  249. struct ktermios *termios,
  250. struct ktermios *old)
  251. {
  252. unsigned long flags;
  253. unsigned int baud;
  254. spin_lock_irqsave(&port->lock, flags);
  255. port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR |
  256. STAT_TX_RDY | STAT_TX_FIFO_FUL;
  257. if (termios->c_iflag & INPCK)
  258. port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
  259. port->ignore_status_mask = 0;
  260. if (termios->c_iflag & IGNPAR)
  261. port->ignore_status_mask |=
  262. STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
  263. if ((termios->c_cflag & CREAD) == 0)
  264. port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR;
  265. if (old)
  266. tty_termios_copy_hw(termios, old);
  267. baud = uart_get_baud_rate(port, termios, old, 0, 460800);
  268. uart_update_timeout(port, termios->c_cflag, baud);
  269. spin_unlock_irqrestore(&port->lock, flags);
  270. }
  271. static const char *mvebu_uart_type(struct uart_port *port)
  272. {
  273. return MVEBU_UART_TYPE;
  274. }
  275. static void mvebu_uart_release_port(struct uart_port *port)
  276. {
  277. /* Nothing to do here */
  278. }
  279. static int mvebu_uart_request_port(struct uart_port *port)
  280. {
  281. return 0;
  282. }
  283. #ifdef CONFIG_CONSOLE_POLL
  284. static int mvebu_uart_get_poll_char(struct uart_port *port)
  285. {
  286. unsigned int st = readl(port->membase + UART_STAT);
  287. if (!(st & STAT_RX_RDY))
  288. return NO_POLL_CHAR;
  289. return readl(port->membase + UART_RBR);
  290. }
  291. static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
  292. {
  293. unsigned int st;
  294. for (;;) {
  295. st = readl(port->membase + UART_STAT);
  296. if (!(st & STAT_TX_FIFO_FUL))
  297. break;
  298. udelay(1);
  299. }
  300. writel(c, port->membase + UART_TSH);
  301. }
  302. #endif
  303. static const struct uart_ops mvebu_uart_ops = {
  304. .tx_empty = mvebu_uart_tx_empty,
  305. .set_mctrl = mvebu_uart_set_mctrl,
  306. .get_mctrl = mvebu_uart_get_mctrl,
  307. .stop_tx = mvebu_uart_stop_tx,
  308. .start_tx = mvebu_uart_start_tx,
  309. .stop_rx = mvebu_uart_stop_rx,
  310. .break_ctl = mvebu_uart_break_ctl,
  311. .startup = mvebu_uart_startup,
  312. .shutdown = mvebu_uart_shutdown,
  313. .set_termios = mvebu_uart_set_termios,
  314. .type = mvebu_uart_type,
  315. .release_port = mvebu_uart_release_port,
  316. .request_port = mvebu_uart_request_port,
  317. #ifdef CONFIG_CONSOLE_POLL
  318. .poll_get_char = mvebu_uart_get_poll_char,
  319. .poll_put_char = mvebu_uart_put_poll_char,
  320. #endif
  321. };
  322. /* Console Driver Operations */
  323. #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
  324. /* Early Console */
  325. static void mvebu_uart_putc(struct uart_port *port, int c)
  326. {
  327. unsigned int st;
  328. for (;;) {
  329. st = readl(port->membase + UART_STAT);
  330. if (!(st & STAT_TX_FIFO_FUL))
  331. break;
  332. }
  333. writel(c, port->membase + UART_TSH);
  334. for (;;) {
  335. st = readl(port->membase + UART_STAT);
  336. if (st & STAT_TX_FIFO_EMP)
  337. break;
  338. }
  339. }
  340. static void mvebu_uart_putc_early_write(struct console *con,
  341. const char *s,
  342. unsigned n)
  343. {
  344. struct earlycon_device *dev = con->data;
  345. uart_console_write(&dev->port, s, n, mvebu_uart_putc);
  346. }
  347. static int __init
  348. mvebu_uart_early_console_setup(struct earlycon_device *device,
  349. const char *opt)
  350. {
  351. if (!device->port.membase)
  352. return -ENODEV;
  353. device->con->write = mvebu_uart_putc_early_write;
  354. return 0;
  355. }
  356. EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
  357. OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
  358. mvebu_uart_early_console_setup);
  359. static void wait_for_xmitr(struct uart_port *port)
  360. {
  361. u32 val;
  362. readl_poll_timeout_atomic(port->membase + UART_STAT, val,
  363. (val & STAT_TX_EMP), 1, 10000);
  364. }
  365. static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
  366. {
  367. wait_for_xmitr(port);
  368. writel(ch, port->membase + UART_TSH);
  369. }
  370. static void mvebu_uart_console_write(struct console *co, const char *s,
  371. unsigned int count)
  372. {
  373. struct uart_port *port = &mvebu_uart_ports[co->index];
  374. unsigned long flags;
  375. unsigned int ier;
  376. int locked = 1;
  377. if (oops_in_progress)
  378. locked = spin_trylock_irqsave(&port->lock, flags);
  379. else
  380. spin_lock_irqsave(&port->lock, flags);
  381. ier = readl(port->membase + UART_CTRL) &
  382. (CTRL_RX_INT | CTRL_TX_RDY_INT);
  383. writel(0, port->membase + UART_CTRL);
  384. uart_console_write(port, s, count, mvebu_uart_console_putchar);
  385. wait_for_xmitr(port);
  386. if (ier)
  387. writel(ier, port->membase + UART_CTRL);
  388. if (locked)
  389. spin_unlock_irqrestore(&port->lock, flags);
  390. }
  391. static int mvebu_uart_console_setup(struct console *co, char *options)
  392. {
  393. struct uart_port *port;
  394. int baud = 9600;
  395. int bits = 8;
  396. int parity = 'n';
  397. int flow = 'n';
  398. if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
  399. return -EINVAL;
  400. port = &mvebu_uart_ports[co->index];
  401. if (!port->mapbase || !port->membase) {
  402. pr_debug("console on ttyMV%i not present\n", co->index);
  403. return -ENODEV;
  404. }
  405. if (options)
  406. uart_parse_options(options, &baud, &parity, &bits, &flow);
  407. return uart_set_options(port, co, baud, parity, bits, flow);
  408. }
  409. static struct uart_driver mvebu_uart_driver;
  410. static struct console mvebu_uart_console = {
  411. .name = "ttyMV",
  412. .write = mvebu_uart_console_write,
  413. .device = uart_console_device,
  414. .setup = mvebu_uart_console_setup,
  415. .flags = CON_PRINTBUFFER,
  416. .index = -1,
  417. .data = &mvebu_uart_driver,
  418. };
  419. static int __init mvebu_uart_console_init(void)
  420. {
  421. register_console(&mvebu_uart_console);
  422. return 0;
  423. }
  424. console_initcall(mvebu_uart_console_init);
  425. #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
  426. static struct uart_driver mvebu_uart_driver = {
  427. .owner = THIS_MODULE,
  428. .driver_name = "mvebu_serial",
  429. .dev_name = "ttyMV",
  430. .nr = MVEBU_NR_UARTS,
  431. #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
  432. .cons = &mvebu_uart_console,
  433. #endif
  434. };
  435. static int mvebu_uart_probe(struct platform_device *pdev)
  436. {
  437. struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  438. struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  439. struct uart_port *port;
  440. struct mvebu_uart_data *data;
  441. int ret;
  442. if (!reg || !irq) {
  443. dev_err(&pdev->dev, "no registers/irq defined\n");
  444. return -EINVAL;
  445. }
  446. port = &mvebu_uart_ports[0];
  447. spin_lock_init(&port->lock);
  448. port->dev = &pdev->dev;
  449. port->type = PORT_MVEBU;
  450. port->ops = &mvebu_uart_ops;
  451. port->regshift = 0;
  452. port->fifosize = 32;
  453. port->iotype = UPIO_MEM32;
  454. port->flags = UPF_FIXED_PORT;
  455. port->line = 0; /* single port: force line number to 0 */
  456. port->irq = irq->start;
  457. port->irqflags = 0;
  458. port->mapbase = reg->start;
  459. port->membase = devm_ioremap_resource(&pdev->dev, reg);
  460. if (IS_ERR(port->membase))
  461. return -PTR_ERR(port->membase);
  462. data = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart_data),
  463. GFP_KERNEL);
  464. if (!data)
  465. return -ENOMEM;
  466. data->port = port;
  467. port->private_data = data;
  468. platform_set_drvdata(pdev, data);
  469. ret = uart_add_one_port(&mvebu_uart_driver, port);
  470. if (ret)
  471. return ret;
  472. return 0;
  473. }
  474. /* Match table for of_platform binding */
  475. static const struct of_device_id mvebu_uart_of_match[] = {
  476. { .compatible = "marvell,armada-3700-uart", },
  477. {}
  478. };
  479. static struct platform_driver mvebu_uart_platform_driver = {
  480. .probe = mvebu_uart_probe,
  481. .driver = {
  482. .name = "mvebu-uart",
  483. .of_match_table = of_match_ptr(mvebu_uart_of_match),
  484. .suppress_bind_attrs = true,
  485. },
  486. };
  487. static int __init mvebu_uart_init(void)
  488. {
  489. int ret;
  490. ret = uart_register_driver(&mvebu_uart_driver);
  491. if (ret)
  492. return ret;
  493. ret = platform_driver_register(&mvebu_uart_platform_driver);
  494. if (ret)
  495. uart_unregister_driver(&mvebu_uart_driver);
  496. return ret;
  497. }
  498. arch_initcall(mvebu_uart_init);