ps3-lpm.c 31 KB

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  1. /*
  2. * PS3 Logical Performance Monitor.
  3. *
  4. * Copyright (C) 2007 Sony Computer Entertainment Inc.
  5. * Copyright 2007 Sony Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/slab.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/uaccess.h>
  25. #include <asm/smp.h>
  26. #include <asm/time.h>
  27. #include <asm/ps3.h>
  28. #include <asm/lv1call.h>
  29. #include <asm/cell-pmu.h>
  30. /* BOOKMARK tag macros */
  31. #define PS3_PM_BOOKMARK_START 0x8000000000000000ULL
  32. #define PS3_PM_BOOKMARK_STOP 0x4000000000000000ULL
  33. #define PS3_PM_BOOKMARK_TAG_KERNEL 0x1000000000000000ULL
  34. #define PS3_PM_BOOKMARK_TAG_USER 0x3000000000000000ULL
  35. #define PS3_PM_BOOKMARK_TAG_MASK_HI 0xF000000000000000ULL
  36. #define PS3_PM_BOOKMARK_TAG_MASK_LO 0x0F00000000000000ULL
  37. /* CBE PM CONTROL register macros */
  38. #define PS3_PM_CONTROL_PPU_TH0_BOOKMARK 0x00001000
  39. #define PS3_PM_CONTROL_PPU_TH1_BOOKMARK 0x00000800
  40. #define PS3_PM_CONTROL_PPU_COUNT_MODE_MASK 0x000C0000
  41. #define PS3_PM_CONTROL_PPU_COUNT_MODE_PROBLEM 0x00080000
  42. #define PS3_WRITE_PM_MASK 0xFFFFFFFFFFFFFFFFULL
  43. /* CBE PM START STOP register macros */
  44. #define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START 0x02000000
  45. #define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START 0x01000000
  46. #define PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP 0x00020000
  47. #define PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP 0x00010000
  48. #define PS3_PM_START_STOP_START_MASK 0xFF000000
  49. #define PS3_PM_START_STOP_STOP_MASK 0x00FF0000
  50. /* CBE PM COUNTER register macres */
  51. #define PS3_PM_COUNTER_MASK_HI 0xFFFFFFFF00000000ULL
  52. #define PS3_PM_COUNTER_MASK_LO 0x00000000FFFFFFFFULL
  53. /* BASE SIGNAL GROUP NUMBER macros */
  54. #define PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER 0
  55. #define PM_ISLAND2_SIGNAL_GROUP_NUMBER1 6
  56. #define PM_ISLAND2_SIGNAL_GROUP_NUMBER2 7
  57. #define PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER 7
  58. #define PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER 15
  59. #define PM_SPU_TRIGGER_SIGNAL_GROUP_NUMBER 17
  60. #define PM_SPU_EVENT_SIGNAL_GROUP_NUMBER 18
  61. #define PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER 18
  62. #define PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER 24
  63. #define PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER 49
  64. #define PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER 52
  65. #define PM_SIG_GROUP_SPU 41
  66. #define PM_SIG_GROUP_SPU_TRIGGER 42
  67. #define PM_SIG_GROUP_SPU_EVENT 43
  68. #define PM_SIG_GROUP_MFC_MAX 60
  69. /**
  70. * struct ps3_lpm_shadow_regs - Performance monitor shadow registers.
  71. *
  72. * @pm_control: Shadow of the processor's pm_control register.
  73. * @pm_start_stop: Shadow of the processor's pm_start_stop register.
  74. * @group_control: Shadow of the processor's group_control register.
  75. * @debug_bus_control: Shadow of the processor's debug_bus_control register.
  76. *
  77. * The logical performance monitor provides a write-only interface to
  78. * these processor registers. These shadow variables cache the processor
  79. * register values for reading.
  80. *
  81. * The initial value of the shadow registers at lpm creation is
  82. * PS3_LPM_SHADOW_REG_INIT.
  83. */
  84. struct ps3_lpm_shadow_regs {
  85. u64 pm_control;
  86. u64 pm_start_stop;
  87. u64 group_control;
  88. u64 debug_bus_control;
  89. };
  90. #define PS3_LPM_SHADOW_REG_INIT 0xFFFFFFFF00000000ULL
  91. /**
  92. * struct ps3_lpm_priv - Private lpm device data.
  93. *
  94. * @open: An atomic variable indicating the lpm driver has been opened.
  95. * @rights: The lpm rigths granted by the system policy module. A logical
  96. * OR of enum ps3_lpm_rights.
  97. * @node_id: The node id of a BE processor whose performance monitor this
  98. * lpar has the right to use.
  99. * @pu_id: The lv1 id of the logical PU.
  100. * @lpm_id: The lv1 id of this lpm instance.
  101. * @outlet_id: The outlet created by lv1 for this lpm instance.
  102. * @tb_count: The number of bytes of data held in the lv1 trace buffer.
  103. * @tb_cache: Kernel buffer to receive the data from the lv1 trace buffer.
  104. * Must be 128 byte aligned.
  105. * @tb_cache_size: Size of the kernel @tb_cache buffer. Must be 128 byte
  106. * aligned.
  107. * @tb_cache_internal: An unaligned buffer allocated by this driver to be
  108. * used for the trace buffer cache when ps3_lpm_open() is called with a
  109. * NULL tb_cache argument. Otherwise unused.
  110. * @shadow: Processor register shadow of type struct ps3_lpm_shadow_regs.
  111. * @sbd: The struct ps3_system_bus_device attached to this driver.
  112. *
  113. * The trace buffer is a buffer allocated and used internally to the lv1
  114. * hypervisor to collect trace data. The trace buffer cache is a guest
  115. * buffer that accepts the trace data from the trace buffer.
  116. */
  117. struct ps3_lpm_priv {
  118. atomic_t open;
  119. u64 rights;
  120. u64 node_id;
  121. u64 pu_id;
  122. u64 lpm_id;
  123. u64 outlet_id;
  124. u64 tb_count;
  125. void *tb_cache;
  126. u64 tb_cache_size;
  127. void *tb_cache_internal;
  128. struct ps3_lpm_shadow_regs shadow;
  129. struct ps3_system_bus_device *sbd;
  130. };
  131. enum {
  132. PS3_LPM_DEFAULT_TB_CACHE_SIZE = 0x4000,
  133. };
  134. /**
  135. * lpm_priv - Static instance of the lpm data.
  136. *
  137. * Since the exported routines don't support the notion of a device
  138. * instance we need to hold the instance in this static variable
  139. * and then only allow at most one instance at a time to be created.
  140. */
  141. static struct ps3_lpm_priv *lpm_priv;
  142. static struct device *sbd_core(void)
  143. {
  144. BUG_ON(!lpm_priv || !lpm_priv->sbd);
  145. return &lpm_priv->sbd->core;
  146. }
  147. /**
  148. * use_start_stop_bookmark - Enable the PPU bookmark trace.
  149. *
  150. * And it enables PPU bookmark triggers ONLY if the other triggers are not set.
  151. * The start/stop bookmarks are inserted at ps3_enable_pm() and ps3_disable_pm()
  152. * to start/stop LPM.
  153. *
  154. * Used to get good quality of the performance counter.
  155. */
  156. enum {use_start_stop_bookmark = 1,};
  157. void ps3_set_bookmark(u64 bookmark)
  158. {
  159. /*
  160. * As per the PPE book IV, to avoid bookmark loss there must
  161. * not be a traced branch within 10 cycles of setting the
  162. * SPRN_BKMK register. The actual text is unclear if 'within'
  163. * includes cycles before the call.
  164. */
  165. asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
  166. mtspr(SPRN_BKMK, bookmark);
  167. asm volatile("nop;nop;nop;nop;nop;nop;nop;nop;nop;");
  168. }
  169. EXPORT_SYMBOL_GPL(ps3_set_bookmark);
  170. void ps3_set_pm_bookmark(u64 tag, u64 incident, u64 th_id)
  171. {
  172. u64 bookmark;
  173. bookmark = (get_tb() & 0x00000000FFFFFFFFULL) |
  174. PS3_PM_BOOKMARK_TAG_KERNEL;
  175. bookmark = ((tag << 56) & PS3_PM_BOOKMARK_TAG_MASK_LO) |
  176. (incident << 48) | (th_id << 32) | bookmark;
  177. ps3_set_bookmark(bookmark);
  178. }
  179. EXPORT_SYMBOL_GPL(ps3_set_pm_bookmark);
  180. /**
  181. * ps3_read_phys_ctr - Read physical counter registers.
  182. *
  183. * Each physical counter can act as one 32 bit counter or as two 16 bit
  184. * counters.
  185. */
  186. u32 ps3_read_phys_ctr(u32 cpu, u32 phys_ctr)
  187. {
  188. int result;
  189. u64 counter0415;
  190. u64 counter2637;
  191. if (phys_ctr >= NR_PHYS_CTRS) {
  192. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  193. __LINE__, phys_ctr);
  194. return 0;
  195. }
  196. result = lv1_set_lpm_counter(lpm_priv->lpm_id, 0, 0, 0, 0, &counter0415,
  197. &counter2637);
  198. if (result) {
  199. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
  200. "phys_ctr %u, %s\n", __func__, __LINE__, phys_ctr,
  201. ps3_result(result));
  202. return 0;
  203. }
  204. switch (phys_ctr) {
  205. case 0:
  206. return counter0415 >> 32;
  207. case 1:
  208. return counter0415 & PS3_PM_COUNTER_MASK_LO;
  209. case 2:
  210. return counter2637 >> 32;
  211. case 3:
  212. return counter2637 & PS3_PM_COUNTER_MASK_LO;
  213. default:
  214. BUG();
  215. }
  216. return 0;
  217. }
  218. EXPORT_SYMBOL_GPL(ps3_read_phys_ctr);
  219. /**
  220. * ps3_write_phys_ctr - Write physical counter registers.
  221. *
  222. * Each physical counter can act as one 32 bit counter or as two 16 bit
  223. * counters.
  224. */
  225. void ps3_write_phys_ctr(u32 cpu, u32 phys_ctr, u32 val)
  226. {
  227. u64 counter0415;
  228. u64 counter0415_mask;
  229. u64 counter2637;
  230. u64 counter2637_mask;
  231. int result;
  232. if (phys_ctr >= NR_PHYS_CTRS) {
  233. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  234. __LINE__, phys_ctr);
  235. return;
  236. }
  237. switch (phys_ctr) {
  238. case 0:
  239. counter0415 = (u64)val << 32;
  240. counter0415_mask = PS3_PM_COUNTER_MASK_HI;
  241. counter2637 = 0x0;
  242. counter2637_mask = 0x0;
  243. break;
  244. case 1:
  245. counter0415 = (u64)val;
  246. counter0415_mask = PS3_PM_COUNTER_MASK_LO;
  247. counter2637 = 0x0;
  248. counter2637_mask = 0x0;
  249. break;
  250. case 2:
  251. counter0415 = 0x0;
  252. counter0415_mask = 0x0;
  253. counter2637 = (u64)val << 32;
  254. counter2637_mask = PS3_PM_COUNTER_MASK_HI;
  255. break;
  256. case 3:
  257. counter0415 = 0x0;
  258. counter0415_mask = 0x0;
  259. counter2637 = (u64)val;
  260. counter2637_mask = PS3_PM_COUNTER_MASK_LO;
  261. break;
  262. default:
  263. BUG();
  264. }
  265. result = lv1_set_lpm_counter(lpm_priv->lpm_id,
  266. counter0415, counter0415_mask,
  267. counter2637, counter2637_mask,
  268. &counter0415, &counter2637);
  269. if (result)
  270. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter failed: "
  271. "phys_ctr %u, val %u, %s\n", __func__, __LINE__,
  272. phys_ctr, val, ps3_result(result));
  273. }
  274. EXPORT_SYMBOL_GPL(ps3_write_phys_ctr);
  275. /**
  276. * ps3_read_ctr - Read counter.
  277. *
  278. * Read 16 or 32 bits depending on the current size of the counter.
  279. * Counters 4, 5, 6 & 7 are always 16 bit.
  280. */
  281. u32 ps3_read_ctr(u32 cpu, u32 ctr)
  282. {
  283. u32 val;
  284. u32 phys_ctr = ctr & (NR_PHYS_CTRS - 1);
  285. val = ps3_read_phys_ctr(cpu, phys_ctr);
  286. if (ps3_get_ctr_size(cpu, phys_ctr) == 16)
  287. val = (ctr < NR_PHYS_CTRS) ? (val >> 16) : (val & 0xffff);
  288. return val;
  289. }
  290. EXPORT_SYMBOL_GPL(ps3_read_ctr);
  291. /**
  292. * ps3_write_ctr - Write counter.
  293. *
  294. * Write 16 or 32 bits depending on the current size of the counter.
  295. * Counters 4, 5, 6 & 7 are always 16 bit.
  296. */
  297. void ps3_write_ctr(u32 cpu, u32 ctr, u32 val)
  298. {
  299. u32 phys_ctr;
  300. u32 phys_val;
  301. phys_ctr = ctr & (NR_PHYS_CTRS - 1);
  302. if (ps3_get_ctr_size(cpu, phys_ctr) == 16) {
  303. phys_val = ps3_read_phys_ctr(cpu, phys_ctr);
  304. if (ctr < NR_PHYS_CTRS)
  305. val = (val << 16) | (phys_val & 0xffff);
  306. else
  307. val = (val & 0xffff) | (phys_val & 0xffff0000);
  308. }
  309. ps3_write_phys_ctr(cpu, phys_ctr, val);
  310. }
  311. EXPORT_SYMBOL_GPL(ps3_write_ctr);
  312. /**
  313. * ps3_read_pm07_control - Read counter control registers.
  314. *
  315. * Each logical counter has a corresponding control register.
  316. */
  317. u32 ps3_read_pm07_control(u32 cpu, u32 ctr)
  318. {
  319. return 0;
  320. }
  321. EXPORT_SYMBOL_GPL(ps3_read_pm07_control);
  322. /**
  323. * ps3_write_pm07_control - Write counter control registers.
  324. *
  325. * Each logical counter has a corresponding control register.
  326. */
  327. void ps3_write_pm07_control(u32 cpu, u32 ctr, u32 val)
  328. {
  329. int result;
  330. static const u64 mask = 0xFFFFFFFFFFFFFFFFULL;
  331. u64 old_value;
  332. if (ctr >= NR_CTRS) {
  333. dev_dbg(sbd_core(), "%s:%u: ctr too big: %u\n", __func__,
  334. __LINE__, ctr);
  335. return;
  336. }
  337. result = lv1_set_lpm_counter_control(lpm_priv->lpm_id, ctr, val, mask,
  338. &old_value);
  339. if (result)
  340. dev_err(sbd_core(), "%s:%u: lv1_set_lpm_counter_control "
  341. "failed: ctr %u, %s\n", __func__, __LINE__, ctr,
  342. ps3_result(result));
  343. }
  344. EXPORT_SYMBOL_GPL(ps3_write_pm07_control);
  345. /**
  346. * ps3_read_pm - Read Other LPM control registers.
  347. */
  348. u32 ps3_read_pm(u32 cpu, enum pm_reg_name reg)
  349. {
  350. int result = 0;
  351. u64 val = 0;
  352. switch (reg) {
  353. case pm_control:
  354. return lpm_priv->shadow.pm_control;
  355. case trace_address:
  356. return CBE_PM_TRACE_BUF_EMPTY;
  357. case pm_start_stop:
  358. return lpm_priv->shadow.pm_start_stop;
  359. case pm_interval:
  360. result = lv1_set_lpm_interval(lpm_priv->lpm_id, 0, 0, &val);
  361. if (result) {
  362. val = 0;
  363. dev_dbg(sbd_core(), "%s:%u: lv1 set_interval failed: "
  364. "reg %u, %s\n", __func__, __LINE__, reg,
  365. ps3_result(result));
  366. }
  367. return (u32)val;
  368. case group_control:
  369. return lpm_priv->shadow.group_control;
  370. case debug_bus_control:
  371. return lpm_priv->shadow.debug_bus_control;
  372. case pm_status:
  373. result = lv1_get_lpm_interrupt_status(lpm_priv->lpm_id,
  374. &val);
  375. if (result) {
  376. val = 0;
  377. dev_dbg(sbd_core(), "%s:%u: lv1 get_lpm_status failed: "
  378. "reg %u, %s\n", __func__, __LINE__, reg,
  379. ps3_result(result));
  380. }
  381. return (u32)val;
  382. case ext_tr_timer:
  383. return 0;
  384. default:
  385. dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
  386. __LINE__, reg);
  387. BUG();
  388. break;
  389. }
  390. return 0;
  391. }
  392. EXPORT_SYMBOL_GPL(ps3_read_pm);
  393. /**
  394. * ps3_write_pm - Write Other LPM control registers.
  395. */
  396. void ps3_write_pm(u32 cpu, enum pm_reg_name reg, u32 val)
  397. {
  398. int result = 0;
  399. u64 dummy;
  400. switch (reg) {
  401. case group_control:
  402. if (val != lpm_priv->shadow.group_control)
  403. result = lv1_set_lpm_group_control(lpm_priv->lpm_id,
  404. val,
  405. PS3_WRITE_PM_MASK,
  406. &dummy);
  407. lpm_priv->shadow.group_control = val;
  408. break;
  409. case debug_bus_control:
  410. if (val != lpm_priv->shadow.debug_bus_control)
  411. result = lv1_set_lpm_debug_bus_control(lpm_priv->lpm_id,
  412. val,
  413. PS3_WRITE_PM_MASK,
  414. &dummy);
  415. lpm_priv->shadow.debug_bus_control = val;
  416. break;
  417. case pm_control:
  418. if (use_start_stop_bookmark)
  419. val |= (PS3_PM_CONTROL_PPU_TH0_BOOKMARK |
  420. PS3_PM_CONTROL_PPU_TH1_BOOKMARK);
  421. if (val != lpm_priv->shadow.pm_control)
  422. result = lv1_set_lpm_general_control(lpm_priv->lpm_id,
  423. val,
  424. PS3_WRITE_PM_MASK,
  425. 0, 0, &dummy,
  426. &dummy);
  427. lpm_priv->shadow.pm_control = val;
  428. break;
  429. case pm_interval:
  430. result = lv1_set_lpm_interval(lpm_priv->lpm_id, val,
  431. PS3_WRITE_PM_MASK, &dummy);
  432. break;
  433. case pm_start_stop:
  434. if (val != lpm_priv->shadow.pm_start_stop)
  435. result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
  436. val,
  437. PS3_WRITE_PM_MASK,
  438. &dummy);
  439. lpm_priv->shadow.pm_start_stop = val;
  440. break;
  441. case trace_address:
  442. case ext_tr_timer:
  443. case pm_status:
  444. break;
  445. default:
  446. dev_dbg(sbd_core(), "%s:%u: unknown reg: %d\n", __func__,
  447. __LINE__, reg);
  448. BUG();
  449. break;
  450. }
  451. if (result)
  452. dev_err(sbd_core(), "%s:%u: lv1 set_control failed: "
  453. "reg %u, %s\n", __func__, __LINE__, reg,
  454. ps3_result(result));
  455. }
  456. EXPORT_SYMBOL_GPL(ps3_write_pm);
  457. /**
  458. * ps3_get_ctr_size - Get the size of a physical counter.
  459. *
  460. * Returns either 16 or 32.
  461. */
  462. u32 ps3_get_ctr_size(u32 cpu, u32 phys_ctr)
  463. {
  464. u32 pm_ctrl;
  465. if (phys_ctr >= NR_PHYS_CTRS) {
  466. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  467. __LINE__, phys_ctr);
  468. return 0;
  469. }
  470. pm_ctrl = ps3_read_pm(cpu, pm_control);
  471. return (pm_ctrl & CBE_PM_16BIT_CTR(phys_ctr)) ? 16 : 32;
  472. }
  473. EXPORT_SYMBOL_GPL(ps3_get_ctr_size);
  474. /**
  475. * ps3_set_ctr_size - Set the size of a physical counter to 16 or 32 bits.
  476. */
  477. void ps3_set_ctr_size(u32 cpu, u32 phys_ctr, u32 ctr_size)
  478. {
  479. u32 pm_ctrl;
  480. if (phys_ctr >= NR_PHYS_CTRS) {
  481. dev_dbg(sbd_core(), "%s:%u: phys_ctr too big: %u\n", __func__,
  482. __LINE__, phys_ctr);
  483. return;
  484. }
  485. pm_ctrl = ps3_read_pm(cpu, pm_control);
  486. switch (ctr_size) {
  487. case 16:
  488. pm_ctrl |= CBE_PM_16BIT_CTR(phys_ctr);
  489. ps3_write_pm(cpu, pm_control, pm_ctrl);
  490. break;
  491. case 32:
  492. pm_ctrl &= ~CBE_PM_16BIT_CTR(phys_ctr);
  493. ps3_write_pm(cpu, pm_control, pm_ctrl);
  494. break;
  495. default:
  496. BUG();
  497. }
  498. }
  499. EXPORT_SYMBOL_GPL(ps3_set_ctr_size);
  500. static u64 pm_translate_signal_group_number_on_island2(u64 subgroup)
  501. {
  502. if (subgroup == 2)
  503. subgroup = 3;
  504. if (subgroup <= 6)
  505. return PM_ISLAND2_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  506. else if (subgroup == 7)
  507. return PM_ISLAND2_SIGNAL_GROUP_NUMBER1;
  508. else
  509. return PM_ISLAND2_SIGNAL_GROUP_NUMBER2;
  510. }
  511. static u64 pm_translate_signal_group_number_on_island3(u64 subgroup)
  512. {
  513. switch (subgroup) {
  514. case 2:
  515. case 3:
  516. case 4:
  517. subgroup += 2;
  518. break;
  519. case 5:
  520. subgroup = 8;
  521. break;
  522. default:
  523. break;
  524. }
  525. return PM_ISLAND3_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  526. }
  527. static u64 pm_translate_signal_group_number_on_island4(u64 subgroup)
  528. {
  529. return PM_ISLAND4_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  530. }
  531. static u64 pm_translate_signal_group_number_on_island5(u64 subgroup)
  532. {
  533. switch (subgroup) {
  534. case 3:
  535. subgroup = 4;
  536. break;
  537. case 4:
  538. subgroup = 6;
  539. break;
  540. default:
  541. break;
  542. }
  543. return PM_ISLAND5_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  544. }
  545. static u64 pm_translate_signal_group_number_on_island6(u64 subgroup,
  546. u64 subsubgroup)
  547. {
  548. switch (subgroup) {
  549. case 3:
  550. case 4:
  551. case 5:
  552. subgroup += 1;
  553. break;
  554. default:
  555. break;
  556. }
  557. switch (subsubgroup) {
  558. case 4:
  559. case 5:
  560. case 6:
  561. subsubgroup += 2;
  562. break;
  563. case 7:
  564. case 8:
  565. case 9:
  566. case 10:
  567. subsubgroup += 4;
  568. break;
  569. case 11:
  570. case 12:
  571. case 13:
  572. subsubgroup += 5;
  573. break;
  574. default:
  575. break;
  576. }
  577. if (subgroup <= 5)
  578. return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup);
  579. else
  580. return (PM_ISLAND6_BASE_SIGNAL_GROUP_NUMBER + subgroup
  581. + subsubgroup - 1);
  582. }
  583. static u64 pm_translate_signal_group_number_on_island7(u64 subgroup)
  584. {
  585. return PM_ISLAND7_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  586. }
  587. static u64 pm_translate_signal_group_number_on_island8(u64 subgroup)
  588. {
  589. return PM_ISLAND8_BASE_SIGNAL_GROUP_NUMBER + subgroup;
  590. }
  591. static u64 pm_signal_group_to_ps3_lv1_signal_group(u64 group)
  592. {
  593. u64 island;
  594. u64 subgroup;
  595. u64 subsubgroup;
  596. subgroup = 0;
  597. subsubgroup = 0;
  598. island = 0;
  599. if (group < 1000) {
  600. if (group < 100) {
  601. if (20 <= group && group < 30) {
  602. island = 2;
  603. subgroup = group - 20;
  604. } else if (30 <= group && group < 40) {
  605. island = 3;
  606. subgroup = group - 30;
  607. } else if (40 <= group && group < 50) {
  608. island = 4;
  609. subgroup = group - 40;
  610. } else if (50 <= group && group < 60) {
  611. island = 5;
  612. subgroup = group - 50;
  613. } else if (60 <= group && group < 70) {
  614. island = 6;
  615. subgroup = group - 60;
  616. } else if (70 <= group && group < 80) {
  617. island = 7;
  618. subgroup = group - 70;
  619. } else if (80 <= group && group < 90) {
  620. island = 8;
  621. subgroup = group - 80;
  622. }
  623. } else if (200 <= group && group < 300) {
  624. island = 2;
  625. subgroup = group - 200;
  626. } else if (600 <= group && group < 700) {
  627. island = 6;
  628. subgroup = 5;
  629. subsubgroup = group - 650;
  630. }
  631. } else if (6000 <= group && group < 7000) {
  632. island = 6;
  633. subgroup = 5;
  634. subsubgroup = group - 6500;
  635. }
  636. switch (island) {
  637. case 2:
  638. return pm_translate_signal_group_number_on_island2(subgroup);
  639. case 3:
  640. return pm_translate_signal_group_number_on_island3(subgroup);
  641. case 4:
  642. return pm_translate_signal_group_number_on_island4(subgroup);
  643. case 5:
  644. return pm_translate_signal_group_number_on_island5(subgroup);
  645. case 6:
  646. return pm_translate_signal_group_number_on_island6(subgroup,
  647. subsubgroup);
  648. case 7:
  649. return pm_translate_signal_group_number_on_island7(subgroup);
  650. case 8:
  651. return pm_translate_signal_group_number_on_island8(subgroup);
  652. default:
  653. dev_dbg(sbd_core(), "%s:%u: island not found: %llu\n", __func__,
  654. __LINE__, group);
  655. BUG();
  656. break;
  657. }
  658. return 0;
  659. }
  660. static u64 pm_bus_word_to_ps3_lv1_bus_word(u8 word)
  661. {
  662. switch (word) {
  663. case 1:
  664. return 0xF000;
  665. case 2:
  666. return 0x0F00;
  667. case 4:
  668. return 0x00F0;
  669. case 8:
  670. default:
  671. return 0x000F;
  672. }
  673. }
  674. static int __ps3_set_signal(u64 lv1_signal_group, u64 bus_select,
  675. u64 signal_select, u64 attr1, u64 attr2, u64 attr3)
  676. {
  677. int ret;
  678. ret = lv1_set_lpm_signal(lpm_priv->lpm_id, lv1_signal_group, bus_select,
  679. signal_select, attr1, attr2, attr3);
  680. if (ret)
  681. dev_err(sbd_core(),
  682. "%s:%u: error:%d 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx\n",
  683. __func__, __LINE__, ret, lv1_signal_group, bus_select,
  684. signal_select, attr1, attr2, attr3);
  685. return ret;
  686. }
  687. int ps3_set_signal(u64 signal_group, u8 signal_bit, u16 sub_unit,
  688. u8 bus_word)
  689. {
  690. int ret;
  691. u64 lv1_signal_group;
  692. u64 bus_select;
  693. u64 signal_select;
  694. u64 attr1, attr2, attr3;
  695. if (signal_group == 0)
  696. return __ps3_set_signal(0, 0, 0, 0, 0, 0);
  697. lv1_signal_group =
  698. pm_signal_group_to_ps3_lv1_signal_group(signal_group);
  699. bus_select = pm_bus_word_to_ps3_lv1_bus_word(bus_word);
  700. switch (signal_group) {
  701. case PM_SIG_GROUP_SPU_TRIGGER:
  702. signal_select = 1;
  703. signal_select = signal_select << (63 - signal_bit);
  704. break;
  705. case PM_SIG_GROUP_SPU_EVENT:
  706. signal_select = 1;
  707. signal_select = (signal_select << (63 - signal_bit)) | 0x3;
  708. break;
  709. default:
  710. signal_select = 0;
  711. break;
  712. }
  713. /*
  714. * 0: physical object.
  715. * 1: logical object.
  716. * This parameter is only used for the PPE and SPE signals.
  717. */
  718. attr1 = 1;
  719. /*
  720. * This parameter is used to specify the target physical/logical
  721. * PPE/SPE object.
  722. */
  723. if (PM_SIG_GROUP_SPU <= signal_group &&
  724. signal_group < PM_SIG_GROUP_MFC_MAX)
  725. attr2 = sub_unit;
  726. else
  727. attr2 = lpm_priv->pu_id;
  728. /*
  729. * This parameter is only used for setting the SPE signal.
  730. */
  731. attr3 = 0;
  732. ret = __ps3_set_signal(lv1_signal_group, bus_select, signal_select,
  733. attr1, attr2, attr3);
  734. if (ret)
  735. dev_err(sbd_core(), "%s:%u: __ps3_set_signal failed: %d\n",
  736. __func__, __LINE__, ret);
  737. return ret;
  738. }
  739. EXPORT_SYMBOL_GPL(ps3_set_signal);
  740. u32 ps3_get_hw_thread_id(int cpu)
  741. {
  742. return get_hard_smp_processor_id(cpu);
  743. }
  744. EXPORT_SYMBOL_GPL(ps3_get_hw_thread_id);
  745. /**
  746. * ps3_enable_pm - Enable the entire performance monitoring unit.
  747. *
  748. * When we enable the LPM, all pending writes to counters get committed.
  749. */
  750. void ps3_enable_pm(u32 cpu)
  751. {
  752. int result;
  753. u64 tmp;
  754. int insert_bookmark = 0;
  755. lpm_priv->tb_count = 0;
  756. if (use_start_stop_bookmark) {
  757. if (!(lpm_priv->shadow.pm_start_stop &
  758. (PS3_PM_START_STOP_START_MASK
  759. | PS3_PM_START_STOP_STOP_MASK))) {
  760. result = lv1_set_lpm_trigger_control(lpm_priv->lpm_id,
  761. (PS3_PM_START_STOP_PPU_TH0_BOOKMARK_START |
  762. PS3_PM_START_STOP_PPU_TH1_BOOKMARK_START |
  763. PS3_PM_START_STOP_PPU_TH0_BOOKMARK_STOP |
  764. PS3_PM_START_STOP_PPU_TH1_BOOKMARK_STOP),
  765. 0xFFFFFFFFFFFFFFFFULL, &tmp);
  766. if (result)
  767. dev_err(sbd_core(), "%s:%u: "
  768. "lv1_set_lpm_trigger_control failed: "
  769. "%s\n", __func__, __LINE__,
  770. ps3_result(result));
  771. insert_bookmark = !result;
  772. }
  773. }
  774. result = lv1_start_lpm(lpm_priv->lpm_id);
  775. if (result)
  776. dev_err(sbd_core(), "%s:%u: lv1_start_lpm failed: %s\n",
  777. __func__, __LINE__, ps3_result(result));
  778. if (use_start_stop_bookmark && !result && insert_bookmark)
  779. ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_START);
  780. }
  781. EXPORT_SYMBOL_GPL(ps3_enable_pm);
  782. /**
  783. * ps3_disable_pm - Disable the entire performance monitoring unit.
  784. */
  785. void ps3_disable_pm(u32 cpu)
  786. {
  787. int result;
  788. u64 tmp;
  789. ps3_set_bookmark(get_tb() | PS3_PM_BOOKMARK_STOP);
  790. result = lv1_stop_lpm(lpm_priv->lpm_id, &tmp);
  791. if (result) {
  792. if (result != LV1_WRONG_STATE)
  793. dev_err(sbd_core(), "%s:%u: lv1_stop_lpm failed: %s\n",
  794. __func__, __LINE__, ps3_result(result));
  795. return;
  796. }
  797. lpm_priv->tb_count = tmp;
  798. dev_dbg(sbd_core(), "%s:%u: tb_count %llu (%llxh)\n", __func__, __LINE__,
  799. lpm_priv->tb_count, lpm_priv->tb_count);
  800. }
  801. EXPORT_SYMBOL_GPL(ps3_disable_pm);
  802. /**
  803. * ps3_lpm_copy_tb - Copy data from the trace buffer to a kernel buffer.
  804. * @offset: Offset in bytes from the start of the trace buffer.
  805. * @buf: Copy destination.
  806. * @count: Maximum count of bytes to copy.
  807. * @bytes_copied: Pointer to a variable that will receive the number of
  808. * bytes copied to @buf.
  809. *
  810. * On error @buf will contain any successfully copied trace buffer data
  811. * and bytes_copied will be set to the number of bytes successfully copied.
  812. */
  813. int ps3_lpm_copy_tb(unsigned long offset, void *buf, unsigned long count,
  814. unsigned long *bytes_copied)
  815. {
  816. int result;
  817. *bytes_copied = 0;
  818. if (!lpm_priv->tb_cache)
  819. return -EPERM;
  820. if (offset >= lpm_priv->tb_count)
  821. return 0;
  822. count = min_t(u64, count, lpm_priv->tb_count - offset);
  823. while (*bytes_copied < count) {
  824. const unsigned long request = count - *bytes_copied;
  825. u64 tmp;
  826. result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
  827. request, &tmp);
  828. if (result) {
  829. dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
  830. __func__, __LINE__, request, offset);
  831. dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
  832. "failed: %s\n", __func__, __LINE__,
  833. ps3_result(result));
  834. return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
  835. }
  836. memcpy(buf, lpm_priv->tb_cache, tmp);
  837. buf += tmp;
  838. *bytes_copied += tmp;
  839. offset += tmp;
  840. }
  841. dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
  842. *bytes_copied);
  843. return 0;
  844. }
  845. EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb);
  846. /**
  847. * ps3_lpm_copy_tb_to_user - Copy data from the trace buffer to a user buffer.
  848. * @offset: Offset in bytes from the start of the trace buffer.
  849. * @buf: A __user copy destination.
  850. * @count: Maximum count of bytes to copy.
  851. * @bytes_copied: Pointer to a variable that will receive the number of
  852. * bytes copied to @buf.
  853. *
  854. * On error @buf will contain any successfully copied trace buffer data
  855. * and bytes_copied will be set to the number of bytes successfully copied.
  856. */
  857. int ps3_lpm_copy_tb_to_user(unsigned long offset, void __user *buf,
  858. unsigned long count, unsigned long *bytes_copied)
  859. {
  860. int result;
  861. *bytes_copied = 0;
  862. if (!lpm_priv->tb_cache)
  863. return -EPERM;
  864. if (offset >= lpm_priv->tb_count)
  865. return 0;
  866. count = min_t(u64, count, lpm_priv->tb_count - offset);
  867. while (*bytes_copied < count) {
  868. const unsigned long request = count - *bytes_copied;
  869. u64 tmp;
  870. result = lv1_copy_lpm_trace_buffer(lpm_priv->lpm_id, offset,
  871. request, &tmp);
  872. if (result) {
  873. dev_dbg(sbd_core(), "%s:%u: 0x%lx bytes at 0x%lx\n",
  874. __func__, __LINE__, request, offset);
  875. dev_err(sbd_core(), "%s:%u: lv1_copy_lpm_trace_buffer "
  876. "failed: %s\n", __func__, __LINE__,
  877. ps3_result(result));
  878. return result == LV1_WRONG_STATE ? -EBUSY : -EINVAL;
  879. }
  880. result = copy_to_user(buf, lpm_priv->tb_cache, tmp);
  881. if (result) {
  882. dev_dbg(sbd_core(), "%s:%u: 0x%llx bytes at 0x%p\n",
  883. __func__, __LINE__, tmp, buf);
  884. dev_err(sbd_core(), "%s:%u: copy_to_user failed: %d\n",
  885. __func__, __LINE__, result);
  886. return -EFAULT;
  887. }
  888. buf += tmp;
  889. *bytes_copied += tmp;
  890. offset += tmp;
  891. }
  892. dev_dbg(sbd_core(), "%s:%u: copied %lxh bytes\n", __func__, __LINE__,
  893. *bytes_copied);
  894. return 0;
  895. }
  896. EXPORT_SYMBOL_GPL(ps3_lpm_copy_tb_to_user);
  897. /**
  898. * ps3_get_and_clear_pm_interrupts -
  899. *
  900. * Clearing interrupts for the entire performance monitoring unit.
  901. * Reading pm_status clears the interrupt bits.
  902. */
  903. u32 ps3_get_and_clear_pm_interrupts(u32 cpu)
  904. {
  905. return ps3_read_pm(cpu, pm_status);
  906. }
  907. EXPORT_SYMBOL_GPL(ps3_get_and_clear_pm_interrupts);
  908. /**
  909. * ps3_enable_pm_interrupts -
  910. *
  911. * Enabling interrupts for the entire performance monitoring unit.
  912. * Enables the interrupt bits in the pm_status register.
  913. */
  914. void ps3_enable_pm_interrupts(u32 cpu, u32 thread, u32 mask)
  915. {
  916. if (mask)
  917. ps3_write_pm(cpu, pm_status, mask);
  918. }
  919. EXPORT_SYMBOL_GPL(ps3_enable_pm_interrupts);
  920. /**
  921. * ps3_enable_pm_interrupts -
  922. *
  923. * Disabling interrupts for the entire performance monitoring unit.
  924. */
  925. void ps3_disable_pm_interrupts(u32 cpu)
  926. {
  927. ps3_get_and_clear_pm_interrupts(cpu);
  928. ps3_write_pm(cpu, pm_status, 0);
  929. }
  930. EXPORT_SYMBOL_GPL(ps3_disable_pm_interrupts);
  931. /**
  932. * ps3_lpm_open - Open the logical performance monitor device.
  933. * @tb_type: Specifies the type of trace buffer lv1 should use for this lpm
  934. * instance, specified by one of enum ps3_lpm_tb_type.
  935. * @tb_cache: Optional user supplied buffer to use as the trace buffer cache.
  936. * If NULL, the driver will allocate and manage an internal buffer.
  937. * Unused when when @tb_type is PS3_LPM_TB_TYPE_NONE.
  938. * @tb_cache_size: The size in bytes of the user supplied @tb_cache buffer.
  939. * Unused when @tb_cache is NULL or @tb_type is PS3_LPM_TB_TYPE_NONE.
  940. */
  941. int ps3_lpm_open(enum ps3_lpm_tb_type tb_type, void *tb_cache,
  942. u64 tb_cache_size)
  943. {
  944. int result;
  945. u64 tb_size;
  946. BUG_ON(!lpm_priv);
  947. BUG_ON(tb_type != PS3_LPM_TB_TYPE_NONE
  948. && tb_type != PS3_LPM_TB_TYPE_INTERNAL);
  949. if (tb_type == PS3_LPM_TB_TYPE_NONE && tb_cache)
  950. dev_dbg(sbd_core(), "%s:%u: bad in vals\n", __func__, __LINE__);
  951. if (!atomic_add_unless(&lpm_priv->open, 1, 1)) {
  952. dev_dbg(sbd_core(), "%s:%u: busy\n", __func__, __LINE__);
  953. return -EBUSY;
  954. }
  955. /* Note tb_cache needs 128 byte alignment. */
  956. if (tb_type == PS3_LPM_TB_TYPE_NONE) {
  957. lpm_priv->tb_cache_size = 0;
  958. lpm_priv->tb_cache_internal = NULL;
  959. lpm_priv->tb_cache = NULL;
  960. } else if (tb_cache) {
  961. if (tb_cache != (void *)_ALIGN_UP((unsigned long)tb_cache, 128)
  962. || tb_cache_size != _ALIGN_UP(tb_cache_size, 128)) {
  963. dev_err(sbd_core(), "%s:%u: unaligned tb_cache\n",
  964. __func__, __LINE__);
  965. result = -EINVAL;
  966. goto fail_align;
  967. }
  968. lpm_priv->tb_cache_size = tb_cache_size;
  969. lpm_priv->tb_cache_internal = NULL;
  970. lpm_priv->tb_cache = tb_cache;
  971. } else {
  972. lpm_priv->tb_cache_size = PS3_LPM_DEFAULT_TB_CACHE_SIZE;
  973. lpm_priv->tb_cache_internal = kzalloc(
  974. lpm_priv->tb_cache_size + 127, GFP_KERNEL);
  975. if (!lpm_priv->tb_cache_internal) {
  976. dev_err(sbd_core(), "%s:%u: alloc internal tb_cache "
  977. "failed\n", __func__, __LINE__);
  978. result = -ENOMEM;
  979. goto fail_malloc;
  980. }
  981. lpm_priv->tb_cache = (void *)_ALIGN_UP(
  982. (unsigned long)lpm_priv->tb_cache_internal, 128);
  983. }
  984. result = lv1_construct_lpm(lpm_priv->node_id, tb_type, 0, 0,
  985. ps3_mm_phys_to_lpar(__pa(lpm_priv->tb_cache)),
  986. lpm_priv->tb_cache_size, &lpm_priv->lpm_id,
  987. &lpm_priv->outlet_id, &tb_size);
  988. if (result) {
  989. dev_err(sbd_core(), "%s:%u: lv1_construct_lpm failed: %s\n",
  990. __func__, __LINE__, ps3_result(result));
  991. result = -EINVAL;
  992. goto fail_construct;
  993. }
  994. lpm_priv->shadow.pm_control = PS3_LPM_SHADOW_REG_INIT;
  995. lpm_priv->shadow.pm_start_stop = PS3_LPM_SHADOW_REG_INIT;
  996. lpm_priv->shadow.group_control = PS3_LPM_SHADOW_REG_INIT;
  997. lpm_priv->shadow.debug_bus_control = PS3_LPM_SHADOW_REG_INIT;
  998. dev_dbg(sbd_core(), "%s:%u: lpm_id 0x%llx, outlet_id 0x%llx, "
  999. "tb_size 0x%llx\n", __func__, __LINE__, lpm_priv->lpm_id,
  1000. lpm_priv->outlet_id, tb_size);
  1001. return 0;
  1002. fail_construct:
  1003. kfree(lpm_priv->tb_cache_internal);
  1004. lpm_priv->tb_cache_internal = NULL;
  1005. fail_malloc:
  1006. fail_align:
  1007. atomic_dec(&lpm_priv->open);
  1008. return result;
  1009. }
  1010. EXPORT_SYMBOL_GPL(ps3_lpm_open);
  1011. /**
  1012. * ps3_lpm_close - Close the lpm device.
  1013. *
  1014. */
  1015. int ps3_lpm_close(void)
  1016. {
  1017. dev_dbg(sbd_core(), "%s:%u\n", __func__, __LINE__);
  1018. lv1_destruct_lpm(lpm_priv->lpm_id);
  1019. lpm_priv->lpm_id = 0;
  1020. kfree(lpm_priv->tb_cache_internal);
  1021. lpm_priv->tb_cache_internal = NULL;
  1022. atomic_dec(&lpm_priv->open);
  1023. return 0;
  1024. }
  1025. EXPORT_SYMBOL_GPL(ps3_lpm_close);
  1026. static int ps3_lpm_probe(struct ps3_system_bus_device *dev)
  1027. {
  1028. dev_dbg(&dev->core, " -> %s:%u\n", __func__, __LINE__);
  1029. if (lpm_priv) {
  1030. dev_info(&dev->core, "%s:%u: called twice\n",
  1031. __func__, __LINE__);
  1032. return -EBUSY;
  1033. }
  1034. lpm_priv = kzalloc(sizeof(*lpm_priv), GFP_KERNEL);
  1035. if (!lpm_priv)
  1036. return -ENOMEM;
  1037. lpm_priv->sbd = dev;
  1038. lpm_priv->node_id = dev->lpm.node_id;
  1039. lpm_priv->pu_id = dev->lpm.pu_id;
  1040. lpm_priv->rights = dev->lpm.rights;
  1041. dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
  1042. return 0;
  1043. }
  1044. static int ps3_lpm_remove(struct ps3_system_bus_device *dev)
  1045. {
  1046. dev_dbg(&dev->core, " -> %s:%u:\n", __func__, __LINE__);
  1047. ps3_lpm_close();
  1048. kfree(lpm_priv);
  1049. lpm_priv = NULL;
  1050. dev_info(&dev->core, " <- %s:%u:\n", __func__, __LINE__);
  1051. return 0;
  1052. }
  1053. static struct ps3_system_bus_driver ps3_lpm_driver = {
  1054. .match_id = PS3_MATCH_ID_LPM,
  1055. .core.name = "ps3-lpm",
  1056. .core.owner = THIS_MODULE,
  1057. .probe = ps3_lpm_probe,
  1058. .remove = ps3_lpm_remove,
  1059. .shutdown = ps3_lpm_remove,
  1060. };
  1061. static int __init ps3_lpm_init(void)
  1062. {
  1063. pr_debug("%s:%d:\n", __func__, __LINE__);
  1064. return ps3_system_bus_driver_register(&ps3_lpm_driver);
  1065. }
  1066. static void __exit ps3_lpm_exit(void)
  1067. {
  1068. pr_debug("%s:%d:\n", __func__, __LINE__);
  1069. ps3_system_bus_driver_unregister(&ps3_lpm_driver);
  1070. }
  1071. module_init(ps3_lpm_init);
  1072. module_exit(ps3_lpm_exit);
  1073. MODULE_LICENSE("GPL v2");
  1074. MODULE_DESCRIPTION("PS3 Logical Performance Monitor Driver");
  1075. MODULE_AUTHOR("Sony Corporation");
  1076. MODULE_ALIAS(PS3_MODULE_ALIAS_LPM);