sdhci-cns3xxx.c 2.7 KB

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  1. /*
  2. * SDHCI support for CNS3xxx SoC
  3. *
  4. * Copyright 2008 Cavium Networks
  5. * Copyright 2010 MontaVista Software, LLC.
  6. *
  7. * Authors: Scott Shu
  8. * Anton Vorontsov <avorontsov@mvista.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/mmc/host.h>
  17. #include <linux/module.h>
  18. #include "sdhci-pltfm.h"
  19. static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
  20. {
  21. return 150000000;
  22. }
  23. static void sdhci_cns3xxx_set_clock(struct sdhci_host *host, unsigned int clock)
  24. {
  25. struct device *dev = mmc_dev(host->mmc);
  26. int div = 1;
  27. u16 clk;
  28. unsigned long timeout;
  29. host->mmc->actual_clock = 0;
  30. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  31. if (clock == 0)
  32. return;
  33. while (host->max_clk / div > clock) {
  34. /*
  35. * On CNS3xxx divider grows linearly up to 4, and then
  36. * exponentially up to 256.
  37. */
  38. if (div < 4)
  39. div += 1;
  40. else if (div < 256)
  41. div *= 2;
  42. else
  43. break;
  44. }
  45. dev_dbg(dev, "desired SD clock: %d, actual: %d\n",
  46. clock, host->max_clk / div);
  47. /* Divide by 3 is special. */
  48. if (div != 3)
  49. div >>= 1;
  50. clk = div << SDHCI_DIVIDER_SHIFT;
  51. clk |= SDHCI_CLOCK_INT_EN;
  52. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  53. timeout = 20;
  54. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  55. & SDHCI_CLOCK_INT_STABLE)) {
  56. if (timeout == 0) {
  57. dev_warn(dev, "clock is unstable");
  58. break;
  59. }
  60. timeout--;
  61. mdelay(1);
  62. }
  63. clk |= SDHCI_CLOCK_CARD_EN;
  64. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  65. }
  66. static const struct sdhci_ops sdhci_cns3xxx_ops = {
  67. .get_max_clock = sdhci_cns3xxx_get_max_clk,
  68. .set_clock = sdhci_cns3xxx_set_clock,
  69. .set_bus_width = sdhci_set_bus_width,
  70. .reset = sdhci_reset,
  71. .set_uhs_signaling = sdhci_set_uhs_signaling,
  72. };
  73. static const struct sdhci_pltfm_data sdhci_cns3xxx_pdata = {
  74. .ops = &sdhci_cns3xxx_ops,
  75. .quirks = SDHCI_QUIRK_BROKEN_DMA |
  76. SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
  77. SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
  78. SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
  79. SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
  80. };
  81. static int sdhci_cns3xxx_probe(struct platform_device *pdev)
  82. {
  83. return sdhci_pltfm_register(pdev, &sdhci_cns3xxx_pdata, 0);
  84. }
  85. static struct platform_driver sdhci_cns3xxx_driver = {
  86. .driver = {
  87. .name = "sdhci-cns3xxx",
  88. .pm = &sdhci_pltfm_pmops,
  89. },
  90. .probe = sdhci_cns3xxx_probe,
  91. .remove = sdhci_pltfm_unregister,
  92. };
  93. module_platform_driver(sdhci_cns3xxx_driver);
  94. MODULE_DESCRIPTION("SDHCI driver for CNS3xxx");
  95. MODULE_AUTHOR("Scott Shu, "
  96. "Anton Vorontsov <avorontsov@mvista.com>");
  97. MODULE_LICENSE("GPL v2");