mxs-mmc.c 18 KB

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  1. /*
  2. * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
  3. * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
  4. *
  5. * Copyright 2008 Embedded Alley Solutions, Inc.
  6. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License along
  19. * with this program; if not, write to the Free Software Foundation, Inc.,
  20. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/of_gpio.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/delay.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/dmaengine.h>
  33. #include <linux/highmem.h>
  34. #include <linux/clk.h>
  35. #include <linux/err.h>
  36. #include <linux/completion.h>
  37. #include <linux/mmc/host.h>
  38. #include <linux/mmc/mmc.h>
  39. #include <linux/mmc/sdio.h>
  40. #include <linux/mmc/slot-gpio.h>
  41. #include <linux/gpio.h>
  42. #include <linux/regulator/consumer.h>
  43. #include <linux/module.h>
  44. #include <linux/stmp_device.h>
  45. #include <linux/spi/mxs-spi.h>
  46. #define DRIVER_NAME "mxs-mmc"
  47. #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
  48. BM_SSP_CTRL1_RESP_ERR_IRQ | \
  49. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
  50. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
  51. BM_SSP_CTRL1_DATA_CRC_IRQ | \
  52. BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
  53. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
  54. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
  55. /* card detect polling timeout */
  56. #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
  57. struct mxs_mmc_host {
  58. struct mxs_ssp ssp;
  59. struct mmc_host *mmc;
  60. struct mmc_request *mrq;
  61. struct mmc_command *cmd;
  62. struct mmc_data *data;
  63. unsigned char bus_width;
  64. spinlock_t lock;
  65. int sdio_irq_en;
  66. bool broken_cd;
  67. };
  68. static int mxs_mmc_get_cd(struct mmc_host *mmc)
  69. {
  70. struct mxs_mmc_host *host = mmc_priv(mmc);
  71. struct mxs_ssp *ssp = &host->ssp;
  72. int present, ret;
  73. if (host->broken_cd)
  74. return -ENOSYS;
  75. ret = mmc_gpio_get_cd(mmc);
  76. if (ret >= 0)
  77. return ret;
  78. present = mmc->caps & MMC_CAP_NEEDS_POLL ||
  79. !(readl(ssp->base + HW_SSP_STATUS(ssp)) &
  80. BM_SSP_STATUS_CARD_DETECT);
  81. if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
  82. present = !present;
  83. return present;
  84. }
  85. static int mxs_mmc_reset(struct mxs_mmc_host *host)
  86. {
  87. struct mxs_ssp *ssp = &host->ssp;
  88. u32 ctrl0, ctrl1;
  89. int ret;
  90. ret = stmp_reset_block(ssp->base);
  91. if (ret)
  92. return ret;
  93. ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
  94. ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
  95. BF_SSP(0x7, CTRL1_WORD_LENGTH) |
  96. BM_SSP_CTRL1_DMA_ENABLE |
  97. BM_SSP_CTRL1_POLARITY |
  98. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
  99. BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
  100. BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
  101. BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
  102. BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
  103. writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
  104. BF_SSP(2, TIMING_CLOCK_DIVIDE) |
  105. BF_SSP(0, TIMING_CLOCK_RATE),
  106. ssp->base + HW_SSP_TIMING(ssp));
  107. if (host->sdio_irq_en) {
  108. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  109. ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
  110. }
  111. writel(ctrl0, ssp->base + HW_SSP_CTRL0);
  112. writel(ctrl1, ssp->base + HW_SSP_CTRL1(ssp));
  113. return 0;
  114. }
  115. static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
  116. struct mmc_command *cmd);
  117. static void mxs_mmc_request_done(struct mxs_mmc_host *host)
  118. {
  119. struct mmc_command *cmd = host->cmd;
  120. struct mmc_data *data = host->data;
  121. struct mmc_request *mrq = host->mrq;
  122. struct mxs_ssp *ssp = &host->ssp;
  123. if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
  124. if (mmc_resp_type(cmd) & MMC_RSP_136) {
  125. cmd->resp[3] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
  126. cmd->resp[2] = readl(ssp->base + HW_SSP_SDRESP1(ssp));
  127. cmd->resp[1] = readl(ssp->base + HW_SSP_SDRESP2(ssp));
  128. cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP3(ssp));
  129. } else {
  130. cmd->resp[0] = readl(ssp->base + HW_SSP_SDRESP0(ssp));
  131. }
  132. }
  133. if (data) {
  134. dma_unmap_sg(mmc_dev(host->mmc), data->sg,
  135. data->sg_len, ssp->dma_dir);
  136. /*
  137. * If there was an error on any block, we mark all
  138. * data blocks as being in error.
  139. */
  140. if (!data->error)
  141. data->bytes_xfered = data->blocks * data->blksz;
  142. else
  143. data->bytes_xfered = 0;
  144. host->data = NULL;
  145. if (mrq->stop) {
  146. mxs_mmc_start_cmd(host, mrq->stop);
  147. return;
  148. }
  149. }
  150. host->mrq = NULL;
  151. mmc_request_done(host->mmc, mrq);
  152. }
  153. static void mxs_mmc_dma_irq_callback(void *param)
  154. {
  155. struct mxs_mmc_host *host = param;
  156. mxs_mmc_request_done(host);
  157. }
  158. static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
  159. {
  160. struct mxs_mmc_host *host = dev_id;
  161. struct mmc_command *cmd = host->cmd;
  162. struct mmc_data *data = host->data;
  163. struct mxs_ssp *ssp = &host->ssp;
  164. u32 stat;
  165. spin_lock(&host->lock);
  166. stat = readl(ssp->base + HW_SSP_CTRL1(ssp));
  167. writel(stat & MXS_MMC_IRQ_BITS,
  168. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
  169. spin_unlock(&host->lock);
  170. if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
  171. mmc_signal_sdio_irq(host->mmc);
  172. if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
  173. cmd->error = -ETIMEDOUT;
  174. else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
  175. cmd->error = -EIO;
  176. if (data) {
  177. if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
  178. BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
  179. data->error = -ETIMEDOUT;
  180. else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
  181. data->error = -EILSEQ;
  182. else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
  183. BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
  184. data->error = -EIO;
  185. }
  186. return IRQ_HANDLED;
  187. }
  188. static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
  189. struct mxs_mmc_host *host, unsigned long flags)
  190. {
  191. struct mxs_ssp *ssp = &host->ssp;
  192. struct dma_async_tx_descriptor *desc;
  193. struct mmc_data *data = host->data;
  194. struct scatterlist * sgl;
  195. unsigned int sg_len;
  196. if (data) {
  197. /* data */
  198. dma_map_sg(mmc_dev(host->mmc), data->sg,
  199. data->sg_len, ssp->dma_dir);
  200. sgl = data->sg;
  201. sg_len = data->sg_len;
  202. } else {
  203. /* pio */
  204. sgl = (struct scatterlist *) ssp->ssp_pio_words;
  205. sg_len = SSP_PIO_NUM;
  206. }
  207. desc = dmaengine_prep_slave_sg(ssp->dmach,
  208. sgl, sg_len, ssp->slave_dirn, flags);
  209. if (desc) {
  210. desc->callback = mxs_mmc_dma_irq_callback;
  211. desc->callback_param = host;
  212. } else {
  213. if (data)
  214. dma_unmap_sg(mmc_dev(host->mmc), data->sg,
  215. data->sg_len, ssp->dma_dir);
  216. }
  217. return desc;
  218. }
  219. static void mxs_mmc_bc(struct mxs_mmc_host *host)
  220. {
  221. struct mxs_ssp *ssp = &host->ssp;
  222. struct mmc_command *cmd = host->cmd;
  223. struct dma_async_tx_descriptor *desc;
  224. u32 ctrl0, cmd0, cmd1;
  225. ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
  226. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
  227. cmd1 = cmd->arg;
  228. if (host->sdio_irq_en) {
  229. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  230. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  231. }
  232. ssp->ssp_pio_words[0] = ctrl0;
  233. ssp->ssp_pio_words[1] = cmd0;
  234. ssp->ssp_pio_words[2] = cmd1;
  235. ssp->dma_dir = DMA_NONE;
  236. ssp->slave_dirn = DMA_TRANS_NONE;
  237. desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
  238. if (!desc)
  239. goto out;
  240. dmaengine_submit(desc);
  241. dma_async_issue_pending(ssp->dmach);
  242. return;
  243. out:
  244. dev_warn(mmc_dev(host->mmc),
  245. "%s: failed to prep dma\n", __func__);
  246. }
  247. static void mxs_mmc_ac(struct mxs_mmc_host *host)
  248. {
  249. struct mxs_ssp *ssp = &host->ssp;
  250. struct mmc_command *cmd = host->cmd;
  251. struct dma_async_tx_descriptor *desc;
  252. u32 ignore_crc, get_resp, long_resp;
  253. u32 ctrl0, cmd0, cmd1;
  254. ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
  255. 0 : BM_SSP_CTRL0_IGNORE_CRC;
  256. get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
  257. BM_SSP_CTRL0_GET_RESP : 0;
  258. long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
  259. BM_SSP_CTRL0_LONG_RESP : 0;
  260. ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
  261. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
  262. cmd1 = cmd->arg;
  263. if (cmd->opcode == MMC_STOP_TRANSMISSION)
  264. cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
  265. if (host->sdio_irq_en) {
  266. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  267. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  268. }
  269. ssp->ssp_pio_words[0] = ctrl0;
  270. ssp->ssp_pio_words[1] = cmd0;
  271. ssp->ssp_pio_words[2] = cmd1;
  272. ssp->dma_dir = DMA_NONE;
  273. ssp->slave_dirn = DMA_TRANS_NONE;
  274. desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
  275. if (!desc)
  276. goto out;
  277. dmaengine_submit(desc);
  278. dma_async_issue_pending(ssp->dmach);
  279. return;
  280. out:
  281. dev_warn(mmc_dev(host->mmc),
  282. "%s: failed to prep dma\n", __func__);
  283. }
  284. static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
  285. {
  286. const unsigned int ssp_timeout_mul = 4096;
  287. /*
  288. * Calculate ticks in ms since ns are large numbers
  289. * and might overflow
  290. */
  291. const unsigned int clock_per_ms = clock_rate / 1000;
  292. const unsigned int ms = ns / 1000;
  293. const unsigned int ticks = ms * clock_per_ms;
  294. const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
  295. WARN_ON(ssp_ticks == 0);
  296. return ssp_ticks;
  297. }
  298. static void mxs_mmc_adtc(struct mxs_mmc_host *host)
  299. {
  300. struct mmc_command *cmd = host->cmd;
  301. struct mmc_data *data = cmd->data;
  302. struct dma_async_tx_descriptor *desc;
  303. struct scatterlist *sgl = data->sg, *sg;
  304. unsigned int sg_len = data->sg_len;
  305. unsigned int i;
  306. unsigned short dma_data_dir, timeout;
  307. enum dma_transfer_direction slave_dirn;
  308. unsigned int data_size = 0, log2_blksz;
  309. unsigned int blocks = data->blocks;
  310. struct mxs_ssp *ssp = &host->ssp;
  311. u32 ignore_crc, get_resp, long_resp, read;
  312. u32 ctrl0, cmd0, cmd1, val;
  313. ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
  314. 0 : BM_SSP_CTRL0_IGNORE_CRC;
  315. get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
  316. BM_SSP_CTRL0_GET_RESP : 0;
  317. long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
  318. BM_SSP_CTRL0_LONG_RESP : 0;
  319. if (data->flags & MMC_DATA_WRITE) {
  320. dma_data_dir = DMA_TO_DEVICE;
  321. slave_dirn = DMA_MEM_TO_DEV;
  322. read = 0;
  323. } else {
  324. dma_data_dir = DMA_FROM_DEVICE;
  325. slave_dirn = DMA_DEV_TO_MEM;
  326. read = BM_SSP_CTRL0_READ;
  327. }
  328. ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
  329. ignore_crc | get_resp | long_resp |
  330. BM_SSP_CTRL0_DATA_XFER | read |
  331. BM_SSP_CTRL0_WAIT_FOR_IRQ |
  332. BM_SSP_CTRL0_ENABLE;
  333. cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
  334. /* get logarithm to base 2 of block size for setting register */
  335. log2_blksz = ilog2(data->blksz);
  336. /*
  337. * take special care of the case that data size from data->sg
  338. * is not equal to blocks x blksz
  339. */
  340. for_each_sg(sgl, sg, sg_len, i)
  341. data_size += sg->length;
  342. if (data_size != data->blocks * data->blksz)
  343. blocks = 1;
  344. /* xfer count, block size and count need to be set differently */
  345. if (ssp_is_old(ssp)) {
  346. ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
  347. cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
  348. BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
  349. } else {
  350. writel(data_size, ssp->base + HW_SSP_XFER_SIZE);
  351. writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
  352. BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
  353. ssp->base + HW_SSP_BLOCK_SIZE);
  354. }
  355. if (cmd->opcode == SD_IO_RW_EXTENDED)
  356. cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
  357. cmd1 = cmd->arg;
  358. if (host->sdio_irq_en) {
  359. ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
  360. cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
  361. }
  362. /* set the timeout count */
  363. timeout = mxs_ns_to_ssp_ticks(ssp->clk_rate, data->timeout_ns);
  364. val = readl(ssp->base + HW_SSP_TIMING(ssp));
  365. val &= ~(BM_SSP_TIMING_TIMEOUT);
  366. val |= BF_SSP(timeout, TIMING_TIMEOUT);
  367. writel(val, ssp->base + HW_SSP_TIMING(ssp));
  368. /* pio */
  369. ssp->ssp_pio_words[0] = ctrl0;
  370. ssp->ssp_pio_words[1] = cmd0;
  371. ssp->ssp_pio_words[2] = cmd1;
  372. ssp->dma_dir = DMA_NONE;
  373. ssp->slave_dirn = DMA_TRANS_NONE;
  374. desc = mxs_mmc_prep_dma(host, 0);
  375. if (!desc)
  376. goto out;
  377. /* append data sg */
  378. WARN_ON(host->data != NULL);
  379. host->data = data;
  380. ssp->dma_dir = dma_data_dir;
  381. ssp->slave_dirn = slave_dirn;
  382. desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  383. if (!desc)
  384. goto out;
  385. dmaengine_submit(desc);
  386. dma_async_issue_pending(ssp->dmach);
  387. return;
  388. out:
  389. dev_warn(mmc_dev(host->mmc),
  390. "%s: failed to prep dma\n", __func__);
  391. }
  392. static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
  393. struct mmc_command *cmd)
  394. {
  395. host->cmd = cmd;
  396. switch (mmc_cmd_type(cmd)) {
  397. case MMC_CMD_BC:
  398. mxs_mmc_bc(host);
  399. break;
  400. case MMC_CMD_BCR:
  401. mxs_mmc_ac(host);
  402. break;
  403. case MMC_CMD_AC:
  404. mxs_mmc_ac(host);
  405. break;
  406. case MMC_CMD_ADTC:
  407. mxs_mmc_adtc(host);
  408. break;
  409. default:
  410. dev_warn(mmc_dev(host->mmc),
  411. "%s: unknown MMC command\n", __func__);
  412. break;
  413. }
  414. }
  415. static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
  416. {
  417. struct mxs_mmc_host *host = mmc_priv(mmc);
  418. WARN_ON(host->mrq != NULL);
  419. host->mrq = mrq;
  420. mxs_mmc_start_cmd(host, mrq->cmd);
  421. }
  422. static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  423. {
  424. struct mxs_mmc_host *host = mmc_priv(mmc);
  425. if (ios->bus_width == MMC_BUS_WIDTH_8)
  426. host->bus_width = 2;
  427. else if (ios->bus_width == MMC_BUS_WIDTH_4)
  428. host->bus_width = 1;
  429. else
  430. host->bus_width = 0;
  431. if (ios->clock)
  432. mxs_ssp_set_clk_rate(&host->ssp, ios->clock);
  433. }
  434. static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
  435. {
  436. struct mxs_mmc_host *host = mmc_priv(mmc);
  437. struct mxs_ssp *ssp = &host->ssp;
  438. unsigned long flags;
  439. spin_lock_irqsave(&host->lock, flags);
  440. host->sdio_irq_en = enable;
  441. if (enable) {
  442. writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
  443. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
  444. writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
  445. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_SET);
  446. } else {
  447. writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
  448. ssp->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
  449. writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
  450. ssp->base + HW_SSP_CTRL1(ssp) + STMP_OFFSET_REG_CLR);
  451. }
  452. spin_unlock_irqrestore(&host->lock, flags);
  453. if (enable && readl(ssp->base + HW_SSP_STATUS(ssp)) &
  454. BM_SSP_STATUS_SDIO_IRQ)
  455. mmc_signal_sdio_irq(host->mmc);
  456. }
  457. static const struct mmc_host_ops mxs_mmc_ops = {
  458. .request = mxs_mmc_request,
  459. .get_ro = mmc_gpio_get_ro,
  460. .get_cd = mxs_mmc_get_cd,
  461. .set_ios = mxs_mmc_set_ios,
  462. .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
  463. };
  464. static const struct platform_device_id mxs_ssp_ids[] = {
  465. {
  466. .name = "imx23-mmc",
  467. .driver_data = IMX23_SSP,
  468. }, {
  469. .name = "imx28-mmc",
  470. .driver_data = IMX28_SSP,
  471. }, {
  472. /* sentinel */
  473. }
  474. };
  475. MODULE_DEVICE_TABLE(platform, mxs_ssp_ids);
  476. static const struct of_device_id mxs_mmc_dt_ids[] = {
  477. { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_SSP, },
  478. { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_SSP, },
  479. { /* sentinel */ }
  480. };
  481. MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
  482. static int mxs_mmc_probe(struct platform_device *pdev)
  483. {
  484. const struct of_device_id *of_id =
  485. of_match_device(mxs_mmc_dt_ids, &pdev->dev);
  486. struct device_node *np = pdev->dev.of_node;
  487. struct mxs_mmc_host *host;
  488. struct mmc_host *mmc;
  489. struct resource *iores;
  490. int ret = 0, irq_err;
  491. struct regulator *reg_vmmc;
  492. struct mxs_ssp *ssp;
  493. irq_err = platform_get_irq(pdev, 0);
  494. if (irq_err < 0)
  495. return irq_err;
  496. mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
  497. if (!mmc)
  498. return -ENOMEM;
  499. host = mmc_priv(mmc);
  500. ssp = &host->ssp;
  501. ssp->dev = &pdev->dev;
  502. iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  503. ssp->base = devm_ioremap_resource(&pdev->dev, iores);
  504. if (IS_ERR(ssp->base)) {
  505. ret = PTR_ERR(ssp->base);
  506. goto out_mmc_free;
  507. }
  508. ssp->devid = (enum mxs_ssp_id) of_id->data;
  509. host->mmc = mmc;
  510. host->sdio_irq_en = 0;
  511. reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
  512. if (!IS_ERR(reg_vmmc)) {
  513. ret = regulator_enable(reg_vmmc);
  514. if (ret) {
  515. dev_err(&pdev->dev,
  516. "Failed to enable vmmc regulator: %d\n", ret);
  517. goto out_mmc_free;
  518. }
  519. }
  520. ssp->clk = devm_clk_get(&pdev->dev, NULL);
  521. if (IS_ERR(ssp->clk)) {
  522. ret = PTR_ERR(ssp->clk);
  523. goto out_mmc_free;
  524. }
  525. ret = clk_prepare_enable(ssp->clk);
  526. if (ret)
  527. goto out_mmc_free;
  528. ret = mxs_mmc_reset(host);
  529. if (ret) {
  530. dev_err(&pdev->dev, "Failed to reset mmc: %d\n", ret);
  531. goto out_clk_disable;
  532. }
  533. ssp->dmach = dma_request_slave_channel(&pdev->dev, "rx-tx");
  534. if (!ssp->dmach) {
  535. dev_err(mmc_dev(host->mmc),
  536. "%s: failed to request dma\n", __func__);
  537. ret = -ENODEV;
  538. goto out_clk_disable;
  539. }
  540. /* set mmc core parameters */
  541. mmc->ops = &mxs_mmc_ops;
  542. mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
  543. MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
  544. host->broken_cd = of_property_read_bool(np, "broken-cd");
  545. mmc->f_min = 400000;
  546. mmc->f_max = 288000000;
  547. ret = mmc_of_parse(mmc);
  548. if (ret)
  549. goto out_clk_disable;
  550. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  551. mmc->max_segs = 52;
  552. mmc->max_blk_size = 1 << 0xf;
  553. mmc->max_blk_count = (ssp_is_old(ssp)) ? 0xff : 0xffffff;
  554. mmc->max_req_size = (ssp_is_old(ssp)) ? 0xffff : 0xffffffff;
  555. mmc->max_seg_size = dma_get_max_seg_size(ssp->dmach->device->dev);
  556. platform_set_drvdata(pdev, mmc);
  557. spin_lock_init(&host->lock);
  558. ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
  559. dev_name(&pdev->dev), host);
  560. if (ret)
  561. goto out_free_dma;
  562. ret = mmc_add_host(mmc);
  563. if (ret)
  564. goto out_free_dma;
  565. dev_info(mmc_dev(host->mmc), "initialized\n");
  566. return 0;
  567. out_free_dma:
  568. dma_release_channel(ssp->dmach);
  569. out_clk_disable:
  570. clk_disable_unprepare(ssp->clk);
  571. out_mmc_free:
  572. mmc_free_host(mmc);
  573. return ret;
  574. }
  575. static int mxs_mmc_remove(struct platform_device *pdev)
  576. {
  577. struct mmc_host *mmc = platform_get_drvdata(pdev);
  578. struct mxs_mmc_host *host = mmc_priv(mmc);
  579. struct mxs_ssp *ssp = &host->ssp;
  580. mmc_remove_host(mmc);
  581. if (ssp->dmach)
  582. dma_release_channel(ssp->dmach);
  583. clk_disable_unprepare(ssp->clk);
  584. mmc_free_host(mmc);
  585. return 0;
  586. }
  587. #ifdef CONFIG_PM_SLEEP
  588. static int mxs_mmc_suspend(struct device *dev)
  589. {
  590. struct mmc_host *mmc = dev_get_drvdata(dev);
  591. struct mxs_mmc_host *host = mmc_priv(mmc);
  592. struct mxs_ssp *ssp = &host->ssp;
  593. clk_disable_unprepare(ssp->clk);
  594. return 0;
  595. }
  596. static int mxs_mmc_resume(struct device *dev)
  597. {
  598. struct mmc_host *mmc = dev_get_drvdata(dev);
  599. struct mxs_mmc_host *host = mmc_priv(mmc);
  600. struct mxs_ssp *ssp = &host->ssp;
  601. return clk_prepare_enable(ssp->clk);
  602. }
  603. #endif
  604. static SIMPLE_DEV_PM_OPS(mxs_mmc_pm_ops, mxs_mmc_suspend, mxs_mmc_resume);
  605. static struct platform_driver mxs_mmc_driver = {
  606. .probe = mxs_mmc_probe,
  607. .remove = mxs_mmc_remove,
  608. .id_table = mxs_ssp_ids,
  609. .driver = {
  610. .name = DRIVER_NAME,
  611. .pm = &mxs_mmc_pm_ops,
  612. .of_match_table = mxs_mmc_dt_ids,
  613. },
  614. };
  615. module_platform_driver(mxs_mmc_driver);
  616. MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
  617. MODULE_AUTHOR("Freescale Semiconductor");
  618. MODULE_LICENSE("GPL");
  619. MODULE_ALIAS("platform:" DRIVER_NAME);