hns_roce_mr.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618
  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/platform_device.h>
  34. #include <rdma/ib_umem.h>
  35. #include "hns_roce_device.h"
  36. #include "hns_roce_cmd.h"
  37. #include "hns_roce_hem.h"
  38. static u32 hw_index_to_key(unsigned long ind)
  39. {
  40. return (u32)(ind >> 24) | (ind << 8);
  41. }
  42. static unsigned long key_to_hw_index(u32 key)
  43. {
  44. return (key << 24) | (key >> 8);
  45. }
  46. static int hns_roce_sw2hw_mpt(struct hns_roce_dev *hr_dev,
  47. struct hns_roce_cmd_mailbox *mailbox,
  48. unsigned long mpt_index)
  49. {
  50. return hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, mpt_index, 0,
  51. HNS_ROCE_CMD_SW2HW_MPT,
  52. HNS_ROCE_CMD_TIME_CLASS_B);
  53. }
  54. static int hns_roce_hw2sw_mpt(struct hns_roce_dev *hr_dev,
  55. struct hns_roce_cmd_mailbox *mailbox,
  56. unsigned long mpt_index)
  57. {
  58. return hns_roce_cmd_mbox(hr_dev, 0, mailbox ? mailbox->dma : 0,
  59. mpt_index, !mailbox, HNS_ROCE_CMD_HW2SW_MPT,
  60. HNS_ROCE_CMD_TIME_CLASS_B);
  61. }
  62. static int hns_roce_buddy_alloc(struct hns_roce_buddy *buddy, int order,
  63. unsigned long *seg)
  64. {
  65. int o;
  66. u32 m;
  67. spin_lock(&buddy->lock);
  68. for (o = order; o <= buddy->max_order; ++o) {
  69. if (buddy->num_free[o]) {
  70. m = 1 << (buddy->max_order - o);
  71. *seg = find_first_bit(buddy->bits[o], m);
  72. if (*seg < m)
  73. goto found;
  74. }
  75. }
  76. spin_unlock(&buddy->lock);
  77. return -1;
  78. found:
  79. clear_bit(*seg, buddy->bits[o]);
  80. --buddy->num_free[o];
  81. while (o > order) {
  82. --o;
  83. *seg <<= 1;
  84. set_bit(*seg ^ 1, buddy->bits[o]);
  85. ++buddy->num_free[o];
  86. }
  87. spin_unlock(&buddy->lock);
  88. *seg <<= order;
  89. return 0;
  90. }
  91. static void hns_roce_buddy_free(struct hns_roce_buddy *buddy, unsigned long seg,
  92. int order)
  93. {
  94. seg >>= order;
  95. spin_lock(&buddy->lock);
  96. while (test_bit(seg ^ 1, buddy->bits[order])) {
  97. clear_bit(seg ^ 1, buddy->bits[order]);
  98. --buddy->num_free[order];
  99. seg >>= 1;
  100. ++order;
  101. }
  102. set_bit(seg, buddy->bits[order]);
  103. ++buddy->num_free[order];
  104. spin_unlock(&buddy->lock);
  105. }
  106. static int hns_roce_buddy_init(struct hns_roce_buddy *buddy, int max_order)
  107. {
  108. int i, s;
  109. buddy->max_order = max_order;
  110. spin_lock_init(&buddy->lock);
  111. buddy->bits = kzalloc((buddy->max_order + 1) * sizeof(long *),
  112. GFP_KERNEL);
  113. buddy->num_free = kzalloc((buddy->max_order + 1) * sizeof(int *),
  114. GFP_KERNEL);
  115. if (!buddy->bits || !buddy->num_free)
  116. goto err_out;
  117. for (i = 0; i <= buddy->max_order; ++i) {
  118. s = BITS_TO_LONGS(1 << (buddy->max_order - i));
  119. buddy->bits[i] = kmalloc_array(s, sizeof(long), GFP_KERNEL);
  120. if (!buddy->bits[i])
  121. goto err_out_free;
  122. bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
  123. }
  124. set_bit(0, buddy->bits[buddy->max_order]);
  125. buddy->num_free[buddy->max_order] = 1;
  126. return 0;
  127. err_out_free:
  128. for (i = 0; i <= buddy->max_order; ++i)
  129. kfree(buddy->bits[i]);
  130. err_out:
  131. kfree(buddy->bits);
  132. kfree(buddy->num_free);
  133. return -ENOMEM;
  134. }
  135. static void hns_roce_buddy_cleanup(struct hns_roce_buddy *buddy)
  136. {
  137. int i;
  138. for (i = 0; i <= buddy->max_order; ++i)
  139. kfree(buddy->bits[i]);
  140. kfree(buddy->bits);
  141. kfree(buddy->num_free);
  142. }
  143. static int hns_roce_alloc_mtt_range(struct hns_roce_dev *hr_dev, int order,
  144. unsigned long *seg)
  145. {
  146. struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
  147. int ret = 0;
  148. ret = hns_roce_buddy_alloc(&mr_table->mtt_buddy, order, seg);
  149. if (ret == -1)
  150. return -1;
  151. if (hns_roce_table_get_range(hr_dev, &mr_table->mtt_table, *seg,
  152. *seg + (1 << order) - 1)) {
  153. hns_roce_buddy_free(&mr_table->mtt_buddy, *seg, order);
  154. return -1;
  155. }
  156. return 0;
  157. }
  158. int hns_roce_mtt_init(struct hns_roce_dev *hr_dev, int npages, int page_shift,
  159. struct hns_roce_mtt *mtt)
  160. {
  161. int ret = 0;
  162. int i;
  163. /* Page num is zero, correspond to DMA memory register */
  164. if (!npages) {
  165. mtt->order = -1;
  166. mtt->page_shift = HNS_ROCE_HEM_PAGE_SHIFT;
  167. return 0;
  168. }
  169. /* Note: if page_shift is zero, FAST memory regsiter */
  170. mtt->page_shift = page_shift;
  171. /* Compute MTT entry necessary */
  172. for (mtt->order = 0, i = HNS_ROCE_MTT_ENTRY_PER_SEG; i < npages;
  173. i <<= 1)
  174. ++mtt->order;
  175. /* Allocate MTT entry */
  176. ret = hns_roce_alloc_mtt_range(hr_dev, mtt->order, &mtt->first_seg);
  177. if (ret == -1)
  178. return -ENOMEM;
  179. return 0;
  180. }
  181. void hns_roce_mtt_cleanup(struct hns_roce_dev *hr_dev, struct hns_roce_mtt *mtt)
  182. {
  183. struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
  184. if (mtt->order < 0)
  185. return;
  186. hns_roce_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
  187. hns_roce_table_put_range(hr_dev, &mr_table->mtt_table, mtt->first_seg,
  188. mtt->first_seg + (1 << mtt->order) - 1);
  189. }
  190. static int hns_roce_mr_alloc(struct hns_roce_dev *hr_dev, u32 pd, u64 iova,
  191. u64 size, u32 access, int npages,
  192. struct hns_roce_mr *mr)
  193. {
  194. unsigned long index = 0;
  195. int ret = 0;
  196. struct device *dev = &hr_dev->pdev->dev;
  197. /* Allocate a key for mr from mr_table */
  198. ret = hns_roce_bitmap_alloc(&hr_dev->mr_table.mtpt_bitmap, &index);
  199. if (ret == -1)
  200. return -ENOMEM;
  201. mr->iova = iova; /* MR va starting addr */
  202. mr->size = size; /* MR addr range */
  203. mr->pd = pd; /* MR num */
  204. mr->access = access; /* MR access permit */
  205. mr->enabled = 0; /* MR active status */
  206. mr->key = hw_index_to_key(index); /* MR key */
  207. if (size == ~0ull) {
  208. mr->type = MR_TYPE_DMA;
  209. mr->pbl_buf = NULL;
  210. mr->pbl_dma_addr = 0;
  211. } else {
  212. mr->type = MR_TYPE_MR;
  213. mr->pbl_buf = dma_alloc_coherent(dev, npages * 8,
  214. &(mr->pbl_dma_addr),
  215. GFP_KERNEL);
  216. if (!mr->pbl_buf)
  217. return -ENOMEM;
  218. }
  219. return 0;
  220. }
  221. static void hns_roce_mr_free(struct hns_roce_dev *hr_dev,
  222. struct hns_roce_mr *mr)
  223. {
  224. struct device *dev = &hr_dev->pdev->dev;
  225. int npages = 0;
  226. int ret;
  227. if (mr->enabled) {
  228. ret = hns_roce_hw2sw_mpt(hr_dev, NULL, key_to_hw_index(mr->key)
  229. & (hr_dev->caps.num_mtpts - 1));
  230. if (ret)
  231. dev_warn(dev, "HW2SW_MPT failed (%d)\n", ret);
  232. }
  233. if (mr->size != ~0ULL) {
  234. npages = ib_umem_page_count(mr->umem);
  235. dma_free_coherent(dev, (unsigned int)(npages * 8), mr->pbl_buf,
  236. mr->pbl_dma_addr);
  237. }
  238. hns_roce_bitmap_free(&hr_dev->mr_table.mtpt_bitmap,
  239. key_to_hw_index(mr->key));
  240. }
  241. static int hns_roce_mr_enable(struct hns_roce_dev *hr_dev,
  242. struct hns_roce_mr *mr)
  243. {
  244. int ret;
  245. unsigned long mtpt_idx = key_to_hw_index(mr->key);
  246. struct device *dev = &hr_dev->pdev->dev;
  247. struct hns_roce_cmd_mailbox *mailbox;
  248. struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
  249. /* Prepare HEM entry memory */
  250. ret = hns_roce_table_get(hr_dev, &mr_table->mtpt_table, mtpt_idx);
  251. if (ret)
  252. return ret;
  253. /* Allocate mailbox memory */
  254. mailbox = hns_roce_alloc_cmd_mailbox(hr_dev);
  255. if (IS_ERR(mailbox)) {
  256. ret = PTR_ERR(mailbox);
  257. goto err_table;
  258. }
  259. ret = hr_dev->hw->write_mtpt(mailbox->buf, mr, mtpt_idx);
  260. if (ret) {
  261. dev_err(dev, "Write mtpt fail!\n");
  262. goto err_page;
  263. }
  264. ret = hns_roce_sw2hw_mpt(hr_dev, mailbox,
  265. mtpt_idx & (hr_dev->caps.num_mtpts - 1));
  266. if (ret) {
  267. dev_err(dev, "SW2HW_MPT failed (%d)\n", ret);
  268. goto err_page;
  269. }
  270. mr->enabled = 1;
  271. hns_roce_free_cmd_mailbox(hr_dev, mailbox);
  272. return 0;
  273. err_page:
  274. hns_roce_free_cmd_mailbox(hr_dev, mailbox);
  275. err_table:
  276. hns_roce_table_put(hr_dev, &mr_table->mtpt_table, mtpt_idx);
  277. return ret;
  278. }
  279. static int hns_roce_write_mtt_chunk(struct hns_roce_dev *hr_dev,
  280. struct hns_roce_mtt *mtt, u32 start_index,
  281. u32 npages, u64 *page_list)
  282. {
  283. u32 i = 0;
  284. __le64 *mtts = NULL;
  285. dma_addr_t dma_handle;
  286. u32 s = start_index * sizeof(u64);
  287. /* All MTTs must fit in the same page */
  288. if (start_index / (PAGE_SIZE / sizeof(u64)) !=
  289. (start_index + npages - 1) / (PAGE_SIZE / sizeof(u64)))
  290. return -EINVAL;
  291. if (start_index & (HNS_ROCE_MTT_ENTRY_PER_SEG - 1))
  292. return -EINVAL;
  293. mtts = hns_roce_table_find(&hr_dev->mr_table.mtt_table,
  294. mtt->first_seg + s / hr_dev->caps.mtt_entry_sz,
  295. &dma_handle);
  296. if (!mtts)
  297. return -ENOMEM;
  298. /* Save page addr, low 12 bits : 0 */
  299. for (i = 0; i < npages; ++i)
  300. mtts[i] = (cpu_to_le64(page_list[i])) >> PAGE_ADDR_SHIFT;
  301. return 0;
  302. }
  303. static int hns_roce_write_mtt(struct hns_roce_dev *hr_dev,
  304. struct hns_roce_mtt *mtt, u32 start_index,
  305. u32 npages, u64 *page_list)
  306. {
  307. int chunk;
  308. int ret;
  309. if (mtt->order < 0)
  310. return -EINVAL;
  311. while (npages > 0) {
  312. chunk = min_t(int, PAGE_SIZE / sizeof(u64), npages);
  313. ret = hns_roce_write_mtt_chunk(hr_dev, mtt, start_index, chunk,
  314. page_list);
  315. if (ret)
  316. return ret;
  317. npages -= chunk;
  318. start_index += chunk;
  319. page_list += chunk;
  320. }
  321. return 0;
  322. }
  323. int hns_roce_buf_write_mtt(struct hns_roce_dev *hr_dev,
  324. struct hns_roce_mtt *mtt, struct hns_roce_buf *buf)
  325. {
  326. u32 i = 0;
  327. int ret = 0;
  328. u64 *page_list = NULL;
  329. page_list = kmalloc_array(buf->npages, sizeof(*page_list), GFP_KERNEL);
  330. if (!page_list)
  331. return -ENOMEM;
  332. for (i = 0; i < buf->npages; ++i) {
  333. if (buf->nbufs == 1)
  334. page_list[i] = buf->direct.map + (i << buf->page_shift);
  335. else
  336. page_list[i] = buf->page_list[i].map;
  337. }
  338. ret = hns_roce_write_mtt(hr_dev, mtt, 0, buf->npages, page_list);
  339. kfree(page_list);
  340. return ret;
  341. }
  342. int hns_roce_init_mr_table(struct hns_roce_dev *hr_dev)
  343. {
  344. struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
  345. int ret = 0;
  346. ret = hns_roce_bitmap_init(&mr_table->mtpt_bitmap,
  347. hr_dev->caps.num_mtpts,
  348. hr_dev->caps.num_mtpts - 1,
  349. hr_dev->caps.reserved_mrws, 0);
  350. if (ret)
  351. return ret;
  352. ret = hns_roce_buddy_init(&mr_table->mtt_buddy,
  353. ilog2(hr_dev->caps.num_mtt_segs));
  354. if (ret)
  355. goto err_buddy;
  356. return 0;
  357. err_buddy:
  358. hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap);
  359. return ret;
  360. }
  361. void hns_roce_cleanup_mr_table(struct hns_roce_dev *hr_dev)
  362. {
  363. struct hns_roce_mr_table *mr_table = &hr_dev->mr_table;
  364. hns_roce_buddy_cleanup(&mr_table->mtt_buddy);
  365. hns_roce_bitmap_cleanup(&mr_table->mtpt_bitmap);
  366. }
  367. struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc)
  368. {
  369. int ret = 0;
  370. struct hns_roce_mr *mr = NULL;
  371. mr = kmalloc(sizeof(*mr), GFP_KERNEL);
  372. if (mr == NULL)
  373. return ERR_PTR(-ENOMEM);
  374. /* Allocate memory region key */
  375. ret = hns_roce_mr_alloc(to_hr_dev(pd->device), to_hr_pd(pd)->pdn, 0,
  376. ~0ULL, acc, 0, mr);
  377. if (ret)
  378. goto err_free;
  379. ret = hns_roce_mr_enable(to_hr_dev(pd->device), mr);
  380. if (ret)
  381. goto err_mr;
  382. mr->ibmr.rkey = mr->ibmr.lkey = mr->key;
  383. mr->umem = NULL;
  384. return &mr->ibmr;
  385. err_mr:
  386. hns_roce_mr_free(to_hr_dev(pd->device), mr);
  387. err_free:
  388. kfree(mr);
  389. return ERR_PTR(ret);
  390. }
  391. int hns_roce_ib_umem_write_mtt(struct hns_roce_dev *hr_dev,
  392. struct hns_roce_mtt *mtt, struct ib_umem *umem)
  393. {
  394. struct scatterlist *sg;
  395. int i, k, entry;
  396. int ret = 0;
  397. u64 *pages;
  398. u32 n;
  399. int len;
  400. pages = (u64 *) __get_free_page(GFP_KERNEL);
  401. if (!pages)
  402. return -ENOMEM;
  403. i = n = 0;
  404. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  405. len = sg_dma_len(sg) >> mtt->page_shift;
  406. for (k = 0; k < len; ++k) {
  407. pages[i++] = sg_dma_address(sg) + umem->page_size * k;
  408. if (i == PAGE_SIZE / sizeof(u64)) {
  409. ret = hns_roce_write_mtt(hr_dev, mtt, n, i,
  410. pages);
  411. if (ret)
  412. goto out;
  413. n += i;
  414. i = 0;
  415. }
  416. }
  417. }
  418. if (i)
  419. ret = hns_roce_write_mtt(hr_dev, mtt, n, i, pages);
  420. out:
  421. free_page((unsigned long) pages);
  422. return ret;
  423. }
  424. static int hns_roce_ib_umem_write_mr(struct hns_roce_mr *mr,
  425. struct ib_umem *umem)
  426. {
  427. int i = 0;
  428. int entry;
  429. struct scatterlist *sg;
  430. for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
  431. mr->pbl_buf[i] = ((u64)sg_dma_address(sg)) >> 12;
  432. i++;
  433. }
  434. /* Memory barrier */
  435. mb();
  436. return 0;
  437. }
  438. struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  439. u64 virt_addr, int access_flags,
  440. struct ib_udata *udata)
  441. {
  442. struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
  443. struct device *dev = &hr_dev->pdev->dev;
  444. struct hns_roce_mr *mr = NULL;
  445. int ret = 0;
  446. int n = 0;
  447. mr = kmalloc(sizeof(*mr), GFP_KERNEL);
  448. if (!mr)
  449. return ERR_PTR(-ENOMEM);
  450. mr->umem = ib_umem_get(pd->uobject->context, start, length,
  451. access_flags, 0);
  452. if (IS_ERR(mr->umem)) {
  453. ret = PTR_ERR(mr->umem);
  454. goto err_free;
  455. }
  456. n = ib_umem_page_count(mr->umem);
  457. if (mr->umem->page_size != HNS_ROCE_HEM_PAGE_SIZE) {
  458. dev_err(dev, "Just support 4K page size but is 0x%x now!\n",
  459. mr->umem->page_size);
  460. ret = -EINVAL;
  461. goto err_umem;
  462. }
  463. if (n > HNS_ROCE_MAX_MTPT_PBL_NUM) {
  464. dev_err(dev, " MR len %lld err. MR is limited to 4G at most!\n",
  465. length);
  466. ret = -EINVAL;
  467. goto err_umem;
  468. }
  469. ret = hns_roce_mr_alloc(hr_dev, to_hr_pd(pd)->pdn, virt_addr, length,
  470. access_flags, n, mr);
  471. if (ret)
  472. goto err_umem;
  473. ret = hns_roce_ib_umem_write_mr(mr, mr->umem);
  474. if (ret)
  475. goto err_mr;
  476. ret = hns_roce_mr_enable(hr_dev, mr);
  477. if (ret)
  478. goto err_mr;
  479. mr->ibmr.rkey = mr->ibmr.lkey = mr->key;
  480. return &mr->ibmr;
  481. err_mr:
  482. hns_roce_mr_free(hr_dev, mr);
  483. err_umem:
  484. ib_umem_release(mr->umem);
  485. err_free:
  486. kfree(mr);
  487. return ERR_PTR(ret);
  488. }
  489. int hns_roce_dereg_mr(struct ib_mr *ibmr)
  490. {
  491. struct hns_roce_mr *mr = to_hr_mr(ibmr);
  492. hns_roce_mr_free(to_hr_dev(ibmr->device), mr);
  493. if (mr->umem)
  494. ib_umem_release(mr->umem);
  495. kfree(mr);
  496. return 0;
  497. }