hns_roce_main.c 30 KB

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  1. /*
  2. * Copyright (c) 2016 Hisilicon Limited.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/acpi.h>
  34. #include <linux/of_platform.h>
  35. #include <rdma/ib_addr.h>
  36. #include <rdma/ib_smi.h>
  37. #include <rdma/ib_user_verbs.h>
  38. #include "hns_roce_common.h"
  39. #include "hns_roce_device.h"
  40. #include "hns_roce_user.h"
  41. #include "hns_roce_hem.h"
  42. /**
  43. * hns_roce_addrconf_ifid_eui48 - Get default gid.
  44. * @eui: eui.
  45. * @vlan_id: gid
  46. * @dev: net device
  47. * Description:
  48. * MAC convert to GID
  49. * gid[0..7] = fe80 0000 0000 0000
  50. * gid[8] = mac[0] ^ 2
  51. * gid[9] = mac[1]
  52. * gid[10] = mac[2]
  53. * gid[11] = ff (VLAN ID high byte (4 MS bits))
  54. * gid[12] = fe (VLAN ID low byte)
  55. * gid[13] = mac[3]
  56. * gid[14] = mac[4]
  57. * gid[15] = mac[5]
  58. */
  59. static void hns_roce_addrconf_ifid_eui48(u8 *eui, u16 vlan_id,
  60. struct net_device *dev)
  61. {
  62. memcpy(eui, dev->dev_addr, 3);
  63. memcpy(eui + 5, dev->dev_addr + 3, 3);
  64. if (vlan_id < 0x1000) {
  65. eui[3] = vlan_id >> 8;
  66. eui[4] = vlan_id & 0xff;
  67. } else {
  68. eui[3] = 0xff;
  69. eui[4] = 0xfe;
  70. }
  71. eui[0] ^= 2;
  72. }
  73. static void hns_roce_make_default_gid(struct net_device *dev, union ib_gid *gid)
  74. {
  75. memset(gid, 0, sizeof(*gid));
  76. gid->raw[0] = 0xFE;
  77. gid->raw[1] = 0x80;
  78. hns_roce_addrconf_ifid_eui48(&gid->raw[8], 0xffff, dev);
  79. }
  80. /**
  81. * hns_get_gid_index - Get gid index.
  82. * @hr_dev: pointer to structure hns_roce_dev.
  83. * @port: port, value range: 0 ~ MAX
  84. * @gid_index: gid_index, value range: 0 ~ MAX
  85. * Description:
  86. * N ports shared gids, allocation method as follow:
  87. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  88. * GID[0][0], GID[1][0],.....GID[N - 1][0],
  89. * And so on
  90. */
  91. int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  92. {
  93. return gid_index * hr_dev->caps.num_ports + port;
  94. }
  95. static int hns_roce_set_gid(struct hns_roce_dev *hr_dev, u8 port, int gid_index,
  96. union ib_gid *gid)
  97. {
  98. struct device *dev = &hr_dev->pdev->dev;
  99. u8 gid_idx = 0;
  100. if (gid_index >= hr_dev->caps.gid_table_len[port]) {
  101. dev_err(dev, "gid_index %d illegal, port %d gid range: 0~%d\n",
  102. gid_index, port, hr_dev->caps.gid_table_len[port] - 1);
  103. return -EINVAL;
  104. }
  105. gid_idx = hns_get_gid_index(hr_dev, port, gid_index);
  106. if (!memcmp(gid, &hr_dev->iboe.gid_table[gid_idx], sizeof(*gid)))
  107. return -EINVAL;
  108. memcpy(&hr_dev->iboe.gid_table[gid_idx], gid, sizeof(*gid));
  109. hr_dev->hw->set_gid(hr_dev, port, gid_index, gid);
  110. return 0;
  111. }
  112. static void hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  113. {
  114. u8 phy_port;
  115. u32 i = 0;
  116. if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
  117. return;
  118. for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
  119. hr_dev->dev_addr[port][i] = addr[i];
  120. phy_port = hr_dev->iboe.phy_port[port];
  121. hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  122. }
  123. static void hns_roce_set_mtu(struct hns_roce_dev *hr_dev, u8 port, int mtu)
  124. {
  125. u8 phy_port = hr_dev->iboe.phy_port[port];
  126. enum ib_mtu tmp;
  127. tmp = iboe_get_mtu(mtu);
  128. if (!tmp)
  129. tmp = IB_MTU_256;
  130. hr_dev->hw->set_mtu(hr_dev, phy_port, tmp);
  131. }
  132. static void hns_roce_update_gids(struct hns_roce_dev *hr_dev, int port)
  133. {
  134. struct ib_event event;
  135. /* Refresh gid in ib_cache */
  136. event.device = &hr_dev->ib_dev;
  137. event.element.port_num = port + 1;
  138. event.event = IB_EVENT_GID_CHANGE;
  139. ib_dispatch_event(&event);
  140. }
  141. static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
  142. unsigned long event)
  143. {
  144. struct device *dev = &hr_dev->pdev->dev;
  145. struct net_device *netdev;
  146. unsigned long flags;
  147. union ib_gid gid;
  148. int ret = 0;
  149. netdev = hr_dev->iboe.netdevs[port];
  150. if (!netdev) {
  151. dev_err(dev, "port(%d) can't find netdev\n", port);
  152. return -ENODEV;
  153. }
  154. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  155. switch (event) {
  156. case NETDEV_UP:
  157. case NETDEV_CHANGE:
  158. case NETDEV_REGISTER:
  159. case NETDEV_CHANGEADDR:
  160. hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
  161. hns_roce_make_default_gid(netdev, &gid);
  162. ret = hns_roce_set_gid(hr_dev, port, 0, &gid);
  163. if (!ret)
  164. hns_roce_update_gids(hr_dev, port);
  165. break;
  166. case NETDEV_DOWN:
  167. /*
  168. * In v1 engine, only support all ports closed together.
  169. */
  170. break;
  171. default:
  172. dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
  173. break;
  174. }
  175. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  176. return ret;
  177. }
  178. static int hns_roce_netdev_event(struct notifier_block *self,
  179. unsigned long event, void *ptr)
  180. {
  181. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  182. struct hns_roce_ib_iboe *iboe = NULL;
  183. struct hns_roce_dev *hr_dev = NULL;
  184. u8 port = 0;
  185. int ret = 0;
  186. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
  187. iboe = &hr_dev->iboe;
  188. for (port = 0; port < hr_dev->caps.num_ports; port++) {
  189. if (dev == iboe->netdevs[port]) {
  190. ret = handle_en_event(hr_dev, port, event);
  191. if (ret)
  192. return NOTIFY_DONE;
  193. break;
  194. }
  195. }
  196. return NOTIFY_DONE;
  197. }
  198. static void hns_roce_addr_event(int event, struct net_device *event_netdev,
  199. struct hns_roce_dev *hr_dev, union ib_gid *gid)
  200. {
  201. struct hns_roce_ib_iboe *iboe = NULL;
  202. int gid_table_len = 0;
  203. unsigned long flags;
  204. union ib_gid zgid;
  205. u8 gid_idx = 0;
  206. u8 port = 0;
  207. int i = 0;
  208. int free;
  209. struct net_device *real_dev = rdma_vlan_dev_real_dev(event_netdev) ?
  210. rdma_vlan_dev_real_dev(event_netdev) :
  211. event_netdev;
  212. if (event != NETDEV_UP && event != NETDEV_DOWN)
  213. return;
  214. iboe = &hr_dev->iboe;
  215. while (port < hr_dev->caps.num_ports) {
  216. if (real_dev == iboe->netdevs[port])
  217. break;
  218. port++;
  219. }
  220. if (port >= hr_dev->caps.num_ports) {
  221. dev_dbg(&hr_dev->pdev->dev, "can't find netdev\n");
  222. return;
  223. }
  224. memset(zgid.raw, 0, sizeof(zgid.raw));
  225. free = -1;
  226. gid_table_len = hr_dev->caps.gid_table_len[port];
  227. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  228. for (i = 0; i < gid_table_len; i++) {
  229. gid_idx = hns_get_gid_index(hr_dev, port, i);
  230. if (!memcmp(gid->raw, iboe->gid_table[gid_idx].raw,
  231. sizeof(gid->raw)))
  232. break;
  233. if (free < 0 && !memcmp(zgid.raw,
  234. iboe->gid_table[gid_idx].raw, sizeof(zgid.raw)))
  235. free = i;
  236. }
  237. if (i >= gid_table_len) {
  238. if (free < 0) {
  239. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  240. dev_dbg(&hr_dev->pdev->dev,
  241. "gid_index overflow, port(%d)\n", port);
  242. return;
  243. }
  244. if (!hns_roce_set_gid(hr_dev, port, free, gid))
  245. hns_roce_update_gids(hr_dev, port);
  246. } else if (event == NETDEV_DOWN) {
  247. if (!hns_roce_set_gid(hr_dev, port, i, &zgid))
  248. hns_roce_update_gids(hr_dev, port);
  249. }
  250. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  251. }
  252. static int hns_roce_inet_event(struct notifier_block *self, unsigned long event,
  253. void *ptr)
  254. {
  255. struct in_ifaddr *ifa = ptr;
  256. struct hns_roce_dev *hr_dev;
  257. struct net_device *dev = ifa->ifa_dev->dev;
  258. union ib_gid gid;
  259. ipv6_addr_set_v4mapped(ifa->ifa_address, (struct in6_addr *)&gid);
  260. hr_dev = container_of(self, struct hns_roce_dev, iboe.nb_inet);
  261. hns_roce_addr_event(event, dev, hr_dev, &gid);
  262. return NOTIFY_DONE;
  263. }
  264. static int hns_roce_setup_mtu_gids(struct hns_roce_dev *hr_dev)
  265. {
  266. struct in_ifaddr *ifa_list = NULL;
  267. union ib_gid gid = {{0} };
  268. u32 ipaddr = 0;
  269. int index = 0;
  270. int ret = 0;
  271. u8 i = 0;
  272. for (i = 0; i < hr_dev->caps.num_ports; i++) {
  273. hns_roce_set_mtu(hr_dev, i,
  274. ib_mtu_enum_to_int(hr_dev->caps.max_mtu));
  275. hns_roce_set_mac(hr_dev, i, hr_dev->iboe.netdevs[i]->dev_addr);
  276. if (hr_dev->iboe.netdevs[i]->ip_ptr) {
  277. ifa_list = hr_dev->iboe.netdevs[i]->ip_ptr->ifa_list;
  278. index = 1;
  279. while (ifa_list) {
  280. ipaddr = ifa_list->ifa_address;
  281. ipv6_addr_set_v4mapped(ipaddr,
  282. (struct in6_addr *)&gid);
  283. ret = hns_roce_set_gid(hr_dev, i, index, &gid);
  284. if (ret)
  285. break;
  286. index++;
  287. ifa_list = ifa_list->ifa_next;
  288. }
  289. hns_roce_update_gids(hr_dev, i);
  290. }
  291. }
  292. return ret;
  293. }
  294. static int hns_roce_query_device(struct ib_device *ib_dev,
  295. struct ib_device_attr *props,
  296. struct ib_udata *uhw)
  297. {
  298. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  299. memset(props, 0, sizeof(*props));
  300. props->sys_image_guid = hr_dev->sys_image_guid;
  301. props->max_mr_size = (u64)(~(0ULL));
  302. props->page_size_cap = hr_dev->caps.page_size_cap;
  303. props->vendor_id = hr_dev->vendor_id;
  304. props->vendor_part_id = hr_dev->vendor_part_id;
  305. props->hw_ver = hr_dev->hw_rev;
  306. props->max_qp = hr_dev->caps.num_qps;
  307. props->max_qp_wr = hr_dev->caps.max_wqes;
  308. props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
  309. IB_DEVICE_RC_RNR_NAK_GEN;
  310. props->max_sge = hr_dev->caps.max_sq_sg;
  311. props->max_sge_rd = 1;
  312. props->max_cq = hr_dev->caps.num_cqs;
  313. props->max_cqe = hr_dev->caps.max_cqes;
  314. props->max_mr = hr_dev->caps.num_mtpts;
  315. props->max_pd = hr_dev->caps.num_pds;
  316. props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
  317. props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
  318. props->atomic_cap = IB_ATOMIC_NONE;
  319. props->max_pkeys = 1;
  320. props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
  321. return 0;
  322. }
  323. static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
  324. u8 port_num)
  325. {
  326. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  327. struct net_device *ndev;
  328. if (port_num < 1 || port_num > hr_dev->caps.num_ports)
  329. return NULL;
  330. rcu_read_lock();
  331. ndev = hr_dev->iboe.netdevs[port_num - 1];
  332. if (ndev)
  333. dev_hold(ndev);
  334. rcu_read_unlock();
  335. return ndev;
  336. }
  337. static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
  338. struct ib_port_attr *props)
  339. {
  340. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  341. struct device *dev = &hr_dev->pdev->dev;
  342. struct net_device *net_dev;
  343. unsigned long flags;
  344. enum ib_mtu mtu;
  345. u8 port;
  346. assert(port_num > 0);
  347. port = port_num - 1;
  348. memset(props, 0, sizeof(*props));
  349. props->max_mtu = hr_dev->caps.max_mtu;
  350. props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
  351. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
  352. IB_PORT_VENDOR_CLASS_SUP |
  353. IB_PORT_BOOT_MGMT_SUP;
  354. props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
  355. props->pkey_tbl_len = 1;
  356. props->active_width = IB_WIDTH_4X;
  357. props->active_speed = 1;
  358. spin_lock_irqsave(&hr_dev->iboe.lock, flags);
  359. net_dev = hr_dev->iboe.netdevs[port];
  360. if (!net_dev) {
  361. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  362. dev_err(dev, "find netdev %d failed!\r\n", port);
  363. return -EINVAL;
  364. }
  365. mtu = iboe_get_mtu(net_dev->mtu);
  366. props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
  367. props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
  368. IB_PORT_ACTIVE : IB_PORT_DOWN;
  369. props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
  370. spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
  371. return 0;
  372. }
  373. static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
  374. u8 port_num)
  375. {
  376. return IB_LINK_LAYER_ETHERNET;
  377. }
  378. static int hns_roce_query_gid(struct ib_device *ib_dev, u8 port_num, int index,
  379. union ib_gid *gid)
  380. {
  381. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  382. struct device *dev = &hr_dev->pdev->dev;
  383. u8 gid_idx = 0;
  384. u8 port;
  385. if (port_num < 1 || port_num > hr_dev->caps.num_ports ||
  386. index >= hr_dev->caps.gid_table_len[port_num - 1]) {
  387. dev_err(dev,
  388. "port_num %d index %d illegal! correct range: port_num 1~%d index 0~%d!\n",
  389. port_num, index, hr_dev->caps.num_ports,
  390. hr_dev->caps.gid_table_len[port_num - 1] - 1);
  391. return -EINVAL;
  392. }
  393. port = port_num - 1;
  394. gid_idx = hns_get_gid_index(hr_dev, port, index);
  395. if (gid_idx >= HNS_ROCE_MAX_GID_NUM) {
  396. dev_err(dev, "port_num %d index %d illegal! total gid num %d!\n",
  397. port_num, index, HNS_ROCE_MAX_GID_NUM);
  398. return -EINVAL;
  399. }
  400. memcpy(gid->raw, hr_dev->iboe.gid_table[gid_idx].raw,
  401. HNS_ROCE_GID_SIZE);
  402. return 0;
  403. }
  404. static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
  405. u16 *pkey)
  406. {
  407. *pkey = PKEY_ID;
  408. return 0;
  409. }
  410. static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
  411. struct ib_device_modify *props)
  412. {
  413. unsigned long flags;
  414. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  415. return -EOPNOTSUPP;
  416. if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
  417. spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
  418. memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
  419. spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
  420. }
  421. return 0;
  422. }
  423. static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
  424. struct ib_port_modify *props)
  425. {
  426. return 0;
  427. }
  428. static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
  429. struct ib_udata *udata)
  430. {
  431. int ret = 0;
  432. struct hns_roce_ucontext *context;
  433. struct hns_roce_ib_alloc_ucontext_resp resp;
  434. struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
  435. resp.qp_tab_size = hr_dev->caps.num_qps;
  436. context = kmalloc(sizeof(*context), GFP_KERNEL);
  437. if (!context)
  438. return ERR_PTR(-ENOMEM);
  439. ret = hns_roce_uar_alloc(hr_dev, &context->uar);
  440. if (ret)
  441. goto error_fail_uar_alloc;
  442. ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
  443. if (ret)
  444. goto error_fail_copy_to_udata;
  445. return &context->ibucontext;
  446. error_fail_copy_to_udata:
  447. hns_roce_uar_free(hr_dev, &context->uar);
  448. error_fail_uar_alloc:
  449. kfree(context);
  450. return ERR_PTR(ret);
  451. }
  452. static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
  453. {
  454. struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
  455. hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
  456. kfree(context);
  457. return 0;
  458. }
  459. static int hns_roce_mmap(struct ib_ucontext *context,
  460. struct vm_area_struct *vma)
  461. {
  462. if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
  463. return -EINVAL;
  464. if (vma->vm_pgoff == 0) {
  465. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  466. if (io_remap_pfn_range(vma, vma->vm_start,
  467. to_hr_ucontext(context)->uar.pfn,
  468. PAGE_SIZE, vma->vm_page_prot))
  469. return -EAGAIN;
  470. } else {
  471. return -EINVAL;
  472. }
  473. return 0;
  474. }
  475. static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
  476. struct ib_port_immutable *immutable)
  477. {
  478. struct ib_port_attr attr;
  479. int ret;
  480. ret = hns_roce_query_port(ib_dev, port_num, &attr);
  481. if (ret)
  482. return ret;
  483. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  484. immutable->gid_tbl_len = attr.gid_tbl_len;
  485. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  486. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  487. return 0;
  488. }
  489. static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
  490. {
  491. struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
  492. unregister_inetaddr_notifier(&iboe->nb_inet);
  493. unregister_netdevice_notifier(&iboe->nb);
  494. ib_unregister_device(&hr_dev->ib_dev);
  495. }
  496. static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
  497. {
  498. int ret;
  499. struct hns_roce_ib_iboe *iboe = NULL;
  500. struct ib_device *ib_dev = NULL;
  501. struct device *dev = &hr_dev->pdev->dev;
  502. iboe = &hr_dev->iboe;
  503. spin_lock_init(&iboe->lock);
  504. ib_dev = &hr_dev->ib_dev;
  505. strlcpy(ib_dev->name, "hisi_%d", IB_DEVICE_NAME_MAX);
  506. ib_dev->owner = THIS_MODULE;
  507. ib_dev->node_type = RDMA_NODE_IB_CA;
  508. ib_dev->dma_device = dev;
  509. ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
  510. ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
  511. ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
  512. ib_dev->uverbs_abi_ver = 1;
  513. ib_dev->uverbs_cmd_mask =
  514. (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
  515. (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  516. (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
  517. (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
  518. (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
  519. (1ULL << IB_USER_VERBS_CMD_REG_MR) |
  520. (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
  521. (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  522. (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
  523. (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
  524. (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
  525. (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
  526. (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
  527. (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
  528. /* HCA||device||port */
  529. ib_dev->modify_device = hns_roce_modify_device;
  530. ib_dev->query_device = hns_roce_query_device;
  531. ib_dev->query_port = hns_roce_query_port;
  532. ib_dev->modify_port = hns_roce_modify_port;
  533. ib_dev->get_link_layer = hns_roce_get_link_layer;
  534. ib_dev->get_netdev = hns_roce_get_netdev;
  535. ib_dev->query_gid = hns_roce_query_gid;
  536. ib_dev->query_pkey = hns_roce_query_pkey;
  537. ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
  538. ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
  539. ib_dev->mmap = hns_roce_mmap;
  540. /* PD */
  541. ib_dev->alloc_pd = hns_roce_alloc_pd;
  542. ib_dev->dealloc_pd = hns_roce_dealloc_pd;
  543. /* AH */
  544. ib_dev->create_ah = hns_roce_create_ah;
  545. ib_dev->query_ah = hns_roce_query_ah;
  546. ib_dev->destroy_ah = hns_roce_destroy_ah;
  547. /* QP */
  548. ib_dev->create_qp = hns_roce_create_qp;
  549. ib_dev->modify_qp = hns_roce_modify_qp;
  550. ib_dev->query_qp = hr_dev->hw->query_qp;
  551. ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
  552. ib_dev->post_send = hr_dev->hw->post_send;
  553. ib_dev->post_recv = hr_dev->hw->post_recv;
  554. /* CQ */
  555. ib_dev->create_cq = hns_roce_ib_create_cq;
  556. ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
  557. ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
  558. ib_dev->poll_cq = hr_dev->hw->poll_cq;
  559. /* MR */
  560. ib_dev->get_dma_mr = hns_roce_get_dma_mr;
  561. ib_dev->reg_user_mr = hns_roce_reg_user_mr;
  562. ib_dev->dereg_mr = hns_roce_dereg_mr;
  563. /* OTHERS */
  564. ib_dev->get_port_immutable = hns_roce_port_immutable;
  565. ret = ib_register_device(ib_dev, NULL);
  566. if (ret) {
  567. dev_err(dev, "ib_register_device failed!\n");
  568. return ret;
  569. }
  570. ret = hns_roce_setup_mtu_gids(hr_dev);
  571. if (ret) {
  572. dev_err(dev, "roce_setup_mtu_gids failed!\n");
  573. goto error_failed_setup_mtu_gids;
  574. }
  575. iboe->nb.notifier_call = hns_roce_netdev_event;
  576. ret = register_netdevice_notifier(&iboe->nb);
  577. if (ret) {
  578. dev_err(dev, "register_netdevice_notifier failed!\n");
  579. goto error_failed_setup_mtu_gids;
  580. }
  581. iboe->nb_inet.notifier_call = hns_roce_inet_event;
  582. ret = register_inetaddr_notifier(&iboe->nb_inet);
  583. if (ret) {
  584. dev_err(dev, "register inet addr notifier failed!\n");
  585. goto error_failed_register_inetaddr_notifier;
  586. }
  587. return 0;
  588. error_failed_register_inetaddr_notifier:
  589. unregister_netdevice_notifier(&iboe->nb);
  590. error_failed_setup_mtu_gids:
  591. ib_unregister_device(ib_dev);
  592. return ret;
  593. }
  594. static const struct of_device_id hns_roce_of_match[] = {
  595. { .compatible = "hisilicon,hns-roce-v1", .data = &hns_roce_hw_v1, },
  596. {},
  597. };
  598. MODULE_DEVICE_TABLE(of, hns_roce_of_match);
  599. static const struct acpi_device_id hns_roce_acpi_match[] = {
  600. { "HISI00D1", (kernel_ulong_t)&hns_roce_hw_v1 },
  601. {},
  602. };
  603. MODULE_DEVICE_TABLE(acpi, hns_roce_acpi_match);
  604. static int hns_roce_node_match(struct device *dev, void *fwnode)
  605. {
  606. return dev->fwnode == fwnode;
  607. }
  608. static struct
  609. platform_device *hns_roce_find_pdev(struct fwnode_handle *fwnode)
  610. {
  611. struct device *dev;
  612. /* get the 'device'corresponding to matching 'fwnode' */
  613. dev = bus_find_device(&platform_bus_type, NULL,
  614. fwnode, hns_roce_node_match);
  615. /* get the platform device */
  616. return dev ? to_platform_device(dev) : NULL;
  617. }
  618. static int hns_roce_get_cfg(struct hns_roce_dev *hr_dev)
  619. {
  620. int i;
  621. int ret;
  622. u8 phy_port;
  623. int port_cnt = 0;
  624. struct device *dev = &hr_dev->pdev->dev;
  625. struct device_node *net_node;
  626. struct net_device *netdev = NULL;
  627. struct platform_device *pdev = NULL;
  628. struct resource *res;
  629. /* check if we are compatible with the underlying SoC */
  630. if (dev_of_node(dev)) {
  631. const struct of_device_id *of_id;
  632. of_id = of_match_node(hns_roce_of_match, dev->of_node);
  633. if (!of_id) {
  634. dev_err(dev, "device is not compatible!\n");
  635. return -ENXIO;
  636. }
  637. hr_dev->hw = (struct hns_roce_hw *)of_id->data;
  638. if (!hr_dev->hw) {
  639. dev_err(dev, "couldn't get H/W specific DT data!\n");
  640. return -ENXIO;
  641. }
  642. } else if (is_acpi_device_node(dev->fwnode)) {
  643. const struct acpi_device_id *acpi_id;
  644. acpi_id = acpi_match_device(hns_roce_acpi_match, dev);
  645. if (!acpi_id) {
  646. dev_err(dev, "device is not compatible!\n");
  647. return -ENXIO;
  648. }
  649. hr_dev->hw = (struct hns_roce_hw *) acpi_id->driver_data;
  650. if (!hr_dev->hw) {
  651. dev_err(dev, "couldn't get H/W specific ACPI data!\n");
  652. return -ENXIO;
  653. }
  654. } else {
  655. dev_err(dev, "can't read compatibility data from DT or ACPI\n");
  656. return -ENXIO;
  657. }
  658. /* get the mapped register base address */
  659. res = platform_get_resource(hr_dev->pdev, IORESOURCE_MEM, 0);
  660. if (!res) {
  661. dev_err(dev, "memory resource not found!\n");
  662. return -EINVAL;
  663. }
  664. hr_dev->reg_base = devm_ioremap_resource(dev, res);
  665. if (IS_ERR(hr_dev->reg_base))
  666. return PTR_ERR(hr_dev->reg_base);
  667. /* read the node_guid of IB device from the DT or ACPI */
  668. ret = device_property_read_u8_array(dev, "node-guid",
  669. (u8 *)&hr_dev->ib_dev.node_guid,
  670. GUID_LEN);
  671. if (ret) {
  672. dev_err(dev, "couldn't get node_guid from DT or ACPI!\n");
  673. return ret;
  674. }
  675. /* get the RoCE associated ethernet ports or netdevices */
  676. for (i = 0; i < HNS_ROCE_MAX_PORTS; i++) {
  677. if (dev_of_node(dev)) {
  678. net_node = of_parse_phandle(dev->of_node, "eth-handle",
  679. i);
  680. if (!net_node)
  681. continue;
  682. pdev = of_find_device_by_node(net_node);
  683. } else if (is_acpi_device_node(dev->fwnode)) {
  684. struct acpi_reference_args args;
  685. struct fwnode_handle *fwnode;
  686. ret = acpi_node_get_property_reference(dev->fwnode,
  687. "eth-handle",
  688. i, &args);
  689. if (ret)
  690. continue;
  691. fwnode = acpi_fwnode_handle(args.adev);
  692. pdev = hns_roce_find_pdev(fwnode);
  693. } else {
  694. dev_err(dev, "cannot read data from DT or ACPI\n");
  695. return -ENXIO;
  696. }
  697. if (pdev) {
  698. netdev = platform_get_drvdata(pdev);
  699. phy_port = (u8)i;
  700. if (netdev) {
  701. hr_dev->iboe.netdevs[port_cnt] = netdev;
  702. hr_dev->iboe.phy_port[port_cnt] = phy_port;
  703. } else {
  704. dev_err(dev, "no netdev found with pdev %s\n",
  705. pdev->name);
  706. return -ENODEV;
  707. }
  708. port_cnt++;
  709. }
  710. }
  711. if (port_cnt == 0) {
  712. dev_err(dev, "unable to get eth-handle for available ports!\n");
  713. return -EINVAL;
  714. }
  715. hr_dev->caps.num_ports = port_cnt;
  716. /* cmd issue mode: 0 is poll, 1 is event */
  717. hr_dev->cmd_mod = 1;
  718. hr_dev->loop_idc = 0;
  719. /* read the interrupt names from the DT or ACPI */
  720. ret = device_property_read_string_array(dev, "interrupt-names",
  721. hr_dev->irq_names,
  722. HNS_ROCE_MAX_IRQ_NUM);
  723. if (ret < 0) {
  724. dev_err(dev, "couldn't get interrupt names from DT or ACPI!\n");
  725. return ret;
  726. }
  727. /* fetch the interrupt numbers */
  728. for (i = 0; i < HNS_ROCE_MAX_IRQ_NUM; i++) {
  729. hr_dev->irq[i] = platform_get_irq(hr_dev->pdev, i);
  730. if (hr_dev->irq[i] <= 0) {
  731. dev_err(dev, "platform get of irq[=%d] failed!\n", i);
  732. return -EINVAL;
  733. }
  734. }
  735. return 0;
  736. }
  737. static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
  738. {
  739. int ret;
  740. struct device *dev = &hr_dev->pdev->dev;
  741. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
  742. HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
  743. hr_dev->caps.num_mtt_segs, 1);
  744. if (ret) {
  745. dev_err(dev, "Failed to init MTT context memory, aborting.\n");
  746. return ret;
  747. }
  748. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
  749. HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
  750. hr_dev->caps.num_mtpts, 1);
  751. if (ret) {
  752. dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
  753. goto err_unmap_mtt;
  754. }
  755. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
  756. HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
  757. hr_dev->caps.num_qps, 1);
  758. if (ret) {
  759. dev_err(dev, "Failed to init QP context memory, aborting.\n");
  760. goto err_unmap_dmpt;
  761. }
  762. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
  763. HEM_TYPE_IRRL,
  764. hr_dev->caps.irrl_entry_sz *
  765. hr_dev->caps.max_qp_init_rdma,
  766. hr_dev->caps.num_qps, 1);
  767. if (ret) {
  768. dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
  769. goto err_unmap_qp;
  770. }
  771. ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
  772. HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
  773. hr_dev->caps.num_cqs, 1);
  774. if (ret) {
  775. dev_err(dev, "Failed to init CQ context memory, aborting.\n");
  776. goto err_unmap_irrl;
  777. }
  778. return 0;
  779. err_unmap_irrl:
  780. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
  781. err_unmap_qp:
  782. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
  783. err_unmap_dmpt:
  784. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
  785. err_unmap_mtt:
  786. hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
  787. return ret;
  788. }
  789. /**
  790. * hns_roce_setup_hca - setup host channel adapter
  791. * @hr_dev: pointer to hns roce device
  792. * Return : int
  793. */
  794. static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
  795. {
  796. int ret;
  797. struct device *dev = &hr_dev->pdev->dev;
  798. spin_lock_init(&hr_dev->sm_lock);
  799. spin_lock_init(&hr_dev->bt_cmd_lock);
  800. ret = hns_roce_init_uar_table(hr_dev);
  801. if (ret) {
  802. dev_err(dev, "Failed to initialize uar table. aborting\n");
  803. return ret;
  804. }
  805. ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
  806. if (ret) {
  807. dev_err(dev, "Failed to allocate priv_uar.\n");
  808. goto err_uar_table_free;
  809. }
  810. ret = hns_roce_init_pd_table(hr_dev);
  811. if (ret) {
  812. dev_err(dev, "Failed to init protected domain table.\n");
  813. goto err_uar_alloc_free;
  814. }
  815. ret = hns_roce_init_mr_table(hr_dev);
  816. if (ret) {
  817. dev_err(dev, "Failed to init memory region table.\n");
  818. goto err_pd_table_free;
  819. }
  820. ret = hns_roce_init_cq_table(hr_dev);
  821. if (ret) {
  822. dev_err(dev, "Failed to init completion queue table.\n");
  823. goto err_mr_table_free;
  824. }
  825. ret = hns_roce_init_qp_table(hr_dev);
  826. if (ret) {
  827. dev_err(dev, "Failed to init queue pair table.\n");
  828. goto err_cq_table_free;
  829. }
  830. return 0;
  831. err_cq_table_free:
  832. hns_roce_cleanup_cq_table(hr_dev);
  833. err_mr_table_free:
  834. hns_roce_cleanup_mr_table(hr_dev);
  835. err_pd_table_free:
  836. hns_roce_cleanup_pd_table(hr_dev);
  837. err_uar_alloc_free:
  838. hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
  839. err_uar_table_free:
  840. hns_roce_cleanup_uar_table(hr_dev);
  841. return ret;
  842. }
  843. /**
  844. * hns_roce_probe - RoCE driver entrance
  845. * @pdev: pointer to platform device
  846. * Return : int
  847. *
  848. */
  849. static int hns_roce_probe(struct platform_device *pdev)
  850. {
  851. int ret;
  852. struct hns_roce_dev *hr_dev;
  853. struct device *dev = &pdev->dev;
  854. hr_dev = (struct hns_roce_dev *)ib_alloc_device(sizeof(*hr_dev));
  855. if (!hr_dev)
  856. return -ENOMEM;
  857. memset((u8 *)hr_dev + sizeof(struct ib_device), 0,
  858. sizeof(struct hns_roce_dev) - sizeof(struct ib_device));
  859. hr_dev->pdev = pdev;
  860. platform_set_drvdata(pdev, hr_dev);
  861. if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64ULL)) &&
  862. dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32ULL))) {
  863. dev_err(dev, "Not usable DMA addressing mode\n");
  864. ret = -EIO;
  865. goto error_failed_get_cfg;
  866. }
  867. ret = hns_roce_get_cfg(hr_dev);
  868. if (ret) {
  869. dev_err(dev, "Get Configuration failed!\n");
  870. goto error_failed_get_cfg;
  871. }
  872. ret = hr_dev->hw->reset(hr_dev, true);
  873. if (ret) {
  874. dev_err(dev, "Reset RoCE engine failed!\n");
  875. goto error_failed_get_cfg;
  876. }
  877. hr_dev->hw->hw_profile(hr_dev);
  878. ret = hns_roce_cmd_init(hr_dev);
  879. if (ret) {
  880. dev_err(dev, "cmd init failed!\n");
  881. goto error_failed_cmd_init;
  882. }
  883. ret = hns_roce_init_eq_table(hr_dev);
  884. if (ret) {
  885. dev_err(dev, "eq init failed!\n");
  886. goto error_failed_eq_table;
  887. }
  888. if (hr_dev->cmd_mod) {
  889. ret = hns_roce_cmd_use_events(hr_dev);
  890. if (ret) {
  891. dev_err(dev, "Switch to event-driven cmd failed!\n");
  892. goto error_failed_use_event;
  893. }
  894. }
  895. ret = hns_roce_init_hem(hr_dev);
  896. if (ret) {
  897. dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
  898. goto error_failed_init_hem;
  899. }
  900. ret = hns_roce_setup_hca(hr_dev);
  901. if (ret) {
  902. dev_err(dev, "setup hca failed!\n");
  903. goto error_failed_setup_hca;
  904. }
  905. ret = hr_dev->hw->hw_init(hr_dev);
  906. if (ret) {
  907. dev_err(dev, "hw_init failed!\n");
  908. goto error_failed_engine_init;
  909. }
  910. ret = hns_roce_register_device(hr_dev);
  911. if (ret)
  912. goto error_failed_register_device;
  913. return 0;
  914. error_failed_register_device:
  915. hr_dev->hw->hw_exit(hr_dev);
  916. error_failed_engine_init:
  917. hns_roce_cleanup_bitmap(hr_dev);
  918. error_failed_setup_hca:
  919. hns_roce_cleanup_hem(hr_dev);
  920. error_failed_init_hem:
  921. if (hr_dev->cmd_mod)
  922. hns_roce_cmd_use_polling(hr_dev);
  923. error_failed_use_event:
  924. hns_roce_cleanup_eq_table(hr_dev);
  925. error_failed_eq_table:
  926. hns_roce_cmd_cleanup(hr_dev);
  927. error_failed_cmd_init:
  928. ret = hr_dev->hw->reset(hr_dev, false);
  929. if (ret)
  930. dev_err(&hr_dev->pdev->dev, "roce_engine reset fail\n");
  931. error_failed_get_cfg:
  932. ib_dealloc_device(&hr_dev->ib_dev);
  933. return ret;
  934. }
  935. /**
  936. * hns_roce_remove - remove RoCE device
  937. * @pdev: pointer to platform device
  938. */
  939. static int hns_roce_remove(struct platform_device *pdev)
  940. {
  941. struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);
  942. hns_roce_unregister_device(hr_dev);
  943. hr_dev->hw->hw_exit(hr_dev);
  944. hns_roce_cleanup_bitmap(hr_dev);
  945. hns_roce_cleanup_hem(hr_dev);
  946. if (hr_dev->cmd_mod)
  947. hns_roce_cmd_use_polling(hr_dev);
  948. hns_roce_cleanup_eq_table(hr_dev);
  949. hns_roce_cmd_cleanup(hr_dev);
  950. hr_dev->hw->reset(hr_dev, false);
  951. ib_dealloc_device(&hr_dev->ib_dev);
  952. return 0;
  953. }
  954. static struct platform_driver hns_roce_driver = {
  955. .probe = hns_roce_probe,
  956. .remove = hns_roce_remove,
  957. .driver = {
  958. .name = DRV_NAME,
  959. .of_match_table = hns_roce_of_match,
  960. .acpi_match_table = ACPI_PTR(hns_roce_acpi_match),
  961. },
  962. };
  963. module_platform_driver(hns_roce_driver);
  964. MODULE_LICENSE("Dual BSD/GPL");
  965. MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
  966. MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
  967. MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
  968. MODULE_DESCRIPTION("HNS RoCE Driver");