gpio-zx.c 7.4 KB

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  1. /*
  2. * ZTE ZX296702 GPIO driver
  3. *
  4. * Author: Jun Nie <jun.nie@linaro.org>
  5. *
  6. * Copyright (C) 2015 Linaro Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/bitops.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/gpio/driver.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/init.h>
  18. #include <linux/of.h>
  19. #include <linux/pinctrl/consumer.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm.h>
  22. #include <linux/slab.h>
  23. #include <linux/spinlock.h>
  24. #define ZX_GPIO_DIR 0x00
  25. #define ZX_GPIO_IVE 0x04
  26. #define ZX_GPIO_IV 0x08
  27. #define ZX_GPIO_IEP 0x0C
  28. #define ZX_GPIO_IEN 0x10
  29. #define ZX_GPIO_DI 0x14
  30. #define ZX_GPIO_DO1 0x18
  31. #define ZX_GPIO_DO0 0x1C
  32. #define ZX_GPIO_DO 0x20
  33. #define ZX_GPIO_IM 0x28
  34. #define ZX_GPIO_IE 0x2C
  35. #define ZX_GPIO_MIS 0x30
  36. #define ZX_GPIO_IC 0x34
  37. #define ZX_GPIO_NR 16
  38. struct zx_gpio {
  39. spinlock_t lock;
  40. void __iomem *base;
  41. struct gpio_chip gc;
  42. };
  43. static int zx_direction_input(struct gpio_chip *gc, unsigned offset)
  44. {
  45. struct zx_gpio *chip = gpiochip_get_data(gc);
  46. unsigned long flags;
  47. u16 gpiodir;
  48. if (offset >= gc->ngpio)
  49. return -EINVAL;
  50. spin_lock_irqsave(&chip->lock, flags);
  51. gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
  52. gpiodir &= ~BIT(offset);
  53. writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
  54. spin_unlock_irqrestore(&chip->lock, flags);
  55. return 0;
  56. }
  57. static int zx_direction_output(struct gpio_chip *gc, unsigned offset,
  58. int value)
  59. {
  60. struct zx_gpio *chip = gpiochip_get_data(gc);
  61. unsigned long flags;
  62. u16 gpiodir;
  63. if (offset >= gc->ngpio)
  64. return -EINVAL;
  65. spin_lock_irqsave(&chip->lock, flags);
  66. gpiodir = readw_relaxed(chip->base + ZX_GPIO_DIR);
  67. gpiodir |= BIT(offset);
  68. writew_relaxed(gpiodir, chip->base + ZX_GPIO_DIR);
  69. if (value)
  70. writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
  71. else
  72. writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
  73. spin_unlock_irqrestore(&chip->lock, flags);
  74. return 0;
  75. }
  76. static int zx_get_value(struct gpio_chip *gc, unsigned offset)
  77. {
  78. struct zx_gpio *chip = gpiochip_get_data(gc);
  79. return !!(readw_relaxed(chip->base + ZX_GPIO_DI) & BIT(offset));
  80. }
  81. static void zx_set_value(struct gpio_chip *gc, unsigned offset, int value)
  82. {
  83. struct zx_gpio *chip = gpiochip_get_data(gc);
  84. if (value)
  85. writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO1);
  86. else
  87. writew_relaxed(BIT(offset), chip->base + ZX_GPIO_DO0);
  88. }
  89. static int zx_irq_type(struct irq_data *d, unsigned trigger)
  90. {
  91. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  92. struct zx_gpio *chip = gpiochip_get_data(gc);
  93. int offset = irqd_to_hwirq(d);
  94. unsigned long flags;
  95. u16 gpiois, gpioi_epos, gpioi_eneg, gpioiev;
  96. u16 bit = BIT(offset);
  97. if (offset < 0 || offset >= ZX_GPIO_NR)
  98. return -EINVAL;
  99. spin_lock_irqsave(&chip->lock, flags);
  100. gpioiev = readw_relaxed(chip->base + ZX_GPIO_IV);
  101. gpiois = readw_relaxed(chip->base + ZX_GPIO_IVE);
  102. gpioi_epos = readw_relaxed(chip->base + ZX_GPIO_IEP);
  103. gpioi_eneg = readw_relaxed(chip->base + ZX_GPIO_IEN);
  104. if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
  105. gpiois |= bit;
  106. if (trigger & IRQ_TYPE_LEVEL_HIGH)
  107. gpioiev |= bit;
  108. else
  109. gpioiev &= ~bit;
  110. } else
  111. gpiois &= ~bit;
  112. if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
  113. gpioi_epos |= bit;
  114. gpioi_eneg |= bit;
  115. } else {
  116. if (trigger & IRQ_TYPE_EDGE_RISING) {
  117. gpioi_epos |= bit;
  118. gpioi_eneg &= ~bit;
  119. } else if (trigger & IRQ_TYPE_EDGE_FALLING) {
  120. gpioi_eneg |= bit;
  121. gpioi_epos &= ~bit;
  122. }
  123. }
  124. writew_relaxed(gpiois, chip->base + ZX_GPIO_IVE);
  125. writew_relaxed(gpioi_epos, chip->base + ZX_GPIO_IEP);
  126. writew_relaxed(gpioi_eneg, chip->base + ZX_GPIO_IEN);
  127. writew_relaxed(gpioiev, chip->base + ZX_GPIO_IV);
  128. spin_unlock_irqrestore(&chip->lock, flags);
  129. return 0;
  130. }
  131. static void zx_irq_handler(struct irq_desc *desc)
  132. {
  133. unsigned long pending;
  134. int offset;
  135. struct gpio_chip *gc = irq_desc_get_handler_data(desc);
  136. struct zx_gpio *chip = gpiochip_get_data(gc);
  137. struct irq_chip *irqchip = irq_desc_get_chip(desc);
  138. chained_irq_enter(irqchip, desc);
  139. pending = readw_relaxed(chip->base + ZX_GPIO_MIS);
  140. writew_relaxed(pending, chip->base + ZX_GPIO_IC);
  141. if (pending) {
  142. for_each_set_bit(offset, &pending, ZX_GPIO_NR)
  143. generic_handle_irq(irq_find_mapping(gc->irqdomain,
  144. offset));
  145. }
  146. chained_irq_exit(irqchip, desc);
  147. }
  148. static void zx_irq_mask(struct irq_data *d)
  149. {
  150. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  151. struct zx_gpio *chip = gpiochip_get_data(gc);
  152. u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
  153. u16 gpioie;
  154. spin_lock(&chip->lock);
  155. gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) | mask;
  156. writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
  157. gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) & ~mask;
  158. writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
  159. spin_unlock(&chip->lock);
  160. }
  161. static void zx_irq_unmask(struct irq_data *d)
  162. {
  163. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  164. struct zx_gpio *chip = gpiochip_get_data(gc);
  165. u16 mask = BIT(irqd_to_hwirq(d) % ZX_GPIO_NR);
  166. u16 gpioie;
  167. spin_lock(&chip->lock);
  168. gpioie = readw_relaxed(chip->base + ZX_GPIO_IM) & ~mask;
  169. writew_relaxed(gpioie, chip->base + ZX_GPIO_IM);
  170. gpioie = readw_relaxed(chip->base + ZX_GPIO_IE) | mask;
  171. writew_relaxed(gpioie, chip->base + ZX_GPIO_IE);
  172. spin_unlock(&chip->lock);
  173. }
  174. static struct irq_chip zx_irqchip = {
  175. .name = "zx-gpio",
  176. .irq_mask = zx_irq_mask,
  177. .irq_unmask = zx_irq_unmask,
  178. .irq_set_type = zx_irq_type,
  179. };
  180. static int zx_gpio_probe(struct platform_device *pdev)
  181. {
  182. struct device *dev = &pdev->dev;
  183. struct zx_gpio *chip;
  184. struct resource *res;
  185. int irq, id, ret;
  186. chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
  187. if (!chip)
  188. return -ENOMEM;
  189. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  190. chip->base = devm_ioremap_resource(dev, res);
  191. if (IS_ERR(chip->base))
  192. return PTR_ERR(chip->base);
  193. spin_lock_init(&chip->lock);
  194. if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
  195. chip->gc.request = gpiochip_generic_request;
  196. chip->gc.free = gpiochip_generic_free;
  197. }
  198. id = of_alias_get_id(dev->of_node, "gpio");
  199. chip->gc.direction_input = zx_direction_input;
  200. chip->gc.direction_output = zx_direction_output;
  201. chip->gc.get = zx_get_value;
  202. chip->gc.set = zx_set_value;
  203. chip->gc.base = ZX_GPIO_NR * id;
  204. chip->gc.ngpio = ZX_GPIO_NR;
  205. chip->gc.label = dev_name(dev);
  206. chip->gc.parent = dev;
  207. chip->gc.owner = THIS_MODULE;
  208. ret = gpiochip_add_data(&chip->gc, chip);
  209. if (ret)
  210. return ret;
  211. /*
  212. * irq_chip support
  213. */
  214. writew_relaxed(0xffff, chip->base + ZX_GPIO_IM);
  215. writew_relaxed(0, chip->base + ZX_GPIO_IE);
  216. irq = platform_get_irq(pdev, 0);
  217. if (irq < 0) {
  218. dev_err(dev, "invalid IRQ\n");
  219. gpiochip_remove(&chip->gc);
  220. return -ENODEV;
  221. }
  222. ret = gpiochip_irqchip_add(&chip->gc, &zx_irqchip,
  223. 0, handle_simple_irq,
  224. IRQ_TYPE_NONE);
  225. if (ret) {
  226. dev_err(dev, "could not add irqchip\n");
  227. gpiochip_remove(&chip->gc);
  228. return ret;
  229. }
  230. gpiochip_set_chained_irqchip(&chip->gc, &zx_irqchip,
  231. irq, zx_irq_handler);
  232. platform_set_drvdata(pdev, chip);
  233. dev_info(dev, "ZX GPIO chip registered\n");
  234. return 0;
  235. }
  236. static const struct of_device_id zx_gpio_match[] = {
  237. {
  238. .compatible = "zte,zx296702-gpio",
  239. },
  240. { },
  241. };
  242. static struct platform_driver zx_gpio_driver = {
  243. .probe = zx_gpio_probe,
  244. .driver = {
  245. .name = "zx_gpio",
  246. .of_match_table = of_match_ptr(zx_gpio_match),
  247. },
  248. };
  249. builtin_platform_driver(zx_gpio_driver)