gpio-zevio.c 5.9 KB

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  1. /*
  2. * GPIO controller in LSI ZEVIO SoCs.
  3. *
  4. * Author: Fabian Vogt <fabian@ritter-vogt.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/spinlock.h>
  11. #include <linux/errno.h>
  12. #include <linux/init.h>
  13. #include <linux/bitops.h>
  14. #include <linux/io.h>
  15. #include <linux/of_device.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/slab.h>
  18. #include <linux/gpio.h>
  19. /*
  20. * Memory layout:
  21. * This chip has four gpio sections, each controls 8 GPIOs.
  22. * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
  23. * Disclaimer: Reverse engineered!
  24. * For more information refer to:
  25. * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
  26. *
  27. * 0x00-0x3F: Section 0
  28. * +0x00: Masked interrupt status (read-only)
  29. * +0x04: R: Interrupt status W: Reset interrupt status
  30. * +0x08: R: Interrupt mask W: Mask interrupt
  31. * +0x0C: W: Unmask interrupt (write-only)
  32. * +0x10: Direction: I/O=1/0
  33. * +0x14: Output
  34. * +0x18: Input (read-only)
  35. * +0x20: R: Level interrupt W: Set as level interrupt
  36. * 0x40-0x7F: Section 1
  37. * 0x80-0xBF: Section 2
  38. * 0xC0-0xFF: Section 3
  39. */
  40. #define ZEVIO_GPIO_SECTION_SIZE 0x40
  41. /* Offsets to various registers */
  42. #define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
  43. #define ZEVIO_GPIO_INT_STATUS 0x04
  44. #define ZEVIO_GPIO_INT_UNMASK 0x08
  45. #define ZEVIO_GPIO_INT_MASK 0x0C
  46. #define ZEVIO_GPIO_DIRECTION 0x10
  47. #define ZEVIO_GPIO_OUTPUT 0x14
  48. #define ZEVIO_GPIO_INPUT 0x18
  49. #define ZEVIO_GPIO_INT_STICKY 0x20
  50. /* Bit number of GPIO in its section */
  51. #define ZEVIO_GPIO_BIT(gpio) (gpio&7)
  52. struct zevio_gpio {
  53. spinlock_t lock;
  54. struct of_mm_gpio_chip chip;
  55. };
  56. static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
  57. unsigned port_offset)
  58. {
  59. unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
  60. return readl(IOMEM(c->chip.regs + section_offset + port_offset));
  61. }
  62. static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
  63. unsigned port_offset, u32 val)
  64. {
  65. unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
  66. writel(val, IOMEM(c->chip.regs + section_offset + port_offset));
  67. }
  68. /* Functions for struct gpio_chip */
  69. static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
  70. {
  71. struct zevio_gpio *controller = gpiochip_get_data(chip);
  72. u32 val, dir;
  73. spin_lock(&controller->lock);
  74. dir = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  75. if (dir & BIT(ZEVIO_GPIO_BIT(pin)))
  76. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
  77. else
  78. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  79. spin_unlock(&controller->lock);
  80. return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
  81. }
  82. static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
  83. {
  84. struct zevio_gpio *controller = gpiochip_get_data(chip);
  85. u32 val;
  86. spin_lock(&controller->lock);
  87. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  88. if (value)
  89. val |= BIT(ZEVIO_GPIO_BIT(pin));
  90. else
  91. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  92. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
  93. spin_unlock(&controller->lock);
  94. }
  95. static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
  96. {
  97. struct zevio_gpio *controller = gpiochip_get_data(chip);
  98. u32 val;
  99. spin_lock(&controller->lock);
  100. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  101. val |= BIT(ZEVIO_GPIO_BIT(pin));
  102. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
  103. spin_unlock(&controller->lock);
  104. return 0;
  105. }
  106. static int zevio_gpio_direction_output(struct gpio_chip *chip,
  107. unsigned pin, int value)
  108. {
  109. struct zevio_gpio *controller = gpiochip_get_data(chip);
  110. u32 val;
  111. spin_lock(&controller->lock);
  112. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
  113. if (value)
  114. val |= BIT(ZEVIO_GPIO_BIT(pin));
  115. else
  116. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  117. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
  118. val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
  119. val &= ~BIT(ZEVIO_GPIO_BIT(pin));
  120. zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
  121. spin_unlock(&controller->lock);
  122. return 0;
  123. }
  124. static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
  125. {
  126. /*
  127. * TODO: Implement IRQs.
  128. * Not implemented yet due to weird lockups
  129. */
  130. return -ENXIO;
  131. }
  132. static struct gpio_chip zevio_gpio_chip = {
  133. .direction_input = zevio_gpio_direction_input,
  134. .direction_output = zevio_gpio_direction_output,
  135. .set = zevio_gpio_set,
  136. .get = zevio_gpio_get,
  137. .to_irq = zevio_gpio_to_irq,
  138. .base = 0,
  139. .owner = THIS_MODULE,
  140. .ngpio = 32,
  141. .of_gpio_n_cells = 2,
  142. };
  143. /* Initialization */
  144. static int zevio_gpio_probe(struct platform_device *pdev)
  145. {
  146. struct zevio_gpio *controller;
  147. int status, i;
  148. controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
  149. if (!controller)
  150. return -ENOMEM;
  151. platform_set_drvdata(pdev, controller);
  152. /* Copy our reference */
  153. controller->chip.gc = zevio_gpio_chip;
  154. controller->chip.gc.parent = &pdev->dev;
  155. status = of_mm_gpiochip_add_data(pdev->dev.of_node,
  156. &(controller->chip),
  157. controller);
  158. if (status) {
  159. dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
  160. return status;
  161. }
  162. spin_lock_init(&controller->lock);
  163. /* Disable interrupts, they only cause errors */
  164. for (i = 0; i < controller->chip.gc.ngpio; i += 8)
  165. zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
  166. dev_dbg(controller->chip.gc.parent, "ZEVIO GPIO controller set up!\n");
  167. return 0;
  168. }
  169. static const struct of_device_id zevio_gpio_of_match[] = {
  170. { .compatible = "lsi,zevio-gpio", },
  171. { },
  172. };
  173. static struct platform_driver zevio_gpio_driver = {
  174. .driver = {
  175. .name = "gpio-zevio",
  176. .of_match_table = zevio_gpio_of_match,
  177. .suppress_bind_attrs = true,
  178. },
  179. .probe = zevio_gpio_probe,
  180. };
  181. builtin_platform_driver(zevio_gpio_driver);