gpio-xgene-sb.c 9.8 KB

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  1. /*
  2. * AppliedMicro X-Gene SoC GPIO-Standby Driver
  3. *
  4. * Copyright (c) 2014, Applied Micro Circuits Corporation
  5. * Author: Tin Huynh <tnhuynh@apm.com>.
  6. * Y Vo <yvo@apm.com>.
  7. * Quan Nguyen <qnguyen@apm.com>.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  21. */
  22. #include <linux/module.h>
  23. #include <linux/io.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/of_gpio.h>
  26. #include <linux/gpio/driver.h>
  27. #include <linux/acpi.h>
  28. #include "gpiolib.h"
  29. /* Common property names */
  30. #define XGENE_NIRQ_PROPERTY "apm,nr-irqs"
  31. #define XGENE_NGPIO_PROPERTY "apm,nr-gpios"
  32. #define XGENE_IRQ_START_PROPERTY "apm,irq-start"
  33. #define XGENE_DFLT_MAX_NGPIO 22
  34. #define XGENE_DFLT_MAX_NIRQ 6
  35. #define XGENE_DFLT_IRQ_START_PIN 8
  36. #define GPIO_MASK(x) (1U << ((x) % 32))
  37. #define MPA_GPIO_INT_LVL 0x0290
  38. #define MPA_GPIO_OE_ADDR 0x029c
  39. #define MPA_GPIO_OUT_ADDR 0x02a0
  40. #define MPA_GPIO_IN_ADDR 0x02a4
  41. #define MPA_GPIO_SEL_LO 0x0294
  42. #define GPIO_INT_LEVEL_H 0x000001
  43. #define GPIO_INT_LEVEL_L 0x000000
  44. /**
  45. * struct xgene_gpio_sb - GPIO-Standby private data structure.
  46. * @gc: memory-mapped GPIO controllers.
  47. * @regs: GPIO register base offset
  48. * @irq_domain: GPIO interrupt domain
  49. * @irq_start: GPIO pin that start support interrupt
  50. * @nirq: Number of GPIO pins that supports interrupt
  51. * @parent_irq_base: Start parent HWIRQ
  52. */
  53. struct xgene_gpio_sb {
  54. struct gpio_chip gc;
  55. void __iomem *regs;
  56. struct irq_domain *irq_domain;
  57. u16 irq_start;
  58. u16 nirq;
  59. u16 parent_irq_base;
  60. };
  61. #define HWIRQ_TO_GPIO(priv, hwirq) ((hwirq) + (priv)->irq_start)
  62. #define GPIO_TO_HWIRQ(priv, gpio) ((gpio) - (priv)->irq_start)
  63. static void xgene_gpio_set_bit(struct gpio_chip *gc,
  64. void __iomem *reg, u32 gpio, int val)
  65. {
  66. u32 data;
  67. data = gc->read_reg(reg);
  68. if (val)
  69. data |= GPIO_MASK(gpio);
  70. else
  71. data &= ~GPIO_MASK(gpio);
  72. gc->write_reg(reg, data);
  73. }
  74. static int xgene_gpio_sb_irq_set_type(struct irq_data *d, unsigned int type)
  75. {
  76. struct xgene_gpio_sb *priv = irq_data_get_irq_chip_data(d);
  77. int gpio = HWIRQ_TO_GPIO(priv, d->hwirq);
  78. int lvl_type = GPIO_INT_LEVEL_H;
  79. switch (type & IRQ_TYPE_SENSE_MASK) {
  80. case IRQ_TYPE_EDGE_RISING:
  81. case IRQ_TYPE_LEVEL_HIGH:
  82. lvl_type = GPIO_INT_LEVEL_H;
  83. break;
  84. case IRQ_TYPE_EDGE_FALLING:
  85. case IRQ_TYPE_LEVEL_LOW:
  86. lvl_type = GPIO_INT_LEVEL_L;
  87. break;
  88. default:
  89. break;
  90. }
  91. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  92. gpio * 2, 1);
  93. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_INT_LVL,
  94. d->hwirq, lvl_type);
  95. /* Propagate IRQ type setting to parent */
  96. if (type & IRQ_TYPE_EDGE_BOTH)
  97. return irq_chip_set_type_parent(d, IRQ_TYPE_EDGE_RISING);
  98. else
  99. return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
  100. }
  101. static struct irq_chip xgene_gpio_sb_irq_chip = {
  102. .name = "sbgpio",
  103. .irq_eoi = irq_chip_eoi_parent,
  104. .irq_mask = irq_chip_mask_parent,
  105. .irq_unmask = irq_chip_unmask_parent,
  106. .irq_set_type = xgene_gpio_sb_irq_set_type,
  107. };
  108. static int xgene_gpio_sb_to_irq(struct gpio_chip *gc, u32 gpio)
  109. {
  110. struct xgene_gpio_sb *priv = gpiochip_get_data(gc);
  111. struct irq_fwspec fwspec;
  112. if ((gpio < priv->irq_start) ||
  113. (gpio > HWIRQ_TO_GPIO(priv, priv->nirq)))
  114. return -ENXIO;
  115. if (gc->parent->of_node)
  116. fwspec.fwnode = of_node_to_fwnode(gc->parent->of_node);
  117. else
  118. fwspec.fwnode = gc->parent->fwnode;
  119. fwspec.param_count = 2;
  120. fwspec.param[0] = GPIO_TO_HWIRQ(priv, gpio);
  121. fwspec.param[1] = IRQ_TYPE_NONE;
  122. return irq_create_fwspec_mapping(&fwspec);
  123. }
  124. static void xgene_gpio_sb_domain_activate(struct irq_domain *d,
  125. struct irq_data *irq_data)
  126. {
  127. struct xgene_gpio_sb *priv = d->host_data;
  128. u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
  129. if (gpiochip_lock_as_irq(&priv->gc, gpio)) {
  130. dev_err(priv->gc.parent,
  131. "Unable to configure XGene GPIO standby pin %d as IRQ\n",
  132. gpio);
  133. return;
  134. }
  135. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  136. gpio * 2, 1);
  137. }
  138. static void xgene_gpio_sb_domain_deactivate(struct irq_domain *d,
  139. struct irq_data *irq_data)
  140. {
  141. struct xgene_gpio_sb *priv = d->host_data;
  142. u32 gpio = HWIRQ_TO_GPIO(priv, irq_data->hwirq);
  143. gpiochip_unlock_as_irq(&priv->gc, gpio);
  144. xgene_gpio_set_bit(&priv->gc, priv->regs + MPA_GPIO_SEL_LO,
  145. gpio * 2, 0);
  146. }
  147. static int xgene_gpio_sb_domain_translate(struct irq_domain *d,
  148. struct irq_fwspec *fwspec,
  149. unsigned long *hwirq,
  150. unsigned int *type)
  151. {
  152. struct xgene_gpio_sb *priv = d->host_data;
  153. if ((fwspec->param_count != 2) ||
  154. (fwspec->param[0] >= priv->nirq))
  155. return -EINVAL;
  156. *hwirq = fwspec->param[0];
  157. *type = fwspec->param[1];
  158. return 0;
  159. }
  160. static int xgene_gpio_sb_domain_alloc(struct irq_domain *domain,
  161. unsigned int virq,
  162. unsigned int nr_irqs, void *data)
  163. {
  164. struct irq_fwspec *fwspec = data;
  165. struct irq_fwspec parent_fwspec;
  166. struct xgene_gpio_sb *priv = domain->host_data;
  167. irq_hw_number_t hwirq;
  168. unsigned int i;
  169. hwirq = fwspec->param[0];
  170. for (i = 0; i < nr_irqs; i++)
  171. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  172. &xgene_gpio_sb_irq_chip, priv);
  173. parent_fwspec.fwnode = domain->parent->fwnode;
  174. if (is_of_node(parent_fwspec.fwnode)) {
  175. parent_fwspec.param_count = 3;
  176. parent_fwspec.param[0] = 0;/* SPI */
  177. /* Skip SGIs and PPIs*/
  178. parent_fwspec.param[1] = hwirq + priv->parent_irq_base - 32;
  179. parent_fwspec.param[2] = fwspec->param[1];
  180. } else if (is_fwnode_irqchip(parent_fwspec.fwnode)) {
  181. parent_fwspec.param_count = 2;
  182. parent_fwspec.param[0] = hwirq + priv->parent_irq_base;
  183. parent_fwspec.param[1] = fwspec->param[1];
  184. } else
  185. return -EINVAL;
  186. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
  187. &parent_fwspec);
  188. }
  189. static const struct irq_domain_ops xgene_gpio_sb_domain_ops = {
  190. .translate = xgene_gpio_sb_domain_translate,
  191. .alloc = xgene_gpio_sb_domain_alloc,
  192. .free = irq_domain_free_irqs_common,
  193. .activate = xgene_gpio_sb_domain_activate,
  194. .deactivate = xgene_gpio_sb_domain_deactivate,
  195. };
  196. static int xgene_gpio_sb_probe(struct platform_device *pdev)
  197. {
  198. struct xgene_gpio_sb *priv;
  199. int ret;
  200. struct resource *res;
  201. void __iomem *regs;
  202. struct irq_domain *parent_domain = NULL;
  203. struct fwnode_handle *fwnode;
  204. u32 val32;
  205. priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
  206. if (!priv)
  207. return -ENOMEM;
  208. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  209. regs = devm_ioremap_resource(&pdev->dev, res);
  210. if (IS_ERR(regs))
  211. return PTR_ERR(regs);
  212. priv->regs = regs;
  213. ret = platform_get_irq(pdev, 0);
  214. if (ret > 0) {
  215. priv->parent_irq_base = irq_get_irq_data(ret)->hwirq;
  216. parent_domain = irq_get_irq_data(ret)->domain;
  217. }
  218. if (!parent_domain) {
  219. dev_err(&pdev->dev, "unable to obtain parent domain\n");
  220. return -ENODEV;
  221. }
  222. ret = bgpio_init(&priv->gc, &pdev->dev, 4,
  223. regs + MPA_GPIO_IN_ADDR,
  224. regs + MPA_GPIO_OUT_ADDR, NULL,
  225. regs + MPA_GPIO_OE_ADDR, NULL, 0);
  226. if (ret)
  227. return ret;
  228. priv->gc.to_irq = xgene_gpio_sb_to_irq;
  229. /* Retrieve start irq pin, use default if property not found */
  230. priv->irq_start = XGENE_DFLT_IRQ_START_PIN;
  231. if (!device_property_read_u32(&pdev->dev,
  232. XGENE_IRQ_START_PROPERTY, &val32))
  233. priv->irq_start = val32;
  234. /* Retrieve number irqs, use default if property not found */
  235. priv->nirq = XGENE_DFLT_MAX_NIRQ;
  236. if (!device_property_read_u32(&pdev->dev, XGENE_NIRQ_PROPERTY, &val32))
  237. priv->nirq = val32;
  238. /* Retrieve number gpio, use default if property not found */
  239. priv->gc.ngpio = XGENE_DFLT_MAX_NGPIO;
  240. if (!device_property_read_u32(&pdev->dev, XGENE_NGPIO_PROPERTY, &val32))
  241. priv->gc.ngpio = val32;
  242. dev_info(&pdev->dev, "Support %d gpios, %d irqs start from pin %d\n",
  243. priv->gc.ngpio, priv->nirq, priv->irq_start);
  244. platform_set_drvdata(pdev, priv);
  245. if (pdev->dev.of_node)
  246. fwnode = of_node_to_fwnode(pdev->dev.of_node);
  247. else
  248. fwnode = pdev->dev.fwnode;
  249. priv->irq_domain = irq_domain_create_hierarchy(parent_domain,
  250. 0, priv->nirq, fwnode,
  251. &xgene_gpio_sb_domain_ops, priv);
  252. if (!priv->irq_domain)
  253. return -ENODEV;
  254. priv->gc.irqdomain = priv->irq_domain;
  255. ret = devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
  256. if (ret) {
  257. dev_err(&pdev->dev,
  258. "failed to register X-Gene GPIO Standby driver\n");
  259. irq_domain_remove(priv->irq_domain);
  260. return ret;
  261. }
  262. dev_info(&pdev->dev, "X-Gene GPIO Standby driver registered\n");
  263. if (priv->nirq > 0) {
  264. /* Register interrupt handlers for gpio signaled acpi events */
  265. acpi_gpiochip_request_interrupts(&priv->gc);
  266. }
  267. return ret;
  268. }
  269. static int xgene_gpio_sb_remove(struct platform_device *pdev)
  270. {
  271. struct xgene_gpio_sb *priv = platform_get_drvdata(pdev);
  272. if (priv->nirq > 0) {
  273. acpi_gpiochip_free_interrupts(&priv->gc);
  274. }
  275. irq_domain_remove(priv->irq_domain);
  276. return 0;
  277. }
  278. static const struct of_device_id xgene_gpio_sb_of_match[] = {
  279. {.compatible = "apm,xgene-gpio-sb", },
  280. {},
  281. };
  282. MODULE_DEVICE_TABLE(of, xgene_gpio_sb_of_match);
  283. #ifdef CONFIG_ACPI
  284. static const struct acpi_device_id xgene_gpio_sb_acpi_match[] = {
  285. {"APMC0D15", 0},
  286. {},
  287. };
  288. MODULE_DEVICE_TABLE(acpi, xgene_gpio_sb_acpi_match);
  289. #endif
  290. static struct platform_driver xgene_gpio_sb_driver = {
  291. .driver = {
  292. .name = "xgene-gpio-sb",
  293. .of_match_table = xgene_gpio_sb_of_match,
  294. .acpi_match_table = ACPI_PTR(xgene_gpio_sb_acpi_match),
  295. },
  296. .probe = xgene_gpio_sb_probe,
  297. .remove = xgene_gpio_sb_remove,
  298. };
  299. module_platform_driver(xgene_gpio_sb_driver);
  300. MODULE_AUTHOR("AppliedMicro");
  301. MODULE_DESCRIPTION("APM X-Gene GPIO Standby driver");
  302. MODULE_LICENSE("GPL");