gpio-pca953x.c 24 KB

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  1. /*
  2. * PCA953x 4/8/16/24/40 bit I/O ports
  3. *
  4. * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
  5. * Copyright (C) 2007 Marvell International Ltd.
  6. *
  7. * Derived from drivers/i2c/chips/pca9539.c
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; version 2 of the License.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_data/pca953x.h>
  19. #include <linux/slab.h>
  20. #include <asm/unaligned.h>
  21. #include <linux/of_platform.h>
  22. #include <linux/acpi.h>
  23. #include <linux/regulator/consumer.h>
  24. #define PCA953X_INPUT 0
  25. #define PCA953X_OUTPUT 1
  26. #define PCA953X_INVERT 2
  27. #define PCA953X_DIRECTION 3
  28. #define REG_ADDR_AI 0x80
  29. #define PCA957X_IN 0
  30. #define PCA957X_INVRT 1
  31. #define PCA957X_BKEN 2
  32. #define PCA957X_PUPD 3
  33. #define PCA957X_CFG 4
  34. #define PCA957X_OUT 5
  35. #define PCA957X_MSK 6
  36. #define PCA957X_INTS 7
  37. #define PCAL953X_IN_LATCH 34
  38. #define PCAL953X_INT_MASK 37
  39. #define PCAL953X_INT_STAT 38
  40. #define PCA_GPIO_MASK 0x00FF
  41. #define PCA_INT 0x0100
  42. #define PCA_PCAL 0x0200
  43. #define PCA953X_TYPE 0x1000
  44. #define PCA957X_TYPE 0x2000
  45. #define PCA_TYPE_MASK 0xF000
  46. #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
  47. static const struct i2c_device_id pca953x_id[] = {
  48. { "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
  49. { "pca9534", 8 | PCA953X_TYPE | PCA_INT, },
  50. { "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
  51. { "pca9536", 4 | PCA953X_TYPE, },
  52. { "pca9537", 4 | PCA953X_TYPE | PCA_INT, },
  53. { "pca9538", 8 | PCA953X_TYPE | PCA_INT, },
  54. { "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
  55. { "pca9554", 8 | PCA953X_TYPE | PCA_INT, },
  56. { "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
  57. { "pca9556", 8 | PCA953X_TYPE, },
  58. { "pca9557", 8 | PCA953X_TYPE, },
  59. { "pca9574", 8 | PCA957X_TYPE | PCA_INT, },
  60. { "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
  61. { "pca9698", 40 | PCA953X_TYPE, },
  62. { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  63. { "max7310", 8 | PCA953X_TYPE, },
  64. { "max7312", 16 | PCA953X_TYPE | PCA_INT, },
  65. { "max7313", 16 | PCA953X_TYPE | PCA_INT, },
  66. { "max7315", 8 | PCA953X_TYPE | PCA_INT, },
  67. { "pca6107", 8 | PCA953X_TYPE | PCA_INT, },
  68. { "tca6408", 8 | PCA953X_TYPE | PCA_INT, },
  69. { "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
  70. { "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
  71. { "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
  72. { "xra1202", 8 | PCA953X_TYPE },
  73. { }
  74. };
  75. MODULE_DEVICE_TABLE(i2c, pca953x_id);
  76. static const struct acpi_device_id pca953x_acpi_ids[] = {
  77. { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, },
  78. { }
  79. };
  80. MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);
  81. #define MAX_BANK 5
  82. #define BANK_SZ 8
  83. #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
  84. struct pca953x_reg_config {
  85. int direction;
  86. int output;
  87. int input;
  88. };
  89. static const struct pca953x_reg_config pca953x_regs = {
  90. .direction = PCA953X_DIRECTION,
  91. .output = PCA953X_OUTPUT,
  92. .input = PCA953X_INPUT,
  93. };
  94. static const struct pca953x_reg_config pca957x_regs = {
  95. .direction = PCA957X_CFG,
  96. .output = PCA957X_OUT,
  97. .input = PCA957X_IN,
  98. };
  99. struct pca953x_chip {
  100. unsigned gpio_start;
  101. u8 reg_output[MAX_BANK];
  102. u8 reg_direction[MAX_BANK];
  103. struct mutex i2c_lock;
  104. #ifdef CONFIG_GPIO_PCA953X_IRQ
  105. struct mutex irq_lock;
  106. u8 irq_mask[MAX_BANK];
  107. u8 irq_stat[MAX_BANK];
  108. u8 irq_trig_raise[MAX_BANK];
  109. u8 irq_trig_fall[MAX_BANK];
  110. #endif
  111. struct i2c_client *client;
  112. struct gpio_chip gpio_chip;
  113. const char *const *names;
  114. unsigned long driver_data;
  115. struct regulator *regulator;
  116. const struct pca953x_reg_config *regs;
  117. int (*write_regs)(struct pca953x_chip *, int, u8 *);
  118. int (*read_regs)(struct pca953x_chip *, int, u8 *);
  119. };
  120. static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val,
  121. int off)
  122. {
  123. int ret;
  124. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  125. int offset = off / BANK_SZ;
  126. ret = i2c_smbus_read_byte_data(chip->client,
  127. (reg << bank_shift) + offset);
  128. *val = ret;
  129. if (ret < 0) {
  130. dev_err(&chip->client->dev, "failed reading register\n");
  131. return ret;
  132. }
  133. return 0;
  134. }
  135. static int pca953x_write_single(struct pca953x_chip *chip, int reg, u32 val,
  136. int off)
  137. {
  138. int ret;
  139. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  140. int offset = off / BANK_SZ;
  141. ret = i2c_smbus_write_byte_data(chip->client,
  142. (reg << bank_shift) + offset, val);
  143. if (ret < 0) {
  144. dev_err(&chip->client->dev, "failed writing register\n");
  145. return ret;
  146. }
  147. return 0;
  148. }
  149. static int pca953x_write_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  150. {
  151. return i2c_smbus_write_byte_data(chip->client, reg, *val);
  152. }
  153. static int pca953x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  154. {
  155. __le16 word = cpu_to_le16(get_unaligned((u16 *)val));
  156. return i2c_smbus_write_word_data(chip->client,
  157. reg << 1, (__force u16)word);
  158. }
  159. static int pca957x_write_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  160. {
  161. int ret;
  162. ret = i2c_smbus_write_byte_data(chip->client, reg << 1, val[0]);
  163. if (ret < 0)
  164. return ret;
  165. return i2c_smbus_write_byte_data(chip->client, (reg << 1) + 1, val[1]);
  166. }
  167. static int pca953x_write_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  168. {
  169. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  170. return i2c_smbus_write_i2c_block_data(chip->client,
  171. (reg << bank_shift) | REG_ADDR_AI,
  172. NBANK(chip), val);
  173. }
  174. static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
  175. {
  176. int ret = 0;
  177. ret = chip->write_regs(chip, reg, val);
  178. if (ret < 0) {
  179. dev_err(&chip->client->dev, "failed writing register\n");
  180. return ret;
  181. }
  182. return 0;
  183. }
  184. static int pca953x_read_regs_8(struct pca953x_chip *chip, int reg, u8 *val)
  185. {
  186. int ret;
  187. ret = i2c_smbus_read_byte_data(chip->client, reg);
  188. *val = ret;
  189. return ret;
  190. }
  191. static int pca953x_read_regs_16(struct pca953x_chip *chip, int reg, u8 *val)
  192. {
  193. int ret;
  194. ret = i2c_smbus_read_word_data(chip->client, reg << 1);
  195. val[0] = (u16)ret & 0xFF;
  196. val[1] = (u16)ret >> 8;
  197. return ret;
  198. }
  199. static int pca953x_read_regs_24(struct pca953x_chip *chip, int reg, u8 *val)
  200. {
  201. int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  202. return i2c_smbus_read_i2c_block_data(chip->client,
  203. (reg << bank_shift) | REG_ADDR_AI,
  204. NBANK(chip), val);
  205. }
  206. static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
  207. {
  208. int ret;
  209. ret = chip->read_regs(chip, reg, val);
  210. if (ret < 0) {
  211. dev_err(&chip->client->dev, "failed reading register\n");
  212. return ret;
  213. }
  214. return 0;
  215. }
  216. static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
  217. {
  218. struct pca953x_chip *chip = gpiochip_get_data(gc);
  219. u8 reg_val;
  220. int ret;
  221. mutex_lock(&chip->i2c_lock);
  222. reg_val = chip->reg_direction[off / BANK_SZ] | (1u << (off % BANK_SZ));
  223. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  224. if (ret)
  225. goto exit;
  226. chip->reg_direction[off / BANK_SZ] = reg_val;
  227. exit:
  228. mutex_unlock(&chip->i2c_lock);
  229. return ret;
  230. }
  231. static int pca953x_gpio_direction_output(struct gpio_chip *gc,
  232. unsigned off, int val)
  233. {
  234. struct pca953x_chip *chip = gpiochip_get_data(gc);
  235. u8 reg_val;
  236. int ret;
  237. mutex_lock(&chip->i2c_lock);
  238. /* set output level */
  239. if (val)
  240. reg_val = chip->reg_output[off / BANK_SZ]
  241. | (1u << (off % BANK_SZ));
  242. else
  243. reg_val = chip->reg_output[off / BANK_SZ]
  244. & ~(1u << (off % BANK_SZ));
  245. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  246. if (ret)
  247. goto exit;
  248. chip->reg_output[off / BANK_SZ] = reg_val;
  249. /* then direction */
  250. reg_val = chip->reg_direction[off / BANK_SZ] & ~(1u << (off % BANK_SZ));
  251. ret = pca953x_write_single(chip, chip->regs->direction, reg_val, off);
  252. if (ret)
  253. goto exit;
  254. chip->reg_direction[off / BANK_SZ] = reg_val;
  255. exit:
  256. mutex_unlock(&chip->i2c_lock);
  257. return ret;
  258. }
  259. static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
  260. {
  261. struct pca953x_chip *chip = gpiochip_get_data(gc);
  262. u32 reg_val;
  263. int ret;
  264. mutex_lock(&chip->i2c_lock);
  265. ret = pca953x_read_single(chip, chip->regs->input, &reg_val, off);
  266. mutex_unlock(&chip->i2c_lock);
  267. if (ret < 0) {
  268. /* NOTE: diagnostic already emitted; that's all we should
  269. * do unless gpio_*_value_cansleep() calls become different
  270. * from their nonsleeping siblings (and report faults).
  271. */
  272. return 0;
  273. }
  274. return (reg_val & (1u << (off % BANK_SZ))) ? 1 : 0;
  275. }
  276. static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
  277. {
  278. struct pca953x_chip *chip = gpiochip_get_data(gc);
  279. u8 reg_val;
  280. int ret;
  281. mutex_lock(&chip->i2c_lock);
  282. if (val)
  283. reg_val = chip->reg_output[off / BANK_SZ]
  284. | (1u << (off % BANK_SZ));
  285. else
  286. reg_val = chip->reg_output[off / BANK_SZ]
  287. & ~(1u << (off % BANK_SZ));
  288. ret = pca953x_write_single(chip, chip->regs->output, reg_val, off);
  289. if (ret)
  290. goto exit;
  291. chip->reg_output[off / BANK_SZ] = reg_val;
  292. exit:
  293. mutex_unlock(&chip->i2c_lock);
  294. }
  295. static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
  296. unsigned long *mask, unsigned long *bits)
  297. {
  298. struct pca953x_chip *chip = gpiochip_get_data(gc);
  299. unsigned int bank_mask, bank_val;
  300. int bank_shift, bank;
  301. u8 reg_val[MAX_BANK];
  302. int ret;
  303. bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
  304. mutex_lock(&chip->i2c_lock);
  305. memcpy(reg_val, chip->reg_output, NBANK(chip));
  306. for (bank = 0; bank < NBANK(chip); bank++) {
  307. bank_mask = mask[bank / sizeof(*mask)] >>
  308. ((bank % sizeof(*mask)) * 8);
  309. if (bank_mask) {
  310. bank_val = bits[bank / sizeof(*bits)] >>
  311. ((bank % sizeof(*bits)) * 8);
  312. bank_val &= bank_mask;
  313. reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
  314. }
  315. }
  316. ret = i2c_smbus_write_i2c_block_data(chip->client,
  317. chip->regs->output << bank_shift,
  318. NBANK(chip), reg_val);
  319. if (ret)
  320. goto exit;
  321. memcpy(chip->reg_output, reg_val, NBANK(chip));
  322. exit:
  323. mutex_unlock(&chip->i2c_lock);
  324. }
  325. static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
  326. {
  327. struct gpio_chip *gc;
  328. gc = &chip->gpio_chip;
  329. gc->direction_input = pca953x_gpio_direction_input;
  330. gc->direction_output = pca953x_gpio_direction_output;
  331. gc->get = pca953x_gpio_get_value;
  332. gc->set = pca953x_gpio_set_value;
  333. gc->set_multiple = pca953x_gpio_set_multiple;
  334. gc->can_sleep = true;
  335. gc->base = chip->gpio_start;
  336. gc->ngpio = gpios;
  337. gc->label = chip->client->name;
  338. gc->parent = &chip->client->dev;
  339. gc->owner = THIS_MODULE;
  340. gc->names = chip->names;
  341. }
  342. #ifdef CONFIG_GPIO_PCA953X_IRQ
  343. static void pca953x_irq_mask(struct irq_data *d)
  344. {
  345. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  346. struct pca953x_chip *chip = gpiochip_get_data(gc);
  347. chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
  348. }
  349. static void pca953x_irq_unmask(struct irq_data *d)
  350. {
  351. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  352. struct pca953x_chip *chip = gpiochip_get_data(gc);
  353. chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
  354. }
  355. static void pca953x_irq_bus_lock(struct irq_data *d)
  356. {
  357. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  358. struct pca953x_chip *chip = gpiochip_get_data(gc);
  359. mutex_lock(&chip->irq_lock);
  360. }
  361. static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
  362. {
  363. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  364. struct pca953x_chip *chip = gpiochip_get_data(gc);
  365. u8 new_irqs;
  366. int level, i;
  367. u8 invert_irq_mask[MAX_BANK];
  368. if (chip->driver_data & PCA_PCAL) {
  369. /* Enable latch on interrupt-enabled inputs */
  370. pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);
  371. for (i = 0; i < NBANK(chip); i++)
  372. invert_irq_mask[i] = ~chip->irq_mask[i];
  373. /* Unmask enabled interrupts */
  374. pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
  375. }
  376. /* Look for any newly setup interrupt */
  377. for (i = 0; i < NBANK(chip); i++) {
  378. new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
  379. new_irqs &= ~chip->reg_direction[i];
  380. while (new_irqs) {
  381. level = __ffs(new_irqs);
  382. pca953x_gpio_direction_input(&chip->gpio_chip,
  383. level + (BANK_SZ * i));
  384. new_irqs &= ~(1 << level);
  385. }
  386. }
  387. mutex_unlock(&chip->irq_lock);
  388. }
  389. static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
  390. {
  391. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  392. struct pca953x_chip *chip = gpiochip_get_data(gc);
  393. int bank_nb = d->hwirq / BANK_SZ;
  394. u8 mask = 1 << (d->hwirq % BANK_SZ);
  395. if (!(type & IRQ_TYPE_EDGE_BOTH)) {
  396. dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
  397. d->irq, type);
  398. return -EINVAL;
  399. }
  400. if (type & IRQ_TYPE_EDGE_FALLING)
  401. chip->irq_trig_fall[bank_nb] |= mask;
  402. else
  403. chip->irq_trig_fall[bank_nb] &= ~mask;
  404. if (type & IRQ_TYPE_EDGE_RISING)
  405. chip->irq_trig_raise[bank_nb] |= mask;
  406. else
  407. chip->irq_trig_raise[bank_nb] &= ~mask;
  408. return 0;
  409. }
  410. static struct irq_chip pca953x_irq_chip = {
  411. .name = "pca953x",
  412. .irq_mask = pca953x_irq_mask,
  413. .irq_unmask = pca953x_irq_unmask,
  414. .irq_bus_lock = pca953x_irq_bus_lock,
  415. .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock,
  416. .irq_set_type = pca953x_irq_set_type,
  417. };
  418. static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
  419. {
  420. u8 cur_stat[MAX_BANK];
  421. u8 old_stat[MAX_BANK];
  422. bool pending_seen = false;
  423. bool trigger_seen = false;
  424. u8 trigger[MAX_BANK];
  425. int ret, i;
  426. if (chip->driver_data & PCA_PCAL) {
  427. /* Read the current interrupt status from the device */
  428. ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
  429. if (ret)
  430. return false;
  431. /* Check latched inputs and clear interrupt status */
  432. ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
  433. if (ret)
  434. return false;
  435. for (i = 0; i < NBANK(chip); i++) {
  436. /* Apply filter for rising/falling edge selection */
  437. pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
  438. (cur_stat[i] & chip->irq_trig_raise[i]);
  439. pending[i] &= trigger[i];
  440. if (pending[i])
  441. pending_seen = true;
  442. }
  443. return pending_seen;
  444. }
  445. ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
  446. if (ret)
  447. return false;
  448. /* Remove output pins from the equation */
  449. for (i = 0; i < NBANK(chip); i++)
  450. cur_stat[i] &= chip->reg_direction[i];
  451. memcpy(old_stat, chip->irq_stat, NBANK(chip));
  452. for (i = 0; i < NBANK(chip); i++) {
  453. trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
  454. if (trigger[i])
  455. trigger_seen = true;
  456. }
  457. if (!trigger_seen)
  458. return false;
  459. memcpy(chip->irq_stat, cur_stat, NBANK(chip));
  460. for (i = 0; i < NBANK(chip); i++) {
  461. pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
  462. (cur_stat[i] & chip->irq_trig_raise[i]);
  463. pending[i] &= trigger[i];
  464. if (pending[i])
  465. pending_seen = true;
  466. }
  467. return pending_seen;
  468. }
  469. static irqreturn_t pca953x_irq_handler(int irq, void *devid)
  470. {
  471. struct pca953x_chip *chip = devid;
  472. u8 pending[MAX_BANK];
  473. u8 level;
  474. unsigned nhandled = 0;
  475. int i;
  476. if (!pca953x_irq_pending(chip, pending))
  477. return IRQ_NONE;
  478. for (i = 0; i < NBANK(chip); i++) {
  479. while (pending[i]) {
  480. level = __ffs(pending[i]);
  481. handle_nested_irq(irq_find_mapping(chip->gpio_chip.irqdomain,
  482. level + (BANK_SZ * i)));
  483. pending[i] &= ~(1 << level);
  484. nhandled++;
  485. }
  486. }
  487. return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
  488. }
  489. static int pca953x_irq_setup(struct pca953x_chip *chip,
  490. int irq_base)
  491. {
  492. struct i2c_client *client = chip->client;
  493. int ret, i;
  494. if (client->irq && irq_base != -1
  495. && (chip->driver_data & PCA_INT)) {
  496. ret = pca953x_read_regs(chip,
  497. chip->regs->input, chip->irq_stat);
  498. if (ret)
  499. return ret;
  500. /*
  501. * There is no way to know which GPIO line generated the
  502. * interrupt. We have to rely on the previous read for
  503. * this purpose.
  504. */
  505. for (i = 0; i < NBANK(chip); i++)
  506. chip->irq_stat[i] &= chip->reg_direction[i];
  507. mutex_init(&chip->irq_lock);
  508. ret = devm_request_threaded_irq(&client->dev,
  509. client->irq,
  510. NULL,
  511. pca953x_irq_handler,
  512. IRQF_TRIGGER_LOW | IRQF_ONESHOT |
  513. IRQF_SHARED,
  514. dev_name(&client->dev), chip);
  515. if (ret) {
  516. dev_err(&client->dev, "failed to request irq %d\n",
  517. client->irq);
  518. return ret;
  519. }
  520. ret = gpiochip_irqchip_add(&chip->gpio_chip,
  521. &pca953x_irq_chip,
  522. irq_base,
  523. handle_simple_irq,
  524. IRQ_TYPE_NONE);
  525. if (ret) {
  526. dev_err(&client->dev,
  527. "could not connect irqchip to gpiochip\n");
  528. return ret;
  529. }
  530. gpiochip_set_chained_irqchip(&chip->gpio_chip,
  531. &pca953x_irq_chip,
  532. client->irq, NULL);
  533. }
  534. return 0;
  535. }
  536. #else /* CONFIG_GPIO_PCA953X_IRQ */
  537. static int pca953x_irq_setup(struct pca953x_chip *chip,
  538. int irq_base)
  539. {
  540. struct i2c_client *client = chip->client;
  541. if (irq_base != -1 && (chip->driver_data & PCA_INT))
  542. dev_warn(&client->dev, "interrupt support not compiled in\n");
  543. return 0;
  544. }
  545. #endif
  546. static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
  547. {
  548. int ret;
  549. u8 val[MAX_BANK];
  550. chip->regs = &pca953x_regs;
  551. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  552. if (ret)
  553. goto out;
  554. ret = pca953x_read_regs(chip, chip->regs->direction,
  555. chip->reg_direction);
  556. if (ret)
  557. goto out;
  558. /* set platform specific polarity inversion */
  559. if (invert)
  560. memset(val, 0xFF, NBANK(chip));
  561. else
  562. memset(val, 0, NBANK(chip));
  563. ret = pca953x_write_regs(chip, PCA953X_INVERT, val);
  564. out:
  565. return ret;
  566. }
  567. static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
  568. {
  569. int ret;
  570. u8 val[MAX_BANK];
  571. chip->regs = &pca957x_regs;
  572. ret = pca953x_read_regs(chip, chip->regs->output, chip->reg_output);
  573. if (ret)
  574. goto out;
  575. ret = pca953x_read_regs(chip, chip->regs->direction,
  576. chip->reg_direction);
  577. if (ret)
  578. goto out;
  579. /* set platform specific polarity inversion */
  580. if (invert)
  581. memset(val, 0xFF, NBANK(chip));
  582. else
  583. memset(val, 0, NBANK(chip));
  584. ret = pca953x_write_regs(chip, PCA957X_INVRT, val);
  585. if (ret)
  586. goto out;
  587. /* To enable register 6, 7 to control pull up and pull down */
  588. memset(val, 0x02, NBANK(chip));
  589. ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
  590. if (ret)
  591. goto out;
  592. return 0;
  593. out:
  594. return ret;
  595. }
  596. static const struct of_device_id pca953x_dt_ids[];
  597. static int pca953x_probe(struct i2c_client *client,
  598. const struct i2c_device_id *i2c_id)
  599. {
  600. struct pca953x_platform_data *pdata;
  601. struct pca953x_chip *chip;
  602. int irq_base = 0;
  603. int ret;
  604. u32 invert = 0;
  605. struct regulator *reg;
  606. chip = devm_kzalloc(&client->dev,
  607. sizeof(struct pca953x_chip), GFP_KERNEL);
  608. if (chip == NULL)
  609. return -ENOMEM;
  610. pdata = dev_get_platdata(&client->dev);
  611. if (pdata) {
  612. irq_base = pdata->irq_base;
  613. chip->gpio_start = pdata->gpio_base;
  614. invert = pdata->invert;
  615. chip->names = pdata->names;
  616. } else {
  617. chip->gpio_start = -1;
  618. irq_base = 0;
  619. }
  620. chip->client = client;
  621. reg = devm_regulator_get(&client->dev, "vcc");
  622. if (IS_ERR(reg)) {
  623. ret = PTR_ERR(reg);
  624. if (ret != -EPROBE_DEFER)
  625. dev_err(&client->dev, "reg get err: %d\n", ret);
  626. return ret;
  627. }
  628. ret = regulator_enable(reg);
  629. if (ret) {
  630. dev_err(&client->dev, "reg en err: %d\n", ret);
  631. return ret;
  632. }
  633. chip->regulator = reg;
  634. if (i2c_id) {
  635. chip->driver_data = i2c_id->driver_data;
  636. } else {
  637. const struct acpi_device_id *acpi_id;
  638. const struct of_device_id *match;
  639. match = of_match_device(pca953x_dt_ids, &client->dev);
  640. if (match) {
  641. chip->driver_data = (int)(uintptr_t)match->data;
  642. } else {
  643. acpi_id = acpi_match_device(pca953x_acpi_ids, &client->dev);
  644. if (!acpi_id) {
  645. ret = -ENODEV;
  646. goto err_exit;
  647. }
  648. chip->driver_data = acpi_id->driver_data;
  649. }
  650. }
  651. mutex_init(&chip->i2c_lock);
  652. /*
  653. * In case we have an i2c-mux controlled by a GPIO provided by an
  654. * expander using the same driver higher on the device tree, read the
  655. * i2c adapter nesting depth and use the retrieved value as lockdep
  656. * subclass for chip->i2c_lock.
  657. *
  658. * REVISIT: This solution is not complete. It protects us from lockdep
  659. * false positives when the expander controlling the i2c-mux is on
  660. * a different level on the device tree, but not when it's on the same
  661. * level on a different branch (in which case the subclass number
  662. * would be the same).
  663. *
  664. * TODO: Once a correct solution is developed, a similar fix should be
  665. * applied to all other i2c-controlled GPIO expanders (and potentially
  666. * regmap-i2c).
  667. */
  668. lockdep_set_subclass(&chip->i2c_lock,
  669. i2c_adapter_depth(client->adapter));
  670. /* initialize cached registers from their original values.
  671. * we can't share this chip with another i2c master.
  672. */
  673. pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
  674. if (chip->gpio_chip.ngpio <= 8) {
  675. chip->write_regs = pca953x_write_regs_8;
  676. chip->read_regs = pca953x_read_regs_8;
  677. } else if (chip->gpio_chip.ngpio >= 24) {
  678. chip->write_regs = pca953x_write_regs_24;
  679. chip->read_regs = pca953x_read_regs_24;
  680. } else {
  681. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  682. chip->write_regs = pca953x_write_regs_16;
  683. else
  684. chip->write_regs = pca957x_write_regs_16;
  685. chip->read_regs = pca953x_read_regs_16;
  686. }
  687. if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
  688. ret = device_pca953x_init(chip, invert);
  689. else
  690. ret = device_pca957x_init(chip, invert);
  691. if (ret)
  692. goto err_exit;
  693. ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
  694. if (ret)
  695. goto err_exit;
  696. ret = pca953x_irq_setup(chip, irq_base);
  697. if (ret)
  698. goto err_exit;
  699. if (pdata && pdata->setup) {
  700. ret = pdata->setup(client, chip->gpio_chip.base,
  701. chip->gpio_chip.ngpio, pdata->context);
  702. if (ret < 0)
  703. dev_warn(&client->dev, "setup failed, %d\n", ret);
  704. }
  705. i2c_set_clientdata(client, chip);
  706. return 0;
  707. err_exit:
  708. regulator_disable(chip->regulator);
  709. return ret;
  710. }
  711. static int pca953x_remove(struct i2c_client *client)
  712. {
  713. struct pca953x_platform_data *pdata = dev_get_platdata(&client->dev);
  714. struct pca953x_chip *chip = i2c_get_clientdata(client);
  715. int ret;
  716. if (pdata && pdata->teardown) {
  717. ret = pdata->teardown(client, chip->gpio_chip.base,
  718. chip->gpio_chip.ngpio, pdata->context);
  719. if (ret < 0)
  720. dev_err(&client->dev, "%s failed, %d\n",
  721. "teardown", ret);
  722. } else {
  723. ret = 0;
  724. }
  725. regulator_disable(chip->regulator);
  726. return ret;
  727. }
  728. /* convenience to stop overlong match-table lines */
  729. #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int)
  730. #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int)
  731. static const struct of_device_id pca953x_dt_ids[] = {
  732. { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
  733. { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
  734. { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
  735. { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
  736. { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
  737. { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
  738. { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
  739. { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), },
  740. { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
  741. { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), },
  742. { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), },
  743. { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), },
  744. { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
  745. { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
  746. { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), },
  747. { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
  748. { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
  749. { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), },
  750. { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), },
  751. { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), },
  752. { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), },
  753. { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
  754. { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
  755. { .compatible = "onsemi,pca9654", .data = OF_953X( 8, PCA_INT), },
  756. { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), },
  757. { }
  758. };
  759. MODULE_DEVICE_TABLE(of, pca953x_dt_ids);
  760. static struct i2c_driver pca953x_driver = {
  761. .driver = {
  762. .name = "pca953x",
  763. .of_match_table = pca953x_dt_ids,
  764. .acpi_match_table = ACPI_PTR(pca953x_acpi_ids),
  765. },
  766. .probe = pca953x_probe,
  767. .remove = pca953x_remove,
  768. .id_table = pca953x_id,
  769. };
  770. static int __init pca953x_init(void)
  771. {
  772. return i2c_add_driver(&pca953x_driver);
  773. }
  774. /* register after i2c postcore initcall and before
  775. * subsys initcalls that may rely on these GPIOs
  776. */
  777. subsys_initcall(pca953x_init);
  778. static void __exit pca953x_exit(void)
  779. {
  780. i2c_del_driver(&pca953x_driver);
  781. }
  782. module_exit(pca953x_exit);
  783. MODULE_AUTHOR("eric miao <eric.miao@marvell.com>");
  784. MODULE_DESCRIPTION("GPIO expander driver for PCA953x");
  785. MODULE_LICENSE("GPL");