gpio-msic.c 8.3 KB

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  1. /*
  2. * Intel Medfield MSIC GPIO driver>
  3. * Copyright (c) 2011, Intel Corporation.
  4. *
  5. * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
  6. * Based on intel_pmic_gpio.c
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  20. *
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/slab.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/init.h>
  26. #include <linux/gpio.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/mfd/intel_msic.h>
  29. /* the offset for the mapping of global gpio pin to irq */
  30. #define MSIC_GPIO_IRQ_OFFSET 0x100
  31. #define MSIC_GPIO_DIR_IN 0
  32. #define MSIC_GPIO_DIR_OUT BIT(5)
  33. #define MSIC_GPIO_TRIG_FALL BIT(1)
  34. #define MSIC_GPIO_TRIG_RISE BIT(2)
  35. /* masks for msic gpio output GPIOxxxxCTLO registers */
  36. #define MSIC_GPIO_DIR_MASK BIT(5)
  37. #define MSIC_GPIO_DRV_MASK BIT(4)
  38. #define MSIC_GPIO_REN_MASK BIT(3)
  39. #define MSIC_GPIO_RVAL_MASK (BIT(2) | BIT(1))
  40. #define MSIC_GPIO_DOUT_MASK BIT(0)
  41. /* masks for msic gpio input GPIOxxxxCTLI registers */
  42. #define MSIC_GPIO_GLBYP_MASK BIT(5)
  43. #define MSIC_GPIO_DBNC_MASK (BIT(4) | BIT(3))
  44. #define MSIC_GPIO_INTCNT_MASK (BIT(2) | BIT(1))
  45. #define MSIC_GPIO_DIN_MASK BIT(0)
  46. #define MSIC_NUM_GPIO 24
  47. struct msic_gpio {
  48. struct platform_device *pdev;
  49. struct mutex buslock;
  50. struct gpio_chip chip;
  51. int irq;
  52. unsigned irq_base;
  53. unsigned long trig_change_mask;
  54. unsigned trig_type;
  55. };
  56. /*
  57. * MSIC has 24 gpios, 16 low voltage (1.2-1.8v) and 8 high voltage (3v).
  58. * Both the high and low voltage gpios are divided in two banks.
  59. * GPIOs are numbered with GPIO0LV0 as gpio_base in the following order:
  60. * GPIO0LV0..GPIO0LV7: low voltage, bank 0, gpio_base
  61. * GPIO1LV0..GPIO1LV7: low voltage, bank 1, gpio_base + 8
  62. * GPIO0HV0..GPIO0HV3: high voltage, bank 0, gpio_base + 16
  63. * GPIO1HV0..GPIO1HV3: high voltage, bank 1, gpio_base + 20
  64. */
  65. static int msic_gpio_to_ireg(unsigned offset)
  66. {
  67. if (offset >= MSIC_NUM_GPIO)
  68. return -EINVAL;
  69. if (offset < 8)
  70. return INTEL_MSIC_GPIO0LV0CTLI - offset;
  71. if (offset < 16)
  72. return INTEL_MSIC_GPIO1LV0CTLI - offset + 8;
  73. if (offset < 20)
  74. return INTEL_MSIC_GPIO0HV0CTLI - offset + 16;
  75. return INTEL_MSIC_GPIO1HV0CTLI - offset + 20;
  76. }
  77. static int msic_gpio_to_oreg(unsigned offset)
  78. {
  79. if (offset >= MSIC_NUM_GPIO)
  80. return -EINVAL;
  81. if (offset < 8)
  82. return INTEL_MSIC_GPIO0LV0CTLO - offset;
  83. if (offset < 16)
  84. return INTEL_MSIC_GPIO1LV0CTLO - offset + 8;
  85. if (offset < 20)
  86. return INTEL_MSIC_GPIO0HV0CTLO - offset + 16;
  87. return INTEL_MSIC_GPIO1HV0CTLO - offset + 20;
  88. }
  89. static int msic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  90. {
  91. int reg;
  92. reg = msic_gpio_to_oreg(offset);
  93. if (reg < 0)
  94. return reg;
  95. return intel_msic_reg_update(reg, MSIC_GPIO_DIR_IN, MSIC_GPIO_DIR_MASK);
  96. }
  97. static int msic_gpio_direction_output(struct gpio_chip *chip,
  98. unsigned offset, int value)
  99. {
  100. int reg;
  101. unsigned mask;
  102. value = (!!value) | MSIC_GPIO_DIR_OUT;
  103. mask = MSIC_GPIO_DIR_MASK | MSIC_GPIO_DOUT_MASK;
  104. reg = msic_gpio_to_oreg(offset);
  105. if (reg < 0)
  106. return reg;
  107. return intel_msic_reg_update(reg, value, mask);
  108. }
  109. static int msic_gpio_get(struct gpio_chip *chip, unsigned offset)
  110. {
  111. u8 r;
  112. int ret;
  113. int reg;
  114. reg = msic_gpio_to_ireg(offset);
  115. if (reg < 0)
  116. return reg;
  117. ret = intel_msic_reg_read(reg, &r);
  118. if (ret < 0)
  119. return ret;
  120. return !!(r & MSIC_GPIO_DIN_MASK);
  121. }
  122. static void msic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  123. {
  124. int reg;
  125. reg = msic_gpio_to_oreg(offset);
  126. if (reg < 0)
  127. return;
  128. intel_msic_reg_update(reg, !!value , MSIC_GPIO_DOUT_MASK);
  129. }
  130. /*
  131. * This is called from genirq with mg->buslock locked and
  132. * irq_desc->lock held. We can not access the scu bus here, so we
  133. * store the change and update in the bus_sync_unlock() function below
  134. */
  135. static int msic_irq_type(struct irq_data *data, unsigned type)
  136. {
  137. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  138. u32 gpio = data->irq - mg->irq_base;
  139. if (gpio >= mg->chip.ngpio)
  140. return -EINVAL;
  141. /* mark for which gpio the trigger changed, protected by buslock */
  142. mg->trig_change_mask |= (1 << gpio);
  143. mg->trig_type = type;
  144. return 0;
  145. }
  146. static int msic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  147. {
  148. struct msic_gpio *mg = gpiochip_get_data(chip);
  149. return mg->irq_base + offset;
  150. }
  151. static void msic_bus_lock(struct irq_data *data)
  152. {
  153. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  154. mutex_lock(&mg->buslock);
  155. }
  156. static void msic_bus_sync_unlock(struct irq_data *data)
  157. {
  158. struct msic_gpio *mg = irq_data_get_irq_chip_data(data);
  159. int offset;
  160. int reg;
  161. u8 trig = 0;
  162. /* We can only get one change at a time as the buslock covers the
  163. entire transaction. The irq_desc->lock is dropped before we are
  164. called but that is fine */
  165. if (mg->trig_change_mask) {
  166. offset = __ffs(mg->trig_change_mask);
  167. reg = msic_gpio_to_ireg(offset);
  168. if (reg < 0)
  169. goto out;
  170. if (mg->trig_type & IRQ_TYPE_EDGE_RISING)
  171. trig |= MSIC_GPIO_TRIG_RISE;
  172. if (mg->trig_type & IRQ_TYPE_EDGE_FALLING)
  173. trig |= MSIC_GPIO_TRIG_FALL;
  174. intel_msic_reg_update(reg, trig, MSIC_GPIO_INTCNT_MASK);
  175. mg->trig_change_mask = 0;
  176. }
  177. out:
  178. mutex_unlock(&mg->buslock);
  179. }
  180. /* Firmware does all the masking and unmasking for us, no masking here. */
  181. static void msic_irq_unmask(struct irq_data *data) { }
  182. static void msic_irq_mask(struct irq_data *data) { }
  183. static struct irq_chip msic_irqchip = {
  184. .name = "MSIC-GPIO",
  185. .irq_mask = msic_irq_mask,
  186. .irq_unmask = msic_irq_unmask,
  187. .irq_set_type = msic_irq_type,
  188. .irq_bus_lock = msic_bus_lock,
  189. .irq_bus_sync_unlock = msic_bus_sync_unlock,
  190. };
  191. static void msic_gpio_irq_handler(struct irq_desc *desc)
  192. {
  193. struct irq_data *data = irq_desc_get_irq_data(desc);
  194. struct msic_gpio *mg = irq_data_get_irq_handler_data(data);
  195. struct irq_chip *chip = irq_data_get_irq_chip(data);
  196. struct intel_msic *msic = pdev_to_intel_msic(mg->pdev);
  197. int i;
  198. int bitnr;
  199. u8 pin;
  200. unsigned long pending = 0;
  201. for (i = 0; i < (mg->chip.ngpio / BITS_PER_BYTE); i++) {
  202. intel_msic_irq_read(msic, INTEL_MSIC_GPIO0LVIRQ + i, &pin);
  203. pending = pin;
  204. if (pending) {
  205. for_each_set_bit(bitnr, &pending, BITS_PER_BYTE)
  206. generic_handle_irq(mg->irq_base +
  207. (i * BITS_PER_BYTE) + bitnr);
  208. }
  209. }
  210. chip->irq_eoi(data);
  211. }
  212. static int platform_msic_gpio_probe(struct platform_device *pdev)
  213. {
  214. struct device *dev = &pdev->dev;
  215. struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev);
  216. struct msic_gpio *mg;
  217. int irq = platform_get_irq(pdev, 0);
  218. int retval;
  219. int i;
  220. if (irq < 0) {
  221. dev_err(dev, "no IRQ line\n");
  222. return -EINVAL;
  223. }
  224. if (!pdata || !pdata->gpio_base) {
  225. dev_err(dev, "incorrect or missing platform data\n");
  226. return -EINVAL;
  227. }
  228. mg = kzalloc(sizeof(*mg), GFP_KERNEL);
  229. if (!mg)
  230. return -ENOMEM;
  231. dev_set_drvdata(dev, mg);
  232. mg->pdev = pdev;
  233. mg->irq = irq;
  234. mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET;
  235. mg->chip.label = "msic_gpio";
  236. mg->chip.direction_input = msic_gpio_direction_input;
  237. mg->chip.direction_output = msic_gpio_direction_output;
  238. mg->chip.get = msic_gpio_get;
  239. mg->chip.set = msic_gpio_set;
  240. mg->chip.to_irq = msic_gpio_to_irq;
  241. mg->chip.base = pdata->gpio_base;
  242. mg->chip.ngpio = MSIC_NUM_GPIO;
  243. mg->chip.can_sleep = true;
  244. mg->chip.parent = dev;
  245. mutex_init(&mg->buslock);
  246. retval = gpiochip_add_data(&mg->chip, mg);
  247. if (retval) {
  248. dev_err(dev, "Adding MSIC gpio chip failed\n");
  249. goto err;
  250. }
  251. for (i = 0; i < mg->chip.ngpio; i++) {
  252. irq_set_chip_data(i + mg->irq_base, mg);
  253. irq_set_chip_and_handler(i + mg->irq_base,
  254. &msic_irqchip,
  255. handle_simple_irq);
  256. }
  257. irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg);
  258. return 0;
  259. err:
  260. kfree(mg);
  261. return retval;
  262. }
  263. static struct platform_driver platform_msic_gpio_driver = {
  264. .driver = {
  265. .name = "msic_gpio",
  266. },
  267. .probe = platform_msic_gpio_probe,
  268. };
  269. static int __init platform_msic_gpio_init(void)
  270. {
  271. return platform_driver_register(&platform_msic_gpio_driver);
  272. }
  273. subsys_initcall(platform_msic_gpio_init);