gpio-mmio.c 17 KB

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  1. /*
  2. * Generic driver for memory-mapped GPIO controllers.
  3. *
  4. * Copyright 2008 MontaVista Software, Inc.
  5. * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
  13. * ...`` ```````..
  14. * ..The simplest form of a GPIO controller that the driver supports is``
  15. * `.just a single "data" register, where GPIO state can be read and/or `
  16. * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
  17. * `````````
  18. ___
  19. _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
  20. __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
  21. o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
  22. `....trivial..'~`.```.```
  23. * ```````
  24. * .```````~~~~`..`.``.``.
  25. * . The driver supports `... ,..```.`~~~```````````````....````.``,,
  26. * . big-endian notation, just`. .. A bit more sophisticated controllers ,
  27. * . register the device with -be`. .with a pair of set/clear-bit registers ,
  28. * `.. suffix. ```~~`````....`.` . affecting the data register and the .`
  29. * ``.`.``...``` ```.. output pins are also supported.`
  30. * ^^ `````.`````````.,``~``~``~~``````
  31. * . ^^
  32. * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
  33. * .. The expectation is that in at least some cases . ,-~~~-,
  34. * .this will be used with roll-your-own ASIC/FPGA .` \ /
  35. * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
  36. * ..````````......``````````` \o_
  37. * |
  38. * ^^ / \
  39. *
  40. * ...`````~~`.....``.`..........``````.`.``.```........``.
  41. * ` 8, 16, 32 and 64 bits registers are supported, and``.
  42. * . the number of GPIOs is determined by the width of ~
  43. * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
  44. * `.......````.```
  45. */
  46. #include <linux/init.h>
  47. #include <linux/err.h>
  48. #include <linux/bug.h>
  49. #include <linux/kernel.h>
  50. #include <linux/module.h>
  51. #include <linux/spinlock.h>
  52. #include <linux/compiler.h>
  53. #include <linux/types.h>
  54. #include <linux/errno.h>
  55. #include <linux/log2.h>
  56. #include <linux/ioport.h>
  57. #include <linux/io.h>
  58. #include <linux/gpio/driver.h>
  59. #include <linux/slab.h>
  60. #include <linux/bitops.h>
  61. #include <linux/platform_device.h>
  62. #include <linux/mod_devicetable.h>
  63. #include <linux/of.h>
  64. #include <linux/of_device.h>
  65. static void bgpio_write8(void __iomem *reg, unsigned long data)
  66. {
  67. writeb(data, reg);
  68. }
  69. static unsigned long bgpio_read8(void __iomem *reg)
  70. {
  71. return readb(reg);
  72. }
  73. static void bgpio_write16(void __iomem *reg, unsigned long data)
  74. {
  75. writew(data, reg);
  76. }
  77. static unsigned long bgpio_read16(void __iomem *reg)
  78. {
  79. return readw(reg);
  80. }
  81. static void bgpio_write32(void __iomem *reg, unsigned long data)
  82. {
  83. writel(data, reg);
  84. }
  85. static unsigned long bgpio_read32(void __iomem *reg)
  86. {
  87. return readl(reg);
  88. }
  89. #if BITS_PER_LONG >= 64
  90. static void bgpio_write64(void __iomem *reg, unsigned long data)
  91. {
  92. writeq(data, reg);
  93. }
  94. static unsigned long bgpio_read64(void __iomem *reg)
  95. {
  96. return readq(reg);
  97. }
  98. #endif /* BITS_PER_LONG >= 64 */
  99. static void bgpio_write16be(void __iomem *reg, unsigned long data)
  100. {
  101. iowrite16be(data, reg);
  102. }
  103. static unsigned long bgpio_read16be(void __iomem *reg)
  104. {
  105. return ioread16be(reg);
  106. }
  107. static void bgpio_write32be(void __iomem *reg, unsigned long data)
  108. {
  109. iowrite32be(data, reg);
  110. }
  111. static unsigned long bgpio_read32be(void __iomem *reg)
  112. {
  113. return ioread32be(reg);
  114. }
  115. static unsigned long bgpio_pin2mask(struct gpio_chip *gc, unsigned int pin)
  116. {
  117. return BIT(pin);
  118. }
  119. static unsigned long bgpio_pin2mask_be(struct gpio_chip *gc,
  120. unsigned int pin)
  121. {
  122. return BIT(gc->bgpio_bits - 1 - pin);
  123. }
  124. static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
  125. {
  126. unsigned long pinmask = gc->pin2mask(gc, gpio);
  127. if (gc->bgpio_dir & pinmask)
  128. return !!(gc->read_reg(gc->reg_set) & pinmask);
  129. else
  130. return !!(gc->read_reg(gc->reg_dat) & pinmask);
  131. }
  132. static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
  133. {
  134. return !!(gc->read_reg(gc->reg_dat) & gc->pin2mask(gc, gpio));
  135. }
  136. static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
  137. {
  138. }
  139. static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  140. {
  141. unsigned long mask = gc->pin2mask(gc, gpio);
  142. unsigned long flags;
  143. spin_lock_irqsave(&gc->bgpio_lock, flags);
  144. if (val)
  145. gc->bgpio_data |= mask;
  146. else
  147. gc->bgpio_data &= ~mask;
  148. gc->write_reg(gc->reg_dat, gc->bgpio_data);
  149. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  150. }
  151. static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
  152. int val)
  153. {
  154. unsigned long mask = gc->pin2mask(gc, gpio);
  155. if (val)
  156. gc->write_reg(gc->reg_set, mask);
  157. else
  158. gc->write_reg(gc->reg_clr, mask);
  159. }
  160. static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
  161. {
  162. unsigned long mask = gc->pin2mask(gc, gpio);
  163. unsigned long flags;
  164. spin_lock_irqsave(&gc->bgpio_lock, flags);
  165. if (val)
  166. gc->bgpio_data |= mask;
  167. else
  168. gc->bgpio_data &= ~mask;
  169. gc->write_reg(gc->reg_set, gc->bgpio_data);
  170. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  171. }
  172. static void bgpio_multiple_get_masks(struct gpio_chip *gc,
  173. unsigned long *mask, unsigned long *bits,
  174. unsigned long *set_mask,
  175. unsigned long *clear_mask)
  176. {
  177. int i;
  178. *set_mask = 0;
  179. *clear_mask = 0;
  180. for (i = 0; i < gc->bgpio_bits; i++) {
  181. if (*mask == 0)
  182. break;
  183. if (__test_and_clear_bit(i, mask)) {
  184. if (test_bit(i, bits))
  185. *set_mask |= gc->pin2mask(gc, i);
  186. else
  187. *clear_mask |= gc->pin2mask(gc, i);
  188. }
  189. }
  190. }
  191. static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
  192. unsigned long *mask,
  193. unsigned long *bits,
  194. void __iomem *reg)
  195. {
  196. unsigned long flags;
  197. unsigned long set_mask, clear_mask;
  198. spin_lock_irqsave(&gc->bgpio_lock, flags);
  199. bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
  200. gc->bgpio_data |= set_mask;
  201. gc->bgpio_data &= ~clear_mask;
  202. gc->write_reg(reg, gc->bgpio_data);
  203. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  204. }
  205. static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
  206. unsigned long *bits)
  207. {
  208. bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
  209. }
  210. static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
  211. unsigned long *bits)
  212. {
  213. bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
  214. }
  215. static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
  216. unsigned long *mask,
  217. unsigned long *bits)
  218. {
  219. unsigned long set_mask, clear_mask;
  220. bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
  221. if (set_mask)
  222. gc->write_reg(gc->reg_set, set_mask);
  223. if (clear_mask)
  224. gc->write_reg(gc->reg_clr, clear_mask);
  225. }
  226. static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
  227. {
  228. return 0;
  229. }
  230. static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
  231. int val)
  232. {
  233. return -EINVAL;
  234. }
  235. static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
  236. int val)
  237. {
  238. gc->set(gc, gpio, val);
  239. return 0;
  240. }
  241. static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
  242. {
  243. unsigned long flags;
  244. spin_lock_irqsave(&gc->bgpio_lock, flags);
  245. gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
  246. gc->write_reg(gc->reg_dir, gc->bgpio_dir);
  247. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  248. return 0;
  249. }
  250. static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
  251. {
  252. /* Return 0 if output, 1 of input */
  253. return !(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
  254. }
  255. static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
  256. {
  257. unsigned long flags;
  258. gc->set(gc, gpio, val);
  259. spin_lock_irqsave(&gc->bgpio_lock, flags);
  260. gc->bgpio_dir |= gc->pin2mask(gc, gpio);
  261. gc->write_reg(gc->reg_dir, gc->bgpio_dir);
  262. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  263. return 0;
  264. }
  265. static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
  266. {
  267. unsigned long flags;
  268. spin_lock_irqsave(&gc->bgpio_lock, flags);
  269. gc->bgpio_dir |= gc->pin2mask(gc, gpio);
  270. gc->write_reg(gc->reg_dir, gc->bgpio_dir);
  271. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  272. return 0;
  273. }
  274. static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
  275. {
  276. unsigned long flags;
  277. gc->set(gc, gpio, val);
  278. spin_lock_irqsave(&gc->bgpio_lock, flags);
  279. gc->bgpio_dir &= ~gc->pin2mask(gc, gpio);
  280. gc->write_reg(gc->reg_dir, gc->bgpio_dir);
  281. spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  282. return 0;
  283. }
  284. static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio)
  285. {
  286. /* Return 0 if output, 1 if input */
  287. return !!(gc->read_reg(gc->reg_dir) & gc->pin2mask(gc, gpio));
  288. }
  289. static int bgpio_setup_accessors(struct device *dev,
  290. struct gpio_chip *gc,
  291. bool bit_be,
  292. bool byte_be)
  293. {
  294. switch (gc->bgpio_bits) {
  295. case 8:
  296. gc->read_reg = bgpio_read8;
  297. gc->write_reg = bgpio_write8;
  298. break;
  299. case 16:
  300. if (byte_be) {
  301. gc->read_reg = bgpio_read16be;
  302. gc->write_reg = bgpio_write16be;
  303. } else {
  304. gc->read_reg = bgpio_read16;
  305. gc->write_reg = bgpio_write16;
  306. }
  307. break;
  308. case 32:
  309. if (byte_be) {
  310. gc->read_reg = bgpio_read32be;
  311. gc->write_reg = bgpio_write32be;
  312. } else {
  313. gc->read_reg = bgpio_read32;
  314. gc->write_reg = bgpio_write32;
  315. }
  316. break;
  317. #if BITS_PER_LONG >= 64
  318. case 64:
  319. if (byte_be) {
  320. dev_err(dev,
  321. "64 bit big endian byte order unsupported\n");
  322. return -EINVAL;
  323. } else {
  324. gc->read_reg = bgpio_read64;
  325. gc->write_reg = bgpio_write64;
  326. }
  327. break;
  328. #endif /* BITS_PER_LONG >= 64 */
  329. default:
  330. dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
  331. return -EINVAL;
  332. }
  333. gc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
  334. return 0;
  335. }
  336. /*
  337. * Create the device and allocate the resources. For setting GPIO's there are
  338. * three supported configurations:
  339. *
  340. * - single input/output register resource (named "dat").
  341. * - set/clear pair (named "set" and "clr").
  342. * - single output register resource and single input resource ("set" and
  343. * dat").
  344. *
  345. * For the single output register, this drives a 1 by setting a bit and a zero
  346. * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
  347. * in the set register and clears it by setting a bit in the clear register.
  348. * The configuration is detected by which resources are present.
  349. *
  350. * For setting the GPIO direction, there are three supported configurations:
  351. *
  352. * - simple bidirection GPIO that requires no configuration.
  353. * - an output direction register (named "dirout") where a 1 bit
  354. * indicates the GPIO is an output.
  355. * - an input direction register (named "dirin") where a 1 bit indicates
  356. * the GPIO is an input.
  357. */
  358. static int bgpio_setup_io(struct gpio_chip *gc,
  359. void __iomem *dat,
  360. void __iomem *set,
  361. void __iomem *clr,
  362. unsigned long flags)
  363. {
  364. gc->reg_dat = dat;
  365. if (!gc->reg_dat)
  366. return -EINVAL;
  367. if (set && clr) {
  368. gc->reg_set = set;
  369. gc->reg_clr = clr;
  370. gc->set = bgpio_set_with_clear;
  371. gc->set_multiple = bgpio_set_multiple_with_clear;
  372. } else if (set && !clr) {
  373. gc->reg_set = set;
  374. gc->set = bgpio_set_set;
  375. gc->set_multiple = bgpio_set_multiple_set;
  376. } else if (flags & BGPIOF_NO_OUTPUT) {
  377. gc->set = bgpio_set_none;
  378. gc->set_multiple = NULL;
  379. } else {
  380. gc->set = bgpio_set;
  381. gc->set_multiple = bgpio_set_multiple;
  382. }
  383. if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
  384. (flags & BGPIOF_READ_OUTPUT_REG_SET))
  385. gc->get = bgpio_get_set;
  386. else
  387. gc->get = bgpio_get;
  388. return 0;
  389. }
  390. static int bgpio_setup_direction(struct gpio_chip *gc,
  391. void __iomem *dirout,
  392. void __iomem *dirin,
  393. unsigned long flags)
  394. {
  395. if (dirout && dirin) {
  396. return -EINVAL;
  397. } else if (dirout) {
  398. gc->reg_dir = dirout;
  399. gc->direction_output = bgpio_dir_out;
  400. gc->direction_input = bgpio_dir_in;
  401. gc->get_direction = bgpio_get_dir;
  402. } else if (dirin) {
  403. gc->reg_dir = dirin;
  404. gc->direction_output = bgpio_dir_out_inv;
  405. gc->direction_input = bgpio_dir_in_inv;
  406. gc->get_direction = bgpio_get_dir_inv;
  407. } else {
  408. if (flags & BGPIOF_NO_OUTPUT)
  409. gc->direction_output = bgpio_dir_out_err;
  410. else
  411. gc->direction_output = bgpio_simple_dir_out;
  412. gc->direction_input = bgpio_simple_dir_in;
  413. }
  414. return 0;
  415. }
  416. static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
  417. {
  418. if (gpio_pin < chip->ngpio)
  419. return 0;
  420. return -EINVAL;
  421. }
  422. int bgpio_init(struct gpio_chip *gc, struct device *dev,
  423. unsigned long sz, void __iomem *dat, void __iomem *set,
  424. void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
  425. unsigned long flags)
  426. {
  427. int ret;
  428. if (!is_power_of_2(sz))
  429. return -EINVAL;
  430. gc->bgpio_bits = sz * 8;
  431. if (gc->bgpio_bits > BITS_PER_LONG)
  432. return -EINVAL;
  433. spin_lock_init(&gc->bgpio_lock);
  434. gc->parent = dev;
  435. gc->label = dev_name(dev);
  436. gc->base = -1;
  437. gc->ngpio = gc->bgpio_bits;
  438. gc->request = bgpio_request;
  439. ret = bgpio_setup_io(gc, dat, set, clr, flags);
  440. if (ret)
  441. return ret;
  442. ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN,
  443. flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
  444. if (ret)
  445. return ret;
  446. ret = bgpio_setup_direction(gc, dirout, dirin, flags);
  447. if (ret)
  448. return ret;
  449. gc->bgpio_data = gc->read_reg(gc->reg_dat);
  450. if (gc->set == bgpio_set_set &&
  451. !(flags & BGPIOF_UNREADABLE_REG_SET))
  452. gc->bgpio_data = gc->read_reg(gc->reg_set);
  453. if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
  454. gc->bgpio_dir = gc->read_reg(gc->reg_dir);
  455. return ret;
  456. }
  457. EXPORT_SYMBOL_GPL(bgpio_init);
  458. #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
  459. static void __iomem *bgpio_map(struct platform_device *pdev,
  460. const char *name,
  461. resource_size_t sane_sz)
  462. {
  463. struct resource *r;
  464. resource_size_t sz;
  465. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  466. if (!r)
  467. return NULL;
  468. sz = resource_size(r);
  469. if (sz != sane_sz)
  470. return IOMEM_ERR_PTR(-EINVAL);
  471. return devm_ioremap_resource(&pdev->dev, r);
  472. }
  473. #ifdef CONFIG_OF
  474. static const struct of_device_id bgpio_of_match[] = {
  475. { .compatible = "brcm,bcm6345-gpio" },
  476. { .compatible = "wd,mbl-gpio" },
  477. { }
  478. };
  479. MODULE_DEVICE_TABLE(of, bgpio_of_match);
  480. static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
  481. unsigned long *flags)
  482. {
  483. struct bgpio_pdata *pdata;
  484. if (!of_match_device(bgpio_of_match, &pdev->dev))
  485. return NULL;
  486. pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
  487. GFP_KERNEL);
  488. if (!pdata)
  489. return ERR_PTR(-ENOMEM);
  490. pdata->base = -1;
  491. if (of_device_is_big_endian(pdev->dev.of_node))
  492. *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
  493. if (of_property_read_bool(pdev->dev.of_node, "no-output"))
  494. *flags |= BGPIOF_NO_OUTPUT;
  495. return pdata;
  496. }
  497. #else
  498. static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
  499. unsigned long *flags)
  500. {
  501. return NULL;
  502. }
  503. #endif /* CONFIG_OF */
  504. static int bgpio_pdev_probe(struct platform_device *pdev)
  505. {
  506. struct device *dev = &pdev->dev;
  507. struct resource *r;
  508. void __iomem *dat;
  509. void __iomem *set;
  510. void __iomem *clr;
  511. void __iomem *dirout;
  512. void __iomem *dirin;
  513. unsigned long sz;
  514. unsigned long flags = 0;
  515. int err;
  516. struct gpio_chip *gc;
  517. struct bgpio_pdata *pdata;
  518. pdata = bgpio_parse_dt(pdev, &flags);
  519. if (IS_ERR(pdata))
  520. return PTR_ERR(pdata);
  521. if (!pdata) {
  522. pdata = dev_get_platdata(dev);
  523. flags = pdev->id_entry->driver_data;
  524. }
  525. r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
  526. if (!r)
  527. return -EINVAL;
  528. sz = resource_size(r);
  529. dat = bgpio_map(pdev, "dat", sz);
  530. if (IS_ERR(dat))
  531. return PTR_ERR(dat);
  532. set = bgpio_map(pdev, "set", sz);
  533. if (IS_ERR(set))
  534. return PTR_ERR(set);
  535. clr = bgpio_map(pdev, "clr", sz);
  536. if (IS_ERR(clr))
  537. return PTR_ERR(clr);
  538. dirout = bgpio_map(pdev, "dirout", sz);
  539. if (IS_ERR(dirout))
  540. return PTR_ERR(dirout);
  541. dirin = bgpio_map(pdev, "dirin", sz);
  542. if (IS_ERR(dirin))
  543. return PTR_ERR(dirin);
  544. gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
  545. if (!gc)
  546. return -ENOMEM;
  547. err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
  548. if (err)
  549. return err;
  550. if (pdata) {
  551. if (pdata->label)
  552. gc->label = pdata->label;
  553. gc->base = pdata->base;
  554. if (pdata->ngpio > 0)
  555. gc->ngpio = pdata->ngpio;
  556. }
  557. platform_set_drvdata(pdev, gc);
  558. return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
  559. }
  560. static const struct platform_device_id bgpio_id_table[] = {
  561. {
  562. .name = "basic-mmio-gpio",
  563. .driver_data = 0,
  564. }, {
  565. .name = "basic-mmio-gpio-be",
  566. .driver_data = BGPIOF_BIG_ENDIAN,
  567. },
  568. { }
  569. };
  570. MODULE_DEVICE_TABLE(platform, bgpio_id_table);
  571. static struct platform_driver bgpio_driver = {
  572. .driver = {
  573. .name = "basic-mmio-gpio",
  574. .of_match_table = of_match_ptr(bgpio_of_match),
  575. },
  576. .id_table = bgpio_id_table,
  577. .probe = bgpio_pdev_probe,
  578. };
  579. module_platform_driver(bgpio_driver);
  580. #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
  581. MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
  582. MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
  583. MODULE_LICENSE("GPL");