gpio-ml-ioh.c 15 KB

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  1. /*
  2. * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License as published by
  6. * the Free Software Foundation; version 2 of the License.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/slab.h>
  20. #include <linux/pci.h>
  21. #include <linux/gpio.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/irq.h>
  24. #define IOH_EDGE_FALLING 0
  25. #define IOH_EDGE_RISING BIT(0)
  26. #define IOH_LEVEL_L BIT(1)
  27. #define IOH_LEVEL_H (BIT(0) | BIT(1))
  28. #define IOH_EDGE_BOTH BIT(2)
  29. #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
  30. #define IOH_IRQ_BASE 0
  31. #define PCI_VENDOR_ID_ROHM 0x10DB
  32. struct ioh_reg_comn {
  33. u32 ien;
  34. u32 istatus;
  35. u32 idisp;
  36. u32 iclr;
  37. u32 imask;
  38. u32 imaskclr;
  39. u32 po;
  40. u32 pi;
  41. u32 pm;
  42. u32 im_0;
  43. u32 im_1;
  44. u32 reserved;
  45. };
  46. struct ioh_regs {
  47. struct ioh_reg_comn regs[8];
  48. u32 reserve1[16];
  49. u32 ioh_sel_reg[4];
  50. u32 reserve2[11];
  51. u32 srst;
  52. };
  53. /**
  54. * struct ioh_gpio_reg_data - The register store data.
  55. * @ien_reg To store contents of interrupt enable register.
  56. * @imask_reg: To store contents of interrupt mask regist
  57. * @po_reg: To store contents of PO register.
  58. * @pm_reg: To store contents of PM register.
  59. * @im0_reg: To store contents of interrupt mode regist0
  60. * @im1_reg: To store contents of interrupt mode regist1
  61. * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
  62. */
  63. struct ioh_gpio_reg_data {
  64. u32 ien_reg;
  65. u32 imask_reg;
  66. u32 po_reg;
  67. u32 pm_reg;
  68. u32 im0_reg;
  69. u32 im1_reg;
  70. u32 use_sel_reg;
  71. };
  72. /**
  73. * struct ioh_gpio - GPIO private data structure.
  74. * @base: PCI base address of Memory mapped I/O register.
  75. * @reg: Memory mapped IOH GPIO register list.
  76. * @dev: Pointer to device structure.
  77. * @gpio: Data for GPIO infrastructure.
  78. * @ioh_gpio_reg: Memory mapped Register data is saved here
  79. * when suspend.
  80. * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
  81. * @ch: Indicate GPIO channel
  82. * @irq_base: Save base of IRQ number for interrupt
  83. * @spinlock: Used for register access protection
  84. */
  85. struct ioh_gpio {
  86. void __iomem *base;
  87. struct ioh_regs __iomem *reg;
  88. struct device *dev;
  89. struct gpio_chip gpio;
  90. struct ioh_gpio_reg_data ioh_gpio_reg;
  91. u32 gpio_use_sel;
  92. int ch;
  93. int irq_base;
  94. spinlock_t spinlock;
  95. };
  96. static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
  97. static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
  98. {
  99. u32 reg_val;
  100. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  101. unsigned long flags;
  102. spin_lock_irqsave(&chip->spinlock, flags);
  103. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  104. if (val)
  105. reg_val |= (1 << nr);
  106. else
  107. reg_val &= ~(1 << nr);
  108. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  109. spin_unlock_irqrestore(&chip->spinlock, flags);
  110. }
  111. static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
  112. {
  113. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  114. return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
  115. }
  116. static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
  117. int val)
  118. {
  119. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  120. u32 pm;
  121. u32 reg_val;
  122. unsigned long flags;
  123. spin_lock_irqsave(&chip->spinlock, flags);
  124. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  125. ((1 << num_ports[chip->ch]) - 1);
  126. pm |= (1 << nr);
  127. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  128. reg_val = ioread32(&chip->reg->regs[chip->ch].po);
  129. if (val)
  130. reg_val |= (1 << nr);
  131. else
  132. reg_val &= ~(1 << nr);
  133. iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
  134. spin_unlock_irqrestore(&chip->spinlock, flags);
  135. return 0;
  136. }
  137. static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
  138. {
  139. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  140. u32 pm;
  141. unsigned long flags;
  142. spin_lock_irqsave(&chip->spinlock, flags);
  143. pm = ioread32(&chip->reg->regs[chip->ch].pm) &
  144. ((1 << num_ports[chip->ch]) - 1);
  145. pm &= ~(1 << nr);
  146. iowrite32(pm, &chip->reg->regs[chip->ch].pm);
  147. spin_unlock_irqrestore(&chip->spinlock, flags);
  148. return 0;
  149. }
  150. #ifdef CONFIG_PM
  151. /*
  152. * Save register configuration and disable interrupts.
  153. */
  154. static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
  155. {
  156. int i;
  157. for (i = 0; i < 8; i ++, chip++) {
  158. chip->ioh_gpio_reg.po_reg =
  159. ioread32(&chip->reg->regs[chip->ch].po);
  160. chip->ioh_gpio_reg.pm_reg =
  161. ioread32(&chip->reg->regs[chip->ch].pm);
  162. chip->ioh_gpio_reg.ien_reg =
  163. ioread32(&chip->reg->regs[chip->ch].ien);
  164. chip->ioh_gpio_reg.imask_reg =
  165. ioread32(&chip->reg->regs[chip->ch].imask);
  166. chip->ioh_gpio_reg.im0_reg =
  167. ioread32(&chip->reg->regs[chip->ch].im_0);
  168. chip->ioh_gpio_reg.im1_reg =
  169. ioread32(&chip->reg->regs[chip->ch].im_1);
  170. if (i < 4)
  171. chip->ioh_gpio_reg.use_sel_reg =
  172. ioread32(&chip->reg->ioh_sel_reg[i]);
  173. }
  174. }
  175. /*
  176. * This function restores the register configuration of the GPIO device.
  177. */
  178. static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
  179. {
  180. int i;
  181. for (i = 0; i < 8; i ++, chip++) {
  182. iowrite32(chip->ioh_gpio_reg.po_reg,
  183. &chip->reg->regs[chip->ch].po);
  184. iowrite32(chip->ioh_gpio_reg.pm_reg,
  185. &chip->reg->regs[chip->ch].pm);
  186. iowrite32(chip->ioh_gpio_reg.ien_reg,
  187. &chip->reg->regs[chip->ch].ien);
  188. iowrite32(chip->ioh_gpio_reg.imask_reg,
  189. &chip->reg->regs[chip->ch].imask);
  190. iowrite32(chip->ioh_gpio_reg.im0_reg,
  191. &chip->reg->regs[chip->ch].im_0);
  192. iowrite32(chip->ioh_gpio_reg.im1_reg,
  193. &chip->reg->regs[chip->ch].im_1);
  194. if (i < 4)
  195. iowrite32(chip->ioh_gpio_reg.use_sel_reg,
  196. &chip->reg->ioh_sel_reg[i]);
  197. }
  198. }
  199. #endif
  200. static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
  201. {
  202. struct ioh_gpio *chip = gpiochip_get_data(gpio);
  203. return chip->irq_base + offset;
  204. }
  205. static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
  206. {
  207. struct gpio_chip *gpio = &chip->gpio;
  208. gpio->label = dev_name(chip->dev);
  209. gpio->owner = THIS_MODULE;
  210. gpio->direction_input = ioh_gpio_direction_input;
  211. gpio->get = ioh_gpio_get;
  212. gpio->direction_output = ioh_gpio_direction_output;
  213. gpio->set = ioh_gpio_set;
  214. gpio->dbg_show = NULL;
  215. gpio->base = -1;
  216. gpio->ngpio = num_port;
  217. gpio->can_sleep = false;
  218. gpio->to_irq = ioh_gpio_to_irq;
  219. }
  220. static int ioh_irq_type(struct irq_data *d, unsigned int type)
  221. {
  222. u32 im;
  223. void __iomem *im_reg;
  224. u32 ien;
  225. u32 im_pos;
  226. int ch;
  227. unsigned long flags;
  228. u32 val;
  229. int irq = d->irq;
  230. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  231. struct ioh_gpio *chip = gc->private;
  232. ch = irq - chip->irq_base;
  233. if (irq <= chip->irq_base + 7) {
  234. im_reg = &chip->reg->regs[chip->ch].im_0;
  235. im_pos = ch;
  236. } else {
  237. im_reg = &chip->reg->regs[chip->ch].im_1;
  238. im_pos = ch - 8;
  239. }
  240. dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
  241. __func__, irq, type, ch, im_pos, type);
  242. spin_lock_irqsave(&chip->spinlock, flags);
  243. switch (type) {
  244. case IRQ_TYPE_EDGE_RISING:
  245. val = IOH_EDGE_RISING;
  246. break;
  247. case IRQ_TYPE_EDGE_FALLING:
  248. val = IOH_EDGE_FALLING;
  249. break;
  250. case IRQ_TYPE_EDGE_BOTH:
  251. val = IOH_EDGE_BOTH;
  252. break;
  253. case IRQ_TYPE_LEVEL_HIGH:
  254. val = IOH_LEVEL_H;
  255. break;
  256. case IRQ_TYPE_LEVEL_LOW:
  257. val = IOH_LEVEL_L;
  258. break;
  259. case IRQ_TYPE_PROBE:
  260. goto end;
  261. default:
  262. dev_warn(chip->dev, "%s: unknown type(%dd)",
  263. __func__, type);
  264. goto end;
  265. }
  266. /* Set interrupt mode */
  267. im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
  268. iowrite32(im | (val << (im_pos * 4)), im_reg);
  269. /* iclr */
  270. iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
  271. /* IMASKCLR */
  272. iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
  273. /* Enable interrupt */
  274. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  275. iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
  276. end:
  277. spin_unlock_irqrestore(&chip->spinlock, flags);
  278. return 0;
  279. }
  280. static void ioh_irq_unmask(struct irq_data *d)
  281. {
  282. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  283. struct ioh_gpio *chip = gc->private;
  284. iowrite32(1 << (d->irq - chip->irq_base),
  285. &chip->reg->regs[chip->ch].imaskclr);
  286. }
  287. static void ioh_irq_mask(struct irq_data *d)
  288. {
  289. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  290. struct ioh_gpio *chip = gc->private;
  291. iowrite32(1 << (d->irq - chip->irq_base),
  292. &chip->reg->regs[chip->ch].imask);
  293. }
  294. static void ioh_irq_disable(struct irq_data *d)
  295. {
  296. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  297. struct ioh_gpio *chip = gc->private;
  298. unsigned long flags;
  299. u32 ien;
  300. spin_lock_irqsave(&chip->spinlock, flags);
  301. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  302. ien &= ~(1 << (d->irq - chip->irq_base));
  303. iowrite32(ien, &chip->reg->regs[chip->ch].ien);
  304. spin_unlock_irqrestore(&chip->spinlock, flags);
  305. }
  306. static void ioh_irq_enable(struct irq_data *d)
  307. {
  308. struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  309. struct ioh_gpio *chip = gc->private;
  310. unsigned long flags;
  311. u32 ien;
  312. spin_lock_irqsave(&chip->spinlock, flags);
  313. ien = ioread32(&chip->reg->regs[chip->ch].ien);
  314. ien |= 1 << (d->irq - chip->irq_base);
  315. iowrite32(ien, &chip->reg->regs[chip->ch].ien);
  316. spin_unlock_irqrestore(&chip->spinlock, flags);
  317. }
  318. static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
  319. {
  320. struct ioh_gpio *chip = dev_id;
  321. u32 reg_val;
  322. int i, j;
  323. int ret = IRQ_NONE;
  324. for (i = 0; i < 8; i++, chip++) {
  325. reg_val = ioread32(&chip->reg->regs[i].istatus);
  326. for (j = 0; j < num_ports[i]; j++) {
  327. if (reg_val & BIT(j)) {
  328. dev_dbg(chip->dev,
  329. "%s:[%d]:irq=%d status=0x%x\n",
  330. __func__, j, irq, reg_val);
  331. iowrite32(BIT(j),
  332. &chip->reg->regs[chip->ch].iclr);
  333. generic_handle_irq(chip->irq_base + j);
  334. ret = IRQ_HANDLED;
  335. }
  336. }
  337. }
  338. return ret;
  339. }
  340. static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
  341. unsigned int irq_start, unsigned int num)
  342. {
  343. struct irq_chip_generic *gc;
  344. struct irq_chip_type *ct;
  345. gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
  346. handle_simple_irq);
  347. gc->private = chip;
  348. ct = gc->chip_types;
  349. ct->chip.irq_mask = ioh_irq_mask;
  350. ct->chip.irq_unmask = ioh_irq_unmask;
  351. ct->chip.irq_set_type = ioh_irq_type;
  352. ct->chip.irq_disable = ioh_irq_disable;
  353. ct->chip.irq_enable = ioh_irq_enable;
  354. irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  355. IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  356. }
  357. static int ioh_gpio_probe(struct pci_dev *pdev,
  358. const struct pci_device_id *id)
  359. {
  360. int ret;
  361. int i, j;
  362. struct ioh_gpio *chip;
  363. void __iomem *base;
  364. void *chip_save;
  365. int irq_base;
  366. ret = pci_enable_device(pdev);
  367. if (ret) {
  368. dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
  369. goto err_pci_enable;
  370. }
  371. ret = pci_request_regions(pdev, KBUILD_MODNAME);
  372. if (ret) {
  373. dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
  374. goto err_request_regions;
  375. }
  376. base = pci_iomap(pdev, 1, 0);
  377. if (!base) {
  378. dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
  379. ret = -ENOMEM;
  380. goto err_iomap;
  381. }
  382. chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
  383. if (chip_save == NULL) {
  384. dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
  385. ret = -ENOMEM;
  386. goto err_kzalloc;
  387. }
  388. chip = chip_save;
  389. for (i = 0; i < 8; i++, chip++) {
  390. chip->dev = &pdev->dev;
  391. chip->base = base;
  392. chip->reg = chip->base;
  393. chip->ch = i;
  394. spin_lock_init(&chip->spinlock);
  395. ioh_gpio_setup(chip, num_ports[i]);
  396. ret = gpiochip_add_data(&chip->gpio, chip);
  397. if (ret) {
  398. dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
  399. goto err_gpiochip_add;
  400. }
  401. }
  402. chip = chip_save;
  403. for (j = 0; j < 8; j++, chip++) {
  404. irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
  405. NUMA_NO_NODE);
  406. if (irq_base < 0) {
  407. dev_warn(&pdev->dev,
  408. "ml_ioh_gpio: Failed to get IRQ base num\n");
  409. chip->irq_base = -1;
  410. ret = irq_base;
  411. goto err_irq_alloc_descs;
  412. }
  413. chip->irq_base = irq_base;
  414. ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
  415. }
  416. chip = chip_save;
  417. ret = request_irq(pdev->irq, ioh_gpio_handler,
  418. IRQF_SHARED, KBUILD_MODNAME, chip);
  419. if (ret != 0) {
  420. dev_err(&pdev->dev,
  421. "%s request_irq failed\n", __func__);
  422. goto err_request_irq;
  423. }
  424. pci_set_drvdata(pdev, chip);
  425. return 0;
  426. err_request_irq:
  427. chip = chip_save;
  428. err_irq_alloc_descs:
  429. while (--j >= 0) {
  430. chip--;
  431. irq_free_descs(chip->irq_base, num_ports[j]);
  432. }
  433. chip = chip_save;
  434. err_gpiochip_add:
  435. while (--i >= 0) {
  436. chip--;
  437. gpiochip_remove(&chip->gpio);
  438. }
  439. kfree(chip_save);
  440. err_kzalloc:
  441. pci_iounmap(pdev, base);
  442. err_iomap:
  443. pci_release_regions(pdev);
  444. err_request_regions:
  445. pci_disable_device(pdev);
  446. err_pci_enable:
  447. dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
  448. return ret;
  449. }
  450. static void ioh_gpio_remove(struct pci_dev *pdev)
  451. {
  452. int i;
  453. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  454. void *chip_save;
  455. chip_save = chip;
  456. free_irq(pdev->irq, chip);
  457. for (i = 0; i < 8; i++, chip++) {
  458. irq_free_descs(chip->irq_base, num_ports[i]);
  459. gpiochip_remove(&chip->gpio);
  460. }
  461. chip = chip_save;
  462. pci_iounmap(pdev, chip->base);
  463. pci_release_regions(pdev);
  464. pci_disable_device(pdev);
  465. kfree(chip);
  466. }
  467. #ifdef CONFIG_PM
  468. static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
  469. {
  470. s32 ret;
  471. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  472. unsigned long flags;
  473. spin_lock_irqsave(&chip->spinlock, flags);
  474. ioh_gpio_save_reg_conf(chip);
  475. spin_unlock_irqrestore(&chip->spinlock, flags);
  476. ret = pci_save_state(pdev);
  477. if (ret) {
  478. dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
  479. return ret;
  480. }
  481. pci_disable_device(pdev);
  482. pci_set_power_state(pdev, PCI_D0);
  483. ret = pci_enable_wake(pdev, PCI_D0, 1);
  484. if (ret)
  485. dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
  486. return 0;
  487. }
  488. static int ioh_gpio_resume(struct pci_dev *pdev)
  489. {
  490. s32 ret;
  491. struct ioh_gpio *chip = pci_get_drvdata(pdev);
  492. unsigned long flags;
  493. ret = pci_enable_wake(pdev, PCI_D0, 0);
  494. pci_set_power_state(pdev, PCI_D0);
  495. ret = pci_enable_device(pdev);
  496. if (ret) {
  497. dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
  498. return ret;
  499. }
  500. pci_restore_state(pdev);
  501. spin_lock_irqsave(&chip->spinlock, flags);
  502. iowrite32(0x01, &chip->reg->srst);
  503. iowrite32(0x00, &chip->reg->srst);
  504. ioh_gpio_restore_reg_conf(chip);
  505. spin_unlock_irqrestore(&chip->spinlock, flags);
  506. return 0;
  507. }
  508. #else
  509. #define ioh_gpio_suspend NULL
  510. #define ioh_gpio_resume NULL
  511. #endif
  512. static const struct pci_device_id ioh_gpio_pcidev_id[] = {
  513. { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
  514. { 0, }
  515. };
  516. MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
  517. static struct pci_driver ioh_gpio_driver = {
  518. .name = "ml_ioh_gpio",
  519. .id_table = ioh_gpio_pcidev_id,
  520. .probe = ioh_gpio_probe,
  521. .remove = ioh_gpio_remove,
  522. .suspend = ioh_gpio_suspend,
  523. .resume = ioh_gpio_resume
  524. };
  525. module_pci_driver(ioh_gpio_driver);
  526. MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
  527. MODULE_LICENSE("GPL");