gpio-em.c 11 KB

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  1. /*
  2. * Emma Mobile GPIO Support - GIO
  3. *
  4. * Copyright (C) 2012 Magnus Damm
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/init.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/ioport.h>
  24. #include <linux/io.h>
  25. #include <linux/irq.h>
  26. #include <linux/irqdomain.h>
  27. #include <linux/bitops.h>
  28. #include <linux/err.h>
  29. #include <linux/gpio.h>
  30. #include <linux/slab.h>
  31. #include <linux/module.h>
  32. #include <linux/pinctrl/consumer.h>
  33. struct em_gio_priv {
  34. void __iomem *base0;
  35. void __iomem *base1;
  36. spinlock_t sense_lock;
  37. struct platform_device *pdev;
  38. struct gpio_chip gpio_chip;
  39. struct irq_chip irq_chip;
  40. struct irq_domain *irq_domain;
  41. };
  42. #define GIO_E1 0x00
  43. #define GIO_E0 0x04
  44. #define GIO_EM 0x04
  45. #define GIO_OL 0x08
  46. #define GIO_OH 0x0c
  47. #define GIO_I 0x10
  48. #define GIO_IIA 0x14
  49. #define GIO_IEN 0x18
  50. #define GIO_IDS 0x1c
  51. #define GIO_IIM 0x1c
  52. #define GIO_RAW 0x20
  53. #define GIO_MST 0x24
  54. #define GIO_IIR 0x28
  55. #define GIO_IDT0 0x40
  56. #define GIO_IDT1 0x44
  57. #define GIO_IDT2 0x48
  58. #define GIO_IDT3 0x4c
  59. #define GIO_RAWBL 0x50
  60. #define GIO_RAWBH 0x54
  61. #define GIO_IRBL 0x58
  62. #define GIO_IRBH 0x5c
  63. #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  64. static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  65. {
  66. if (offs < GIO_IDT0)
  67. return ioread32(p->base0 + offs);
  68. else
  69. return ioread32(p->base1 + (offs - GIO_IDT0));
  70. }
  71. static inline void em_gio_write(struct em_gio_priv *p, int offs,
  72. unsigned long value)
  73. {
  74. if (offs < GIO_IDT0)
  75. iowrite32(value, p->base0 + offs);
  76. else
  77. iowrite32(value, p->base1 + (offs - GIO_IDT0));
  78. }
  79. static void em_gio_irq_disable(struct irq_data *d)
  80. {
  81. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  82. em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  83. }
  84. static void em_gio_irq_enable(struct irq_data *d)
  85. {
  86. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  87. em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
  88. }
  89. static int em_gio_irq_reqres(struct irq_data *d)
  90. {
  91. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  92. if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
  93. dev_err(p->gpio_chip.parent,
  94. "unable to lock HW IRQ %lu for IRQ\n",
  95. irqd_to_hwirq(d));
  96. return -EINVAL;
  97. }
  98. return 0;
  99. }
  100. static void em_gio_irq_relres(struct irq_data *d)
  101. {
  102. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  103. gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
  104. }
  105. #define GIO_ASYNC(x) (x + 8)
  106. static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
  107. [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
  108. [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
  109. [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
  110. [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
  111. [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
  112. };
  113. static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
  114. {
  115. unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
  116. struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  117. unsigned int reg, offset, shift;
  118. unsigned long flags;
  119. unsigned long tmp;
  120. if (!value)
  121. return -EINVAL;
  122. offset = irqd_to_hwirq(d);
  123. pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
  124. /* 8 x 4 bit fields in 4 IDT registers */
  125. reg = GIO_IDT(offset >> 3);
  126. shift = (offset & 0x07) << 4;
  127. spin_lock_irqsave(&p->sense_lock, flags);
  128. /* disable the interrupt in IIA */
  129. tmp = em_gio_read(p, GIO_IIA);
  130. tmp &= ~BIT(offset);
  131. em_gio_write(p, GIO_IIA, tmp);
  132. /* change the sense setting in IDT */
  133. tmp = em_gio_read(p, reg);
  134. tmp &= ~(0xf << shift);
  135. tmp |= value << shift;
  136. em_gio_write(p, reg, tmp);
  137. /* clear pending interrupts */
  138. em_gio_write(p, GIO_IIR, BIT(offset));
  139. /* enable the interrupt in IIA */
  140. tmp = em_gio_read(p, GIO_IIA);
  141. tmp |= BIT(offset);
  142. em_gio_write(p, GIO_IIA, tmp);
  143. spin_unlock_irqrestore(&p->sense_lock, flags);
  144. return 0;
  145. }
  146. static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
  147. {
  148. struct em_gio_priv *p = dev_id;
  149. unsigned long pending;
  150. unsigned int offset, irqs_handled = 0;
  151. while ((pending = em_gio_read(p, GIO_MST))) {
  152. offset = __ffs(pending);
  153. em_gio_write(p, GIO_IIR, BIT(offset));
  154. generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
  155. irqs_handled++;
  156. }
  157. return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
  158. }
  159. static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
  160. {
  161. return gpiochip_get_data(chip);
  162. }
  163. static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
  164. {
  165. em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
  166. return 0;
  167. }
  168. static int em_gio_get(struct gpio_chip *chip, unsigned offset)
  169. {
  170. return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
  171. }
  172. static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
  173. unsigned shift, int value)
  174. {
  175. /* upper 16 bits contains mask and lower 16 actual value */
  176. em_gio_write(gpio_to_priv(chip), reg,
  177. (BIT(shift + 16)) | (value << shift));
  178. }
  179. static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
  180. {
  181. /* output is split into two registers */
  182. if (offset < 16)
  183. __em_gio_set(chip, GIO_OL, offset, value);
  184. else
  185. __em_gio_set(chip, GIO_OH, offset - 16, value);
  186. }
  187. static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
  188. int value)
  189. {
  190. /* write GPIO value to output before selecting output mode of pin */
  191. em_gio_set(chip, offset, value);
  192. em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
  193. return 0;
  194. }
  195. static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
  196. {
  197. return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
  198. }
  199. static int em_gio_request(struct gpio_chip *chip, unsigned offset)
  200. {
  201. return pinctrl_request_gpio(chip->base + offset);
  202. }
  203. static void em_gio_free(struct gpio_chip *chip, unsigned offset)
  204. {
  205. pinctrl_free_gpio(chip->base + offset);
  206. /* Set the GPIO as an input to ensure that the next GPIO request won't
  207. * drive the GPIO pin as an output.
  208. */
  209. em_gio_direction_input(chip, offset);
  210. }
  211. static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
  212. irq_hw_number_t hwirq)
  213. {
  214. struct em_gio_priv *p = h->host_data;
  215. pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
  216. irq_set_chip_data(irq, h->host_data);
  217. irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
  218. return 0;
  219. }
  220. static const struct irq_domain_ops em_gio_irq_domain_ops = {
  221. .map = em_gio_irq_domain_map,
  222. .xlate = irq_domain_xlate_twocell,
  223. };
  224. static int em_gio_probe(struct platform_device *pdev)
  225. {
  226. struct em_gio_priv *p;
  227. struct resource *io[2], *irq[2];
  228. struct gpio_chip *gpio_chip;
  229. struct irq_chip *irq_chip;
  230. const char *name = dev_name(&pdev->dev);
  231. unsigned int ngpios;
  232. int ret;
  233. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  234. if (!p) {
  235. ret = -ENOMEM;
  236. goto err0;
  237. }
  238. p->pdev = pdev;
  239. platform_set_drvdata(pdev, p);
  240. spin_lock_init(&p->sense_lock);
  241. io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  242. io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  243. irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  244. irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
  245. if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
  246. dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
  247. ret = -EINVAL;
  248. goto err0;
  249. }
  250. p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
  251. resource_size(io[0]));
  252. if (!p->base0) {
  253. dev_err(&pdev->dev, "failed to remap low I/O memory\n");
  254. ret = -ENXIO;
  255. goto err0;
  256. }
  257. p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
  258. resource_size(io[1]));
  259. if (!p->base1) {
  260. dev_err(&pdev->dev, "failed to remap high I/O memory\n");
  261. ret = -ENXIO;
  262. goto err0;
  263. }
  264. if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
  265. dev_err(&pdev->dev, "Missing ngpios OF property\n");
  266. ret = -EINVAL;
  267. goto err0;
  268. }
  269. gpio_chip = &p->gpio_chip;
  270. gpio_chip->of_node = pdev->dev.of_node;
  271. gpio_chip->direction_input = em_gio_direction_input;
  272. gpio_chip->get = em_gio_get;
  273. gpio_chip->direction_output = em_gio_direction_output;
  274. gpio_chip->set = em_gio_set;
  275. gpio_chip->to_irq = em_gio_to_irq;
  276. gpio_chip->request = em_gio_request;
  277. gpio_chip->free = em_gio_free;
  278. gpio_chip->label = name;
  279. gpio_chip->parent = &pdev->dev;
  280. gpio_chip->owner = THIS_MODULE;
  281. gpio_chip->base = -1;
  282. gpio_chip->ngpio = ngpios;
  283. irq_chip = &p->irq_chip;
  284. irq_chip->name = name;
  285. irq_chip->irq_mask = em_gio_irq_disable;
  286. irq_chip->irq_unmask = em_gio_irq_enable;
  287. irq_chip->irq_set_type = em_gio_irq_set_type;
  288. irq_chip->irq_request_resources = em_gio_irq_reqres;
  289. irq_chip->irq_release_resources = em_gio_irq_relres;
  290. irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
  291. p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0,
  292. &em_gio_irq_domain_ops, p);
  293. if (!p->irq_domain) {
  294. ret = -ENXIO;
  295. dev_err(&pdev->dev, "cannot initialize irq domain\n");
  296. goto err0;
  297. }
  298. if (devm_request_irq(&pdev->dev, irq[0]->start,
  299. em_gio_irq_handler, 0, name, p)) {
  300. dev_err(&pdev->dev, "failed to request low IRQ\n");
  301. ret = -ENOENT;
  302. goto err1;
  303. }
  304. if (devm_request_irq(&pdev->dev, irq[1]->start,
  305. em_gio_irq_handler, 0, name, p)) {
  306. dev_err(&pdev->dev, "failed to request high IRQ\n");
  307. ret = -ENOENT;
  308. goto err1;
  309. }
  310. ret = gpiochip_add_data(gpio_chip, p);
  311. if (ret) {
  312. dev_err(&pdev->dev, "failed to add GPIO controller\n");
  313. goto err1;
  314. }
  315. return 0;
  316. err1:
  317. irq_domain_remove(p->irq_domain);
  318. err0:
  319. return ret;
  320. }
  321. static int em_gio_remove(struct platform_device *pdev)
  322. {
  323. struct em_gio_priv *p = platform_get_drvdata(pdev);
  324. gpiochip_remove(&p->gpio_chip);
  325. irq_domain_remove(p->irq_domain);
  326. return 0;
  327. }
  328. static const struct of_device_id em_gio_dt_ids[] = {
  329. { .compatible = "renesas,em-gio", },
  330. {},
  331. };
  332. MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
  333. static struct platform_driver em_gio_device_driver = {
  334. .probe = em_gio_probe,
  335. .remove = em_gio_remove,
  336. .driver = {
  337. .name = "em_gio",
  338. .of_match_table = em_gio_dt_ids,
  339. }
  340. };
  341. static int __init em_gio_init(void)
  342. {
  343. return platform_driver_register(&em_gio_device_driver);
  344. }
  345. postcore_initcall(em_gio_init);
  346. static void __exit em_gio_exit(void)
  347. {
  348. platform_driver_unregister(&em_gio_device_driver);
  349. }
  350. module_exit(em_gio_exit);
  351. MODULE_AUTHOR("Magnus Damm");
  352. MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
  353. MODULE_LICENSE("GPL v2");