gpio-dln2.c 13 KB

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  1. /*
  2. * Driver for the Diolan DLN-2 USB-GPIO adapter
  3. *
  4. * Copyright (c) 2014 Intel Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation, version 2.
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/slab.h>
  13. #include <linux/types.h>
  14. #include <linux/irqdomain.h>
  15. #include <linux/irq.h>
  16. #include <linux/irqchip/chained_irq.h>
  17. #include <linux/gpio.h>
  18. #include <linux/gpio/driver.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/mfd/dln2.h>
  21. #define DLN2_GPIO_ID 0x01
  22. #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
  23. #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
  24. #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
  25. #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
  26. #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
  27. #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
  28. #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
  29. #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
  30. #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
  31. #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
  32. #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
  33. #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
  34. #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
  35. #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
  36. #define DLN2_GPIO_EVENT_NONE 0
  37. #define DLN2_GPIO_EVENT_CHANGE 1
  38. #define DLN2_GPIO_EVENT_LVL_HIGH 2
  39. #define DLN2_GPIO_EVENT_LVL_LOW 3
  40. #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
  41. #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
  42. #define DLN2_GPIO_EVENT_MASK 0x0F
  43. #define DLN2_GPIO_MAX_PINS 32
  44. struct dln2_gpio {
  45. struct platform_device *pdev;
  46. struct gpio_chip gpio;
  47. /*
  48. * Cache pin direction to save us one transfer, since the hardware has
  49. * separate commands to read the in and out values.
  50. */
  51. DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
  52. /* active IRQs - not synced to hardware */
  53. DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
  54. /* active IRQS - synced to hardware */
  55. DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
  56. int irq_type[DLN2_GPIO_MAX_PINS];
  57. struct mutex irq_lock;
  58. };
  59. struct dln2_gpio_pin {
  60. __le16 pin;
  61. };
  62. struct dln2_gpio_pin_val {
  63. __le16 pin __packed;
  64. u8 value;
  65. };
  66. static int dln2_gpio_get_pin_count(struct platform_device *pdev)
  67. {
  68. int ret;
  69. __le16 count;
  70. int len = sizeof(count);
  71. ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
  72. if (ret < 0)
  73. return ret;
  74. if (len < sizeof(count))
  75. return -EPROTO;
  76. return le16_to_cpu(count);
  77. }
  78. static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
  79. {
  80. struct dln2_gpio_pin req = {
  81. .pin = cpu_to_le16(pin),
  82. };
  83. return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
  84. }
  85. static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
  86. {
  87. int ret;
  88. struct dln2_gpio_pin req = {
  89. .pin = cpu_to_le16(pin),
  90. };
  91. struct dln2_gpio_pin_val rsp;
  92. int len = sizeof(rsp);
  93. ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
  94. if (ret < 0)
  95. return ret;
  96. if (len < sizeof(rsp) || req.pin != rsp.pin)
  97. return -EPROTO;
  98. return rsp.value;
  99. }
  100. static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
  101. {
  102. int ret;
  103. ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
  104. if (ret < 0)
  105. return ret;
  106. return !!ret;
  107. }
  108. static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
  109. {
  110. int ret;
  111. ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
  112. if (ret < 0)
  113. return ret;
  114. return !!ret;
  115. }
  116. static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
  117. unsigned int pin, int value)
  118. {
  119. struct dln2_gpio_pin_val req = {
  120. .pin = cpu_to_le16(pin),
  121. .value = value,
  122. };
  123. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
  124. sizeof(req));
  125. }
  126. #define DLN2_GPIO_DIRECTION_IN 0
  127. #define DLN2_GPIO_DIRECTION_OUT 1
  128. static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
  129. {
  130. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  131. struct dln2_gpio_pin req = {
  132. .pin = cpu_to_le16(offset),
  133. };
  134. struct dln2_gpio_pin_val rsp;
  135. int len = sizeof(rsp);
  136. int ret;
  137. ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
  138. if (ret < 0)
  139. return ret;
  140. /* cache the pin direction */
  141. ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
  142. &req, sizeof(req), &rsp, &len);
  143. if (ret < 0)
  144. return ret;
  145. if (len < sizeof(rsp) || req.pin != rsp.pin) {
  146. ret = -EPROTO;
  147. goto out_disable;
  148. }
  149. switch (rsp.value) {
  150. case DLN2_GPIO_DIRECTION_IN:
  151. clear_bit(offset, dln2->output_enabled);
  152. return 0;
  153. case DLN2_GPIO_DIRECTION_OUT:
  154. set_bit(offset, dln2->output_enabled);
  155. return 0;
  156. default:
  157. ret = -EPROTO;
  158. goto out_disable;
  159. }
  160. out_disable:
  161. dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
  162. return ret;
  163. }
  164. static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
  165. {
  166. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  167. dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
  168. }
  169. static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  170. {
  171. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  172. if (test_bit(offset, dln2->output_enabled))
  173. return GPIOF_DIR_OUT;
  174. return GPIOF_DIR_IN;
  175. }
  176. static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
  177. {
  178. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  179. int dir;
  180. dir = dln2_gpio_get_direction(chip, offset);
  181. if (dir < 0)
  182. return dir;
  183. if (dir == GPIOF_DIR_IN)
  184. return dln2_gpio_pin_get_in_val(dln2, offset);
  185. return dln2_gpio_pin_get_out_val(dln2, offset);
  186. }
  187. static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  188. {
  189. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  190. dln2_gpio_pin_set_out_val(dln2, offset, value);
  191. }
  192. static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
  193. unsigned dir)
  194. {
  195. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  196. struct dln2_gpio_pin_val req = {
  197. .pin = cpu_to_le16(offset),
  198. .value = dir,
  199. };
  200. int ret;
  201. ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
  202. &req, sizeof(req));
  203. if (ret < 0)
  204. return ret;
  205. if (dir == DLN2_GPIO_DIRECTION_OUT)
  206. set_bit(offset, dln2->output_enabled);
  207. else
  208. clear_bit(offset, dln2->output_enabled);
  209. return ret;
  210. }
  211. static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  212. {
  213. return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
  214. }
  215. static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
  216. int value)
  217. {
  218. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  219. int ret;
  220. ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
  221. if (ret < 0)
  222. return ret;
  223. return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
  224. }
  225. static int dln2_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
  226. unsigned debounce)
  227. {
  228. struct dln2_gpio *dln2 = gpiochip_get_data(chip);
  229. __le32 duration = cpu_to_le32(debounce);
  230. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
  231. &duration, sizeof(duration));
  232. }
  233. static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
  234. unsigned type, unsigned period)
  235. {
  236. struct {
  237. __le16 pin;
  238. u8 type;
  239. __le16 period;
  240. } __packed req = {
  241. .pin = cpu_to_le16(pin),
  242. .type = type,
  243. .period = cpu_to_le16(period),
  244. };
  245. return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
  246. &req, sizeof(req));
  247. }
  248. static void dln2_irq_unmask(struct irq_data *irqd)
  249. {
  250. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  251. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  252. int pin = irqd_to_hwirq(irqd);
  253. set_bit(pin, dln2->unmasked_irqs);
  254. }
  255. static void dln2_irq_mask(struct irq_data *irqd)
  256. {
  257. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  258. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  259. int pin = irqd_to_hwirq(irqd);
  260. clear_bit(pin, dln2->unmasked_irqs);
  261. }
  262. static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
  263. {
  264. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  265. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  266. int pin = irqd_to_hwirq(irqd);
  267. switch (type) {
  268. case IRQ_TYPE_LEVEL_HIGH:
  269. dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
  270. break;
  271. case IRQ_TYPE_LEVEL_LOW:
  272. dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
  273. break;
  274. case IRQ_TYPE_EDGE_BOTH:
  275. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
  276. break;
  277. case IRQ_TYPE_EDGE_RISING:
  278. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
  279. break;
  280. case IRQ_TYPE_EDGE_FALLING:
  281. dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
  282. break;
  283. default:
  284. return -EINVAL;
  285. }
  286. return 0;
  287. }
  288. static void dln2_irq_bus_lock(struct irq_data *irqd)
  289. {
  290. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  291. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  292. mutex_lock(&dln2->irq_lock);
  293. }
  294. static void dln2_irq_bus_unlock(struct irq_data *irqd)
  295. {
  296. struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
  297. struct dln2_gpio *dln2 = gpiochip_get_data(gc);
  298. int pin = irqd_to_hwirq(irqd);
  299. int enabled, unmasked;
  300. unsigned type;
  301. int ret;
  302. enabled = test_bit(pin, dln2->enabled_irqs);
  303. unmasked = test_bit(pin, dln2->unmasked_irqs);
  304. if (enabled != unmasked) {
  305. if (unmasked) {
  306. type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
  307. set_bit(pin, dln2->enabled_irqs);
  308. } else {
  309. type = DLN2_GPIO_EVENT_NONE;
  310. clear_bit(pin, dln2->enabled_irqs);
  311. }
  312. ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
  313. if (ret)
  314. dev_err(dln2->gpio.parent, "failed to set event\n");
  315. }
  316. mutex_unlock(&dln2->irq_lock);
  317. }
  318. static struct irq_chip dln2_gpio_irqchip = {
  319. .name = "dln2-irq",
  320. .irq_mask = dln2_irq_mask,
  321. .irq_unmask = dln2_irq_unmask,
  322. .irq_set_type = dln2_irq_set_type,
  323. .irq_bus_lock = dln2_irq_bus_lock,
  324. .irq_bus_sync_unlock = dln2_irq_bus_unlock,
  325. };
  326. static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
  327. const void *data, int len)
  328. {
  329. int pin, irq;
  330. const struct {
  331. __le16 count;
  332. __u8 type;
  333. __le16 pin;
  334. __u8 value;
  335. } __packed *event = data;
  336. struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
  337. if (len < sizeof(*event)) {
  338. dev_err(dln2->gpio.parent, "short event message\n");
  339. return;
  340. }
  341. pin = le16_to_cpu(event->pin);
  342. if (pin >= dln2->gpio.ngpio) {
  343. dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
  344. return;
  345. }
  346. irq = irq_find_mapping(dln2->gpio.irqdomain, pin);
  347. if (!irq) {
  348. dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
  349. return;
  350. }
  351. switch (dln2->irq_type[pin]) {
  352. case DLN2_GPIO_EVENT_CHANGE_RISING:
  353. if (event->value)
  354. generic_handle_irq(irq);
  355. break;
  356. case DLN2_GPIO_EVENT_CHANGE_FALLING:
  357. if (!event->value)
  358. generic_handle_irq(irq);
  359. break;
  360. default:
  361. generic_handle_irq(irq);
  362. }
  363. }
  364. static int dln2_gpio_probe(struct platform_device *pdev)
  365. {
  366. struct dln2_gpio *dln2;
  367. struct device *dev = &pdev->dev;
  368. int pins;
  369. int ret;
  370. pins = dln2_gpio_get_pin_count(pdev);
  371. if (pins < 0) {
  372. dev_err(dev, "failed to get pin count: %d\n", pins);
  373. return pins;
  374. }
  375. if (pins > DLN2_GPIO_MAX_PINS) {
  376. pins = DLN2_GPIO_MAX_PINS;
  377. dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
  378. }
  379. dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
  380. if (!dln2)
  381. return -ENOMEM;
  382. mutex_init(&dln2->irq_lock);
  383. dln2->pdev = pdev;
  384. dln2->gpio.label = "dln2";
  385. dln2->gpio.parent = dev;
  386. dln2->gpio.owner = THIS_MODULE;
  387. dln2->gpio.base = -1;
  388. dln2->gpio.ngpio = pins;
  389. dln2->gpio.can_sleep = true;
  390. dln2->gpio.irq_not_threaded = true;
  391. dln2->gpio.set = dln2_gpio_set;
  392. dln2->gpio.get = dln2_gpio_get;
  393. dln2->gpio.request = dln2_gpio_request;
  394. dln2->gpio.free = dln2_gpio_free;
  395. dln2->gpio.get_direction = dln2_gpio_get_direction;
  396. dln2->gpio.direction_input = dln2_gpio_direction_input;
  397. dln2->gpio.direction_output = dln2_gpio_direction_output;
  398. dln2->gpio.set_debounce = dln2_gpio_set_debounce;
  399. platform_set_drvdata(pdev, dln2);
  400. ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
  401. if (ret < 0) {
  402. dev_err(dev, "failed to add gpio chip: %d\n", ret);
  403. return ret;
  404. }
  405. ret = gpiochip_irqchip_add(&dln2->gpio, &dln2_gpio_irqchip, 0,
  406. handle_simple_irq, IRQ_TYPE_NONE);
  407. if (ret < 0) {
  408. dev_err(dev, "failed to add irq chip: %d\n", ret);
  409. return ret;
  410. }
  411. ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
  412. dln2_gpio_event);
  413. if (ret) {
  414. dev_err(dev, "failed to register event cb: %d\n", ret);
  415. return ret;
  416. }
  417. return 0;
  418. }
  419. static int dln2_gpio_remove(struct platform_device *pdev)
  420. {
  421. dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
  422. return 0;
  423. }
  424. static struct platform_driver dln2_gpio_driver = {
  425. .driver.name = "dln2-gpio",
  426. .probe = dln2_gpio_probe,
  427. .remove = dln2_gpio_remove,
  428. };
  429. module_platform_driver(dln2_gpio_driver);
  430. MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
  431. MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
  432. MODULE_LICENSE("GPL v2");
  433. MODULE_ALIAS("platform:dln2-gpio");