gpio-crystalcove.c 9.9 KB

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  1. /*
  2. * gpio-crystalcove.c - Intel Crystal Cove GPIO Driver
  3. *
  4. * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License version
  8. * 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * Author: Yang, Bin <bin.yang@intel.com>
  16. */
  17. #include <linux/interrupt.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/gpio.h>
  21. #include <linux/seq_file.h>
  22. #include <linux/bitops.h>
  23. #include <linux/regmap.h>
  24. #include <linux/mfd/intel_soc_pmic.h>
  25. #define CRYSTALCOVE_GPIO_NUM 16
  26. #define CRYSTALCOVE_VGPIO_NUM 95
  27. #define UPDATE_IRQ_TYPE BIT(0)
  28. #define UPDATE_IRQ_MASK BIT(1)
  29. #define GPIO0IRQ 0x0b
  30. #define GPIO1IRQ 0x0c
  31. #define MGPIO0IRQS0 0x19
  32. #define MGPIO1IRQS0 0x1a
  33. #define MGPIO0IRQSX 0x1b
  34. #define MGPIO1IRQSX 0x1c
  35. #define GPIO0P0CTLO 0x2b
  36. #define GPIO0P0CTLI 0x33
  37. #define GPIO1P0CTLO 0x3b
  38. #define GPIO1P0CTLI 0x43
  39. #define GPIOPANELCTL 0x52
  40. #define CTLI_INTCNT_DIS (0)
  41. #define CTLI_INTCNT_NE (1 << 1)
  42. #define CTLI_INTCNT_PE (2 << 1)
  43. #define CTLI_INTCNT_BE (3 << 1)
  44. #define CTLO_DIR_IN (0)
  45. #define CTLO_DIR_OUT (1 << 5)
  46. #define CTLO_DRV_CMOS (0)
  47. #define CTLO_DRV_OD (1 << 4)
  48. #define CTLO_DRV_REN (1 << 3)
  49. #define CTLO_RVAL_2KDW (0)
  50. #define CTLO_RVAL_2KUP (1 << 1)
  51. #define CTLO_RVAL_50KDW (2 << 1)
  52. #define CTLO_RVAL_50KUP (3 << 1)
  53. #define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
  54. #define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET)
  55. enum ctrl_register {
  56. CTRL_IN,
  57. CTRL_OUT,
  58. };
  59. /**
  60. * struct crystalcove_gpio - Crystal Cove GPIO controller
  61. * @buslock: for bus lock/sync and unlock.
  62. * @chip: the abstract gpio_chip structure.
  63. * @regmap: the regmap from the parent device.
  64. * @update: pending IRQ setting update, to be written to the chip upon unlock.
  65. * @intcnt_value: the Interrupt Detect value to be written.
  66. * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
  67. */
  68. struct crystalcove_gpio {
  69. struct mutex buslock; /* irq_bus_lock */
  70. struct gpio_chip chip;
  71. struct regmap *regmap;
  72. int update;
  73. int intcnt_value;
  74. bool set_irq_mask;
  75. };
  76. static inline int to_reg(int gpio, enum ctrl_register reg_type)
  77. {
  78. int reg;
  79. if (gpio >= CRYSTALCOVE_GPIO_NUM) {
  80. /*
  81. * Virtual GPIO called from ACPI, for now we only support
  82. * the panel ctl.
  83. */
  84. switch (gpio) {
  85. case 0x5e:
  86. return GPIOPANELCTL;
  87. default:
  88. return -EOPNOTSUPP;
  89. }
  90. }
  91. if (reg_type == CTRL_IN) {
  92. if (gpio < 8)
  93. reg = GPIO0P0CTLI;
  94. else
  95. reg = GPIO1P0CTLI;
  96. } else {
  97. if (gpio < 8)
  98. reg = GPIO0P0CTLO;
  99. else
  100. reg = GPIO1P0CTLO;
  101. }
  102. return reg + gpio % 8;
  103. }
  104. static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
  105. int gpio)
  106. {
  107. u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
  108. int mask = BIT(gpio % 8);
  109. if (cg->set_irq_mask)
  110. regmap_update_bits(cg->regmap, mirqs0, mask, mask);
  111. else
  112. regmap_update_bits(cg->regmap, mirqs0, mask, 0);
  113. }
  114. static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
  115. {
  116. int reg = to_reg(gpio, CTRL_IN);
  117. regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
  118. }
  119. static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned gpio)
  120. {
  121. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  122. int reg = to_reg(gpio, CTRL_OUT);
  123. if (reg < 0)
  124. return 0;
  125. return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
  126. }
  127. static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned gpio,
  128. int value)
  129. {
  130. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  131. int reg = to_reg(gpio, CTRL_OUT);
  132. if (reg < 0)
  133. return 0;
  134. return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
  135. }
  136. static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned gpio)
  137. {
  138. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  139. unsigned int val;
  140. int ret, reg = to_reg(gpio, CTRL_IN);
  141. if (reg < 0)
  142. return 0;
  143. ret = regmap_read(cg->regmap, reg, &val);
  144. if (ret)
  145. return ret;
  146. return val & 0x1;
  147. }
  148. static void crystalcove_gpio_set(struct gpio_chip *chip,
  149. unsigned gpio, int value)
  150. {
  151. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  152. int reg = to_reg(gpio, CTRL_OUT);
  153. if (reg < 0)
  154. return;
  155. if (value)
  156. regmap_update_bits(cg->regmap, reg, 1, 1);
  157. else
  158. regmap_update_bits(cg->regmap, reg, 1, 0);
  159. }
  160. static int crystalcove_irq_type(struct irq_data *data, unsigned type)
  161. {
  162. struct crystalcove_gpio *cg =
  163. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  164. if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
  165. return 0;
  166. switch (type) {
  167. case IRQ_TYPE_NONE:
  168. cg->intcnt_value = CTLI_INTCNT_DIS;
  169. break;
  170. case IRQ_TYPE_EDGE_BOTH:
  171. cg->intcnt_value = CTLI_INTCNT_BE;
  172. break;
  173. case IRQ_TYPE_EDGE_RISING:
  174. cg->intcnt_value = CTLI_INTCNT_PE;
  175. break;
  176. case IRQ_TYPE_EDGE_FALLING:
  177. cg->intcnt_value = CTLI_INTCNT_NE;
  178. break;
  179. default:
  180. return -EINVAL;
  181. }
  182. cg->update |= UPDATE_IRQ_TYPE;
  183. return 0;
  184. }
  185. static void crystalcove_bus_lock(struct irq_data *data)
  186. {
  187. struct crystalcove_gpio *cg =
  188. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  189. mutex_lock(&cg->buslock);
  190. }
  191. static void crystalcove_bus_sync_unlock(struct irq_data *data)
  192. {
  193. struct crystalcove_gpio *cg =
  194. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  195. int gpio = data->hwirq;
  196. if (cg->update & UPDATE_IRQ_TYPE)
  197. crystalcove_update_irq_ctrl(cg, gpio);
  198. if (cg->update & UPDATE_IRQ_MASK)
  199. crystalcove_update_irq_mask(cg, gpio);
  200. cg->update = 0;
  201. mutex_unlock(&cg->buslock);
  202. }
  203. static void crystalcove_irq_unmask(struct irq_data *data)
  204. {
  205. struct crystalcove_gpio *cg =
  206. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  207. if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
  208. cg->set_irq_mask = false;
  209. cg->update |= UPDATE_IRQ_MASK;
  210. }
  211. }
  212. static void crystalcove_irq_mask(struct irq_data *data)
  213. {
  214. struct crystalcove_gpio *cg =
  215. gpiochip_get_data(irq_data_get_irq_chip_data(data));
  216. if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
  217. cg->set_irq_mask = true;
  218. cg->update |= UPDATE_IRQ_MASK;
  219. }
  220. }
  221. static struct irq_chip crystalcove_irqchip = {
  222. .name = "Crystal Cove",
  223. .irq_mask = crystalcove_irq_mask,
  224. .irq_unmask = crystalcove_irq_unmask,
  225. .irq_set_type = crystalcove_irq_type,
  226. .irq_bus_lock = crystalcove_bus_lock,
  227. .irq_bus_sync_unlock = crystalcove_bus_sync_unlock,
  228. .flags = IRQCHIP_SKIP_SET_WAKE,
  229. };
  230. static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
  231. {
  232. struct crystalcove_gpio *cg = data;
  233. unsigned int p0, p1;
  234. int pending;
  235. int gpio;
  236. unsigned int virq;
  237. if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
  238. regmap_read(cg->regmap, GPIO1IRQ, &p1))
  239. return IRQ_NONE;
  240. regmap_write(cg->regmap, GPIO0IRQ, p0);
  241. regmap_write(cg->regmap, GPIO1IRQ, p1);
  242. pending = p0 | p1 << 8;
  243. for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
  244. if (pending & BIT(gpio)) {
  245. virq = irq_find_mapping(cg->chip.irqdomain, gpio);
  246. handle_nested_irq(virq);
  247. }
  248. }
  249. return IRQ_HANDLED;
  250. }
  251. static void crystalcove_gpio_dbg_show(struct seq_file *s,
  252. struct gpio_chip *chip)
  253. {
  254. struct crystalcove_gpio *cg = gpiochip_get_data(chip);
  255. int gpio, offset;
  256. unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
  257. for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
  258. regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
  259. regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
  260. regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
  261. &mirqs0);
  262. regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
  263. &mirqsx);
  264. regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
  265. &irq);
  266. offset = gpio % 8;
  267. seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
  268. gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
  269. ctli & 0x1 ? "hi" : "lo",
  270. ctli & CTLI_INTCNT_NE ? "fall" : " ",
  271. ctli & CTLI_INTCNT_PE ? "rise" : " ",
  272. ctlo,
  273. mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask",
  274. mirqsx & BIT(offset) ? "sx mask " : "sx unmask",
  275. irq & BIT(offset) ? "pending" : " ");
  276. }
  277. }
  278. static int crystalcove_gpio_probe(struct platform_device *pdev)
  279. {
  280. int irq = platform_get_irq(pdev, 0);
  281. struct crystalcove_gpio *cg;
  282. int retval;
  283. struct device *dev = pdev->dev.parent;
  284. struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
  285. if (irq < 0)
  286. return irq;
  287. cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
  288. if (!cg)
  289. return -ENOMEM;
  290. platform_set_drvdata(pdev, cg);
  291. mutex_init(&cg->buslock);
  292. cg->chip.label = KBUILD_MODNAME;
  293. cg->chip.direction_input = crystalcove_gpio_dir_in;
  294. cg->chip.direction_output = crystalcove_gpio_dir_out;
  295. cg->chip.get = crystalcove_gpio_get;
  296. cg->chip.set = crystalcove_gpio_set;
  297. cg->chip.base = -1;
  298. cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
  299. cg->chip.can_sleep = true;
  300. cg->chip.parent = dev;
  301. cg->chip.dbg_show = crystalcove_gpio_dbg_show;
  302. cg->regmap = pmic->regmap;
  303. retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
  304. if (retval) {
  305. dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
  306. return retval;
  307. }
  308. gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,
  309. handle_simple_irq, IRQ_TYPE_NONE);
  310. retval = request_threaded_irq(irq, NULL, crystalcove_gpio_irq_handler,
  311. IRQF_ONESHOT, KBUILD_MODNAME, cg);
  312. if (retval) {
  313. dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
  314. return retval;
  315. }
  316. return 0;
  317. }
  318. static int crystalcove_gpio_remove(struct platform_device *pdev)
  319. {
  320. struct crystalcove_gpio *cg = platform_get_drvdata(pdev);
  321. int irq = platform_get_irq(pdev, 0);
  322. if (irq >= 0)
  323. free_irq(irq, cg);
  324. return 0;
  325. }
  326. static struct platform_driver crystalcove_gpio_driver = {
  327. .probe = crystalcove_gpio_probe,
  328. .remove = crystalcove_gpio_remove,
  329. .driver = {
  330. .name = "crystal_cove_gpio",
  331. },
  332. };
  333. module_platform_driver(crystalcove_gpio_driver);
  334. MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
  335. MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
  336. MODULE_LICENSE("GPL v2");