h8300_timer16.c 4.0 KB

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  1. /*
  2. * H8/300 16bit Timer driver
  3. *
  4. * Copyright 2015 Yoshinori Sato <ysato@users.sourcefoge.jp>
  5. */
  6. #include <linux/interrupt.h>
  7. #include <linux/init.h>
  8. #include <linux/clocksource.h>
  9. #include <linux/clk.h>
  10. #include <linux/io.h>
  11. #include <linux/of.h>
  12. #include <linux/of_address.h>
  13. #include <linux/of_irq.h>
  14. #define TSTR 0
  15. #define TISRC 6
  16. #define TCR 0
  17. #define TCNT 2
  18. #define bset(b, a) iowrite8(ioread8(a) | (1 << (b)), (a))
  19. #define bclr(b, a) iowrite8(ioread8(a) & ~(1 << (b)), (a))
  20. struct timer16_priv {
  21. struct clocksource cs;
  22. unsigned long total_cycles;
  23. void __iomem *mapbase;
  24. void __iomem *mapcommon;
  25. unsigned short cs_enabled;
  26. unsigned char enb;
  27. unsigned char ovf;
  28. unsigned char ovie;
  29. };
  30. static unsigned long timer16_get_counter(struct timer16_priv *p)
  31. {
  32. unsigned short v1, v2, v3;
  33. unsigned char o1, o2;
  34. o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
  35. /* Make sure the timer value is stable. Stolen from acpi_pm.c */
  36. do {
  37. o2 = o1;
  38. v1 = ioread16be(p->mapbase + TCNT);
  39. v2 = ioread16be(p->mapbase + TCNT);
  40. v3 = ioread16be(p->mapbase + TCNT);
  41. o1 = ioread8(p->mapcommon + TISRC) & p->ovf;
  42. } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
  43. || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
  44. if (likely(!o1))
  45. return v2;
  46. else
  47. return v2 + 0x10000;
  48. }
  49. static irqreturn_t timer16_interrupt(int irq, void *dev_id)
  50. {
  51. struct timer16_priv *p = (struct timer16_priv *)dev_id;
  52. bclr(p->ovf, p->mapcommon + TISRC);
  53. p->total_cycles += 0x10000;
  54. return IRQ_HANDLED;
  55. }
  56. static inline struct timer16_priv *cs_to_priv(struct clocksource *cs)
  57. {
  58. return container_of(cs, struct timer16_priv, cs);
  59. }
  60. static cycle_t timer16_clocksource_read(struct clocksource *cs)
  61. {
  62. struct timer16_priv *p = cs_to_priv(cs);
  63. unsigned long raw, value;
  64. value = p->total_cycles;
  65. raw = timer16_get_counter(p);
  66. return value + raw;
  67. }
  68. static int timer16_enable(struct clocksource *cs)
  69. {
  70. struct timer16_priv *p = cs_to_priv(cs);
  71. WARN_ON(p->cs_enabled);
  72. p->total_cycles = 0;
  73. iowrite16be(0x0000, p->mapbase + TCNT);
  74. iowrite8(0x83, p->mapbase + TCR);
  75. bset(p->ovie, p->mapcommon + TISRC);
  76. bset(p->enb, p->mapcommon + TSTR);
  77. p->cs_enabled = true;
  78. return 0;
  79. }
  80. static void timer16_disable(struct clocksource *cs)
  81. {
  82. struct timer16_priv *p = cs_to_priv(cs);
  83. WARN_ON(!p->cs_enabled);
  84. bclr(p->ovie, p->mapcommon + TISRC);
  85. bclr(p->enb, p->mapcommon + TSTR);
  86. p->cs_enabled = false;
  87. }
  88. static struct timer16_priv timer16_priv = {
  89. .cs = {
  90. .name = "h8300_16timer",
  91. .rating = 200,
  92. .read = timer16_clocksource_read,
  93. .enable = timer16_enable,
  94. .disable = timer16_disable,
  95. .mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8),
  96. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  97. },
  98. };
  99. #define REG_CH 0
  100. #define REG_COMM 1
  101. static int __init h8300_16timer_init(struct device_node *node)
  102. {
  103. void __iomem *base[2];
  104. int ret, irq;
  105. unsigned int ch;
  106. struct clk *clk;
  107. clk = of_clk_get(node, 0);
  108. if (IS_ERR(clk)) {
  109. pr_err("failed to get clock for clocksource\n");
  110. return PTR_ERR(clk);
  111. }
  112. ret = -ENXIO;
  113. base[REG_CH] = of_iomap(node, 0);
  114. if (!base[REG_CH]) {
  115. pr_err("failed to map registers for clocksource\n");
  116. goto free_clk;
  117. }
  118. base[REG_COMM] = of_iomap(node, 1);
  119. if (!base[REG_COMM]) {
  120. pr_err("failed to map registers for clocksource\n");
  121. goto unmap_ch;
  122. }
  123. ret = -EINVAL;
  124. irq = irq_of_parse_and_map(node, 0);
  125. if (!irq) {
  126. pr_err("failed to get irq for clockevent\n");
  127. goto unmap_comm;
  128. }
  129. of_property_read_u32(node, "renesas,channel", &ch);
  130. timer16_priv.mapbase = base[REG_CH];
  131. timer16_priv.mapcommon = base[REG_COMM];
  132. timer16_priv.enb = ch;
  133. timer16_priv.ovf = ch;
  134. timer16_priv.ovie = 4 + ch;
  135. ret = request_irq(irq, timer16_interrupt,
  136. IRQF_TIMER, timer16_priv.cs.name, &timer16_priv);
  137. if (ret < 0) {
  138. pr_err("failed to request irq %d of clocksource\n", irq);
  139. goto unmap_comm;
  140. }
  141. clocksource_register_hz(&timer16_priv.cs,
  142. clk_get_rate(clk) / 8);
  143. return 0;
  144. unmap_comm:
  145. iounmap(base[REG_COMM]);
  146. unmap_ch:
  147. iounmap(base[REG_CH]);
  148. free_clk:
  149. clk_put(clk);
  150. return ret;
  151. }
  152. CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
  153. h8300_16timer_init);