ap806-system-controller.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187
  1. /*
  2. * Marvell Armada AP806 System Controller
  3. *
  4. * Copyright (C) 2016 Marvell
  5. *
  6. * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #define pr_fmt(fmt) "ap806-system-controller: " fmt
  13. #include <linux/clk-provider.h>
  14. #include <linux/mfd/syscon.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/of_address.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/regmap.h>
  20. #define AP806_SAR_REG 0x400
  21. #define AP806_SAR_CLKFREQ_MODE_MASK 0x1f
  22. #define AP806_CLK_NUM 4
  23. static struct clk *ap806_clks[AP806_CLK_NUM];
  24. static struct clk_onecell_data ap806_clk_data = {
  25. .clks = ap806_clks,
  26. .clk_num = AP806_CLK_NUM,
  27. };
  28. static int ap806_syscon_clk_probe(struct platform_device *pdev)
  29. {
  30. unsigned int freq_mode, cpuclk_freq;
  31. const char *name, *fixedclk_name;
  32. struct device_node *np = pdev->dev.of_node;
  33. struct regmap *regmap;
  34. u32 reg;
  35. int ret;
  36. regmap = syscon_node_to_regmap(np);
  37. if (IS_ERR(regmap)) {
  38. dev_err(&pdev->dev, "cannot get regmap\n");
  39. return PTR_ERR(regmap);
  40. }
  41. ret = regmap_read(regmap, AP806_SAR_REG, &reg);
  42. if (ret) {
  43. dev_err(&pdev->dev, "cannot read from regmap\n");
  44. return ret;
  45. }
  46. freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK;
  47. switch (freq_mode) {
  48. case 0x0:
  49. case 0x1:
  50. cpuclk_freq = 2000;
  51. break;
  52. case 0x6:
  53. case 0x7:
  54. cpuclk_freq = 1800;
  55. break;
  56. case 0x4:
  57. case 0xB:
  58. case 0xD:
  59. cpuclk_freq = 1600;
  60. break;
  61. case 0x1a:
  62. cpuclk_freq = 1400;
  63. break;
  64. case 0x14:
  65. case 0x17:
  66. cpuclk_freq = 1300;
  67. break;
  68. case 0x19:
  69. cpuclk_freq = 1200;
  70. break;
  71. case 0x13:
  72. case 0x1d:
  73. cpuclk_freq = 1000;
  74. break;
  75. case 0x1c:
  76. cpuclk_freq = 800;
  77. break;
  78. case 0x1b:
  79. cpuclk_freq = 600;
  80. break;
  81. default:
  82. dev_err(&pdev->dev, "invalid SAR value\n");
  83. return -EINVAL;
  84. }
  85. /* Convert to hertz */
  86. cpuclk_freq *= 1000 * 1000;
  87. /* CPU clocks depend on the Sample At Reset configuration */
  88. of_property_read_string_index(np, "clock-output-names",
  89. 0, &name);
  90. ap806_clks[0] = clk_register_fixed_rate(&pdev->dev, name, NULL,
  91. 0, cpuclk_freq);
  92. if (IS_ERR(ap806_clks[0])) {
  93. ret = PTR_ERR(ap806_clks[0]);
  94. goto fail0;
  95. }
  96. of_property_read_string_index(np, "clock-output-names",
  97. 1, &name);
  98. ap806_clks[1] = clk_register_fixed_rate(&pdev->dev, name, NULL, 0,
  99. cpuclk_freq);
  100. if (IS_ERR(ap806_clks[1])) {
  101. ret = PTR_ERR(ap806_clks[1]);
  102. goto fail1;
  103. }
  104. /* Fixed clock is always 1200 Mhz */
  105. of_property_read_string_index(np, "clock-output-names",
  106. 2, &fixedclk_name);
  107. ap806_clks[2] = clk_register_fixed_rate(&pdev->dev, fixedclk_name, NULL,
  108. 0, 1200 * 1000 * 1000);
  109. if (IS_ERR(ap806_clks[2])) {
  110. ret = PTR_ERR(ap806_clks[2]);
  111. goto fail2;
  112. }
  113. /* MSS Clock is fixed clock divided by 6 */
  114. of_property_read_string_index(np, "clock-output-names",
  115. 3, &name);
  116. ap806_clks[3] = clk_register_fixed_factor(NULL, name, fixedclk_name,
  117. 0, 1, 6);
  118. if (IS_ERR(ap806_clks[3])) {
  119. ret = PTR_ERR(ap806_clks[3]);
  120. goto fail3;
  121. }
  122. ret = of_clk_add_provider(np, of_clk_src_onecell_get, &ap806_clk_data);
  123. if (ret)
  124. goto fail_clk_add;
  125. return 0;
  126. fail_clk_add:
  127. clk_unregister_fixed_factor(ap806_clks[3]);
  128. fail3:
  129. clk_unregister_fixed_rate(ap806_clks[2]);
  130. fail2:
  131. clk_unregister_fixed_rate(ap806_clks[1]);
  132. fail1:
  133. clk_unregister_fixed_rate(ap806_clks[0]);
  134. fail0:
  135. return ret;
  136. }
  137. static int ap806_syscon_clk_remove(struct platform_device *pdev)
  138. {
  139. of_clk_del_provider(pdev->dev.of_node);
  140. clk_unregister_fixed_factor(ap806_clks[3]);
  141. clk_unregister_fixed_rate(ap806_clks[2]);
  142. clk_unregister_fixed_rate(ap806_clks[1]);
  143. clk_unregister_fixed_rate(ap806_clks[0]);
  144. return 0;
  145. }
  146. static const struct of_device_id ap806_syscon_of_match[] = {
  147. { .compatible = "marvell,ap806-system-controller", },
  148. { }
  149. };
  150. MODULE_DEVICE_TABLE(of, armada8k_pcie_of_match);
  151. static struct platform_driver ap806_syscon_driver = {
  152. .probe = ap806_syscon_clk_probe,
  153. .remove = ap806_syscon_clk_remove,
  154. .driver = {
  155. .name = "marvell-ap806-system-controller",
  156. .of_match_table = ap806_syscon_of_match,
  157. },
  158. };
  159. module_platform_driver(ap806_syscon_driver);
  160. MODULE_DESCRIPTION("Marvell AP806 System Controller driver");
  161. MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
  162. MODULE_LICENSE("GPL");