fsl_lbc.c 10 KB

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  1. /*
  2. * Freescale LBC and UPM routines.
  3. *
  4. * Copyright © 2007-2008 MontaVista Software, Inc.
  5. * Copyright © 2010 Freescale Semiconductor
  6. *
  7. * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
  8. * Author: Jack Lan <Jack.Lan@freescale.com>
  9. * Author: Roy Zang <tie-fei.zang@freescale.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/export.h>
  18. #include <linux/kernel.h>
  19. #include <linux/compiler.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/types.h>
  22. #include <linux/io.h>
  23. #include <linux/of.h>
  24. #include <linux/slab.h>
  25. #include <linux/sched.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/mod_devicetable.h>
  29. #include <linux/syscore_ops.h>
  30. #include <asm/prom.h>
  31. #include <asm/fsl_lbc.h>
  32. static spinlock_t fsl_lbc_lock = __SPIN_LOCK_UNLOCKED(fsl_lbc_lock);
  33. struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
  34. EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
  35. /**
  36. * fsl_lbc_addr - convert the base address
  37. * @addr_base: base address of the memory bank
  38. *
  39. * This function converts a base address of lbc into the right format for the
  40. * BR register. If the SOC has eLBC then it returns 32bit physical address
  41. * else it convers a 34bit local bus physical address to correct format of
  42. * 32bit address for BR register (Example: MPC8641).
  43. */
  44. u32 fsl_lbc_addr(phys_addr_t addr_base)
  45. {
  46. struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
  47. u32 addr = addr_base & 0xffff8000;
  48. if (of_device_is_compatible(np, "fsl,elbc"))
  49. return addr;
  50. return addr | ((addr_base & 0x300000000ull) >> 19);
  51. }
  52. EXPORT_SYMBOL(fsl_lbc_addr);
  53. /**
  54. * fsl_lbc_find - find Localbus bank
  55. * @addr_base: base address of the memory bank
  56. *
  57. * This function walks LBC banks comparing "Base address" field of the BR
  58. * registers with the supplied addr_base argument. When bases match this
  59. * function returns bank number (starting with 0), otherwise it returns
  60. * appropriate errno value.
  61. */
  62. int fsl_lbc_find(phys_addr_t addr_base)
  63. {
  64. int i;
  65. struct fsl_lbc_regs __iomem *lbc;
  66. if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
  67. return -ENODEV;
  68. lbc = fsl_lbc_ctrl_dev->regs;
  69. for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
  70. u32 br = in_be32(&lbc->bank[i].br);
  71. u32 or = in_be32(&lbc->bank[i].or);
  72. if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
  73. return i;
  74. }
  75. return -ENOENT;
  76. }
  77. EXPORT_SYMBOL(fsl_lbc_find);
  78. /**
  79. * fsl_upm_find - find pre-programmed UPM via base address
  80. * @addr_base: base address of the memory bank controlled by the UPM
  81. * @upm: pointer to the allocated fsl_upm structure
  82. *
  83. * This function fills fsl_upm structure so you can use it with the rest of
  84. * UPM API. On success this function returns 0, otherwise it returns
  85. * appropriate errno value.
  86. */
  87. int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
  88. {
  89. int bank;
  90. u32 br;
  91. struct fsl_lbc_regs __iomem *lbc;
  92. bank = fsl_lbc_find(addr_base);
  93. if (bank < 0)
  94. return bank;
  95. if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
  96. return -ENODEV;
  97. lbc = fsl_lbc_ctrl_dev->regs;
  98. br = in_be32(&lbc->bank[bank].br);
  99. switch (br & BR_MSEL) {
  100. case BR_MS_UPMA:
  101. upm->mxmr = &lbc->mamr;
  102. break;
  103. case BR_MS_UPMB:
  104. upm->mxmr = &lbc->mbmr;
  105. break;
  106. case BR_MS_UPMC:
  107. upm->mxmr = &lbc->mcmr;
  108. break;
  109. default:
  110. return -EINVAL;
  111. }
  112. switch (br & BR_PS) {
  113. case BR_PS_8:
  114. upm->width = 8;
  115. break;
  116. case BR_PS_16:
  117. upm->width = 16;
  118. break;
  119. case BR_PS_32:
  120. upm->width = 32;
  121. break;
  122. default:
  123. return -EINVAL;
  124. }
  125. return 0;
  126. }
  127. EXPORT_SYMBOL(fsl_upm_find);
  128. /**
  129. * fsl_upm_run_pattern - actually run an UPM pattern
  130. * @upm: pointer to the fsl_upm structure obtained via fsl_upm_find
  131. * @io_base: remapped pointer to where memory access should happen
  132. * @mar: MAR register content during pattern execution
  133. *
  134. * This function triggers dummy write to the memory specified by the io_base,
  135. * thus UPM pattern actually executed. Note that mar usage depends on the
  136. * pre-programmed AMX bits in the UPM RAM.
  137. */
  138. int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
  139. {
  140. int ret = 0;
  141. unsigned long flags;
  142. if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
  143. return -ENODEV;
  144. spin_lock_irqsave(&fsl_lbc_lock, flags);
  145. out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
  146. switch (upm->width) {
  147. case 8:
  148. out_8(io_base, 0x0);
  149. break;
  150. case 16:
  151. out_be16(io_base, 0x0);
  152. break;
  153. case 32:
  154. out_be32(io_base, 0x0);
  155. break;
  156. default:
  157. ret = -EINVAL;
  158. break;
  159. }
  160. spin_unlock_irqrestore(&fsl_lbc_lock, flags);
  161. return ret;
  162. }
  163. EXPORT_SYMBOL(fsl_upm_run_pattern);
  164. static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
  165. struct device_node *node)
  166. {
  167. struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
  168. /* clear event registers */
  169. setbits32(&lbc->ltesr, LTESR_CLEAR);
  170. out_be32(&lbc->lteatr, 0);
  171. out_be32(&lbc->ltear, 0);
  172. out_be32(&lbc->lteccr, LTECCR_CLEAR);
  173. out_be32(&lbc->ltedr, LTEDR_ENABLE);
  174. /* Set the monitor timeout value to the maximum for erratum A001 */
  175. if (of_device_is_compatible(node, "fsl,elbc"))
  176. clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
  177. return 0;
  178. }
  179. /*
  180. * NOTE: This interrupt is used to report localbus events of various kinds,
  181. * such as transaction errors on the chipselects.
  182. */
  183. static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
  184. {
  185. struct fsl_lbc_ctrl *ctrl = data;
  186. struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
  187. u32 status;
  188. unsigned long flags;
  189. spin_lock_irqsave(&fsl_lbc_lock, flags);
  190. status = in_be32(&lbc->ltesr);
  191. if (!status) {
  192. spin_unlock_irqrestore(&fsl_lbc_lock, flags);
  193. return IRQ_NONE;
  194. }
  195. out_be32(&lbc->ltesr, LTESR_CLEAR);
  196. out_be32(&lbc->lteatr, 0);
  197. out_be32(&lbc->ltear, 0);
  198. ctrl->irq_status = status;
  199. if (status & LTESR_BM)
  200. dev_err(ctrl->dev, "Local bus monitor time-out: "
  201. "LTESR 0x%08X\n", status);
  202. if (status & LTESR_WP)
  203. dev_err(ctrl->dev, "Write protect error: "
  204. "LTESR 0x%08X\n", status);
  205. if (status & LTESR_ATMW)
  206. dev_err(ctrl->dev, "Atomic write error: "
  207. "LTESR 0x%08X\n", status);
  208. if (status & LTESR_ATMR)
  209. dev_err(ctrl->dev, "Atomic read error: "
  210. "LTESR 0x%08X\n", status);
  211. if (status & LTESR_CS)
  212. dev_err(ctrl->dev, "Chip select error: "
  213. "LTESR 0x%08X\n", status);
  214. if (status & LTESR_FCT) {
  215. dev_err(ctrl->dev, "FCM command time-out: "
  216. "LTESR 0x%08X\n", status);
  217. smp_wmb();
  218. wake_up(&ctrl->irq_wait);
  219. }
  220. if (status & LTESR_PAR) {
  221. dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
  222. "LTESR 0x%08X\n", status);
  223. smp_wmb();
  224. wake_up(&ctrl->irq_wait);
  225. }
  226. if (status & LTESR_CC) {
  227. smp_wmb();
  228. wake_up(&ctrl->irq_wait);
  229. }
  230. if (status & ~LTESR_MASK)
  231. dev_err(ctrl->dev, "Unknown error: "
  232. "LTESR 0x%08X\n", status);
  233. spin_unlock_irqrestore(&fsl_lbc_lock, flags);
  234. return IRQ_HANDLED;
  235. }
  236. /*
  237. * fsl_lbc_ctrl_probe
  238. *
  239. * called by device layer when it finds a device matching
  240. * one our driver can handled. This code allocates all of
  241. * the resources needed for the controller only. The
  242. * resources for the NAND banks themselves are allocated
  243. * in the chip probe function.
  244. */
  245. static int fsl_lbc_ctrl_probe(struct platform_device *dev)
  246. {
  247. int ret;
  248. if (!dev->dev.of_node) {
  249. dev_err(&dev->dev, "Device OF-Node is NULL");
  250. return -EFAULT;
  251. }
  252. fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
  253. if (!fsl_lbc_ctrl_dev)
  254. return -ENOMEM;
  255. dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
  256. spin_lock_init(&fsl_lbc_ctrl_dev->lock);
  257. init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
  258. fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
  259. if (!fsl_lbc_ctrl_dev->regs) {
  260. dev_err(&dev->dev, "failed to get memory region\n");
  261. ret = -ENODEV;
  262. goto err;
  263. }
  264. fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
  265. if (!fsl_lbc_ctrl_dev->irq[0]) {
  266. dev_err(&dev->dev, "failed to get irq resource\n");
  267. ret = -ENODEV;
  268. goto err;
  269. }
  270. fsl_lbc_ctrl_dev->dev = &dev->dev;
  271. ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
  272. if (ret < 0)
  273. goto err;
  274. ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
  275. "fsl-lbc", fsl_lbc_ctrl_dev);
  276. if (ret != 0) {
  277. dev_err(&dev->dev, "failed to install irq (%d)\n",
  278. fsl_lbc_ctrl_dev->irq[0]);
  279. ret = fsl_lbc_ctrl_dev->irq[0];
  280. goto err;
  281. }
  282. fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
  283. if (fsl_lbc_ctrl_dev->irq[1]) {
  284. ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
  285. IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
  286. if (ret) {
  287. dev_err(&dev->dev, "failed to install irq (%d)\n",
  288. fsl_lbc_ctrl_dev->irq[1]);
  289. ret = fsl_lbc_ctrl_dev->irq[1];
  290. goto err1;
  291. }
  292. }
  293. /* Enable interrupts for any detected events */
  294. out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
  295. return 0;
  296. err1:
  297. free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
  298. err:
  299. iounmap(fsl_lbc_ctrl_dev->regs);
  300. kfree(fsl_lbc_ctrl_dev);
  301. fsl_lbc_ctrl_dev = NULL;
  302. return ret;
  303. }
  304. #ifdef CONFIG_SUSPEND
  305. /* save lbc registers */
  306. static int fsl_lbc_syscore_suspend(void)
  307. {
  308. struct fsl_lbc_ctrl *ctrl;
  309. struct fsl_lbc_regs __iomem *lbc;
  310. ctrl = fsl_lbc_ctrl_dev;
  311. if (!ctrl)
  312. goto out;
  313. lbc = ctrl->regs;
  314. if (!lbc)
  315. goto out;
  316. ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
  317. if (!ctrl->saved_regs)
  318. return -ENOMEM;
  319. _memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
  320. out:
  321. return 0;
  322. }
  323. /* restore lbc registers */
  324. static void fsl_lbc_syscore_resume(void)
  325. {
  326. struct fsl_lbc_ctrl *ctrl;
  327. struct fsl_lbc_regs __iomem *lbc;
  328. ctrl = fsl_lbc_ctrl_dev;
  329. if (!ctrl)
  330. goto out;
  331. lbc = ctrl->regs;
  332. if (!lbc)
  333. goto out;
  334. if (ctrl->saved_regs) {
  335. _memcpy_toio(lbc, ctrl->saved_regs,
  336. sizeof(struct fsl_lbc_regs));
  337. kfree(ctrl->saved_regs);
  338. ctrl->saved_regs = NULL;
  339. }
  340. out:
  341. return;
  342. }
  343. #endif /* CONFIG_SUSPEND */
  344. static const struct of_device_id fsl_lbc_match[] = {
  345. { .compatible = "fsl,elbc", },
  346. { .compatible = "fsl,pq3-localbus", },
  347. { .compatible = "fsl,pq2-localbus", },
  348. { .compatible = "fsl,pq2pro-localbus", },
  349. {},
  350. };
  351. #ifdef CONFIG_SUSPEND
  352. static struct syscore_ops lbc_syscore_pm_ops = {
  353. .suspend = fsl_lbc_syscore_suspend,
  354. .resume = fsl_lbc_syscore_resume,
  355. };
  356. #endif
  357. static struct platform_driver fsl_lbc_ctrl_driver = {
  358. .driver = {
  359. .name = "fsl-lbc",
  360. .of_match_table = fsl_lbc_match,
  361. },
  362. .probe = fsl_lbc_ctrl_probe,
  363. };
  364. static int __init fsl_lbc_init(void)
  365. {
  366. #ifdef CONFIG_SUSPEND
  367. register_syscore_ops(&lbc_syscore_pm_ops);
  368. #endif
  369. return platform_driver_register(&fsl_lbc_ctrl_driver);
  370. }
  371. subsys_initcall(fsl_lbc_init);