spu.c 15 KB

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  1. /*
  2. * PS3 Platform spu routines.
  3. *
  4. * Copyright (C) 2006 Sony Computer Entertainment Inc.
  5. * Copyright 2006 Sony Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; version 2 of the License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/slab.h>
  23. #include <linux/mmzone.h>
  24. #include <linux/export.h>
  25. #include <linux/io.h>
  26. #include <linux/mm.h>
  27. #include <asm/spu.h>
  28. #include <asm/spu_priv1.h>
  29. #include <asm/lv1call.h>
  30. #include <asm/ps3.h>
  31. #include "../cell/spufs/spufs.h"
  32. #include "platform.h"
  33. /* spu_management_ops */
  34. /**
  35. * enum spe_type - Type of spe to create.
  36. * @spe_type_logical: Standard logical spe.
  37. *
  38. * For use with lv1_construct_logical_spe(). The current HV does not support
  39. * any types other than those listed.
  40. */
  41. enum spe_type {
  42. SPE_TYPE_LOGICAL = 0,
  43. };
  44. /**
  45. * struct spe_shadow - logical spe shadow register area.
  46. *
  47. * Read-only shadow of spe registers.
  48. */
  49. struct spe_shadow {
  50. u8 padding_0140[0x0140];
  51. u64 int_status_class0_RW; /* 0x0140 */
  52. u64 int_status_class1_RW; /* 0x0148 */
  53. u64 int_status_class2_RW; /* 0x0150 */
  54. u8 padding_0158[0x0610-0x0158];
  55. u64 mfc_dsisr_RW; /* 0x0610 */
  56. u8 padding_0618[0x0620-0x0618];
  57. u64 mfc_dar_RW; /* 0x0620 */
  58. u8 padding_0628[0x0800-0x0628];
  59. u64 mfc_dsipr_R; /* 0x0800 */
  60. u8 padding_0808[0x0810-0x0808];
  61. u64 mfc_lscrr_R; /* 0x0810 */
  62. u8 padding_0818[0x0c00-0x0818];
  63. u64 mfc_cer_R; /* 0x0c00 */
  64. u8 padding_0c08[0x0f00-0x0c08];
  65. u64 spe_execution_status; /* 0x0f00 */
  66. u8 padding_0f08[0x1000-0x0f08];
  67. };
  68. /**
  69. * enum spe_ex_state - Logical spe execution state.
  70. * @spe_ex_state_unexecutable: Uninitialized.
  71. * @spe_ex_state_executable: Enabled, not ready.
  72. * @spe_ex_state_executed: Ready for use.
  73. *
  74. * The execution state (status) of the logical spe as reported in
  75. * struct spe_shadow:spe_execution_status.
  76. */
  77. enum spe_ex_state {
  78. SPE_EX_STATE_UNEXECUTABLE = 0,
  79. SPE_EX_STATE_EXECUTABLE = 2,
  80. SPE_EX_STATE_EXECUTED = 3,
  81. };
  82. /**
  83. * struct priv1_cache - Cached values of priv1 registers.
  84. * @masks[]: Array of cached spe interrupt masks, indexed by class.
  85. * @sr1: Cached mfc_sr1 register.
  86. * @tclass_id: Cached mfc_tclass_id register.
  87. */
  88. struct priv1_cache {
  89. u64 masks[3];
  90. u64 sr1;
  91. u64 tclass_id;
  92. };
  93. /**
  94. * struct spu_pdata - Platform state variables.
  95. * @spe_id: HV spe id returned by lv1_construct_logical_spe().
  96. * @resource_id: HV spe resource id returned by
  97. * ps3_repository_read_spe_resource_id().
  98. * @priv2_addr: lpar address of spe priv2 area returned by
  99. * lv1_construct_logical_spe().
  100. * @shadow_addr: lpar address of spe register shadow area returned by
  101. * lv1_construct_logical_spe().
  102. * @shadow: Virtual (ioremap) address of spe register shadow area.
  103. * @cache: Cached values of priv1 registers.
  104. */
  105. struct spu_pdata {
  106. u64 spe_id;
  107. u64 resource_id;
  108. u64 priv2_addr;
  109. u64 shadow_addr;
  110. struct spe_shadow __iomem *shadow;
  111. struct priv1_cache cache;
  112. };
  113. static struct spu_pdata *spu_pdata(struct spu *spu)
  114. {
  115. return spu->pdata;
  116. }
  117. #define dump_areas(_a, _b, _c, _d, _e) \
  118. _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
  119. static void _dump_areas(unsigned int spe_id, unsigned long priv2,
  120. unsigned long problem, unsigned long ls, unsigned long shadow,
  121. const char* func, int line)
  122. {
  123. pr_debug("%s:%d: spe_id: %xh (%u)\n", func, line, spe_id, spe_id);
  124. pr_debug("%s:%d: priv2: %lxh\n", func, line, priv2);
  125. pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
  126. pr_debug("%s:%d: ls: %lxh\n", func, line, ls);
  127. pr_debug("%s:%d: shadow: %lxh\n", func, line, shadow);
  128. }
  129. u64 ps3_get_spe_id(void *arg)
  130. {
  131. return spu_pdata(arg)->spe_id;
  132. }
  133. EXPORT_SYMBOL_GPL(ps3_get_spe_id);
  134. static unsigned long get_vas_id(void)
  135. {
  136. u64 id;
  137. lv1_get_logical_ppe_id(&id);
  138. lv1_get_virtual_address_space_id_of_ppe(&id);
  139. return id;
  140. }
  141. static int __init construct_spu(struct spu *spu)
  142. {
  143. int result;
  144. u64 unused;
  145. u64 problem_phys;
  146. u64 local_store_phys;
  147. result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
  148. PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
  149. &spu_pdata(spu)->priv2_addr, &problem_phys,
  150. &local_store_phys, &unused,
  151. &spu_pdata(spu)->shadow_addr,
  152. &spu_pdata(spu)->spe_id);
  153. spu->problem_phys = problem_phys;
  154. spu->local_store_phys = local_store_phys;
  155. if (result) {
  156. pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
  157. __func__, __LINE__, ps3_result(result));
  158. return result;
  159. }
  160. return result;
  161. }
  162. static void spu_unmap(struct spu *spu)
  163. {
  164. iounmap(spu->priv2);
  165. iounmap(spu->problem);
  166. iounmap((__force u8 __iomem *)spu->local_store);
  167. iounmap(spu_pdata(spu)->shadow);
  168. }
  169. /**
  170. * setup_areas - Map the spu regions into the address space.
  171. *
  172. * The current HV requires the spu shadow regs to be mapped with the
  173. * PTE page protection bits set as read-only (PP=3). This implementation
  174. * uses the low level __ioremap() to bypass the page protection settings
  175. * inforced by ioremap_prot() to get the needed PTE bits set for the
  176. * shadow regs.
  177. */
  178. static int __init setup_areas(struct spu *spu)
  179. {
  180. struct table {char* name; unsigned long addr; unsigned long size;};
  181. unsigned long shadow_flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL_RO));
  182. spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
  183. sizeof(struct spe_shadow),
  184. shadow_flags);
  185. if (!spu_pdata(spu)->shadow) {
  186. pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
  187. goto fail_ioremap;
  188. }
  189. spu->local_store = (__force void *)ioremap_prot(spu->local_store_phys,
  190. LS_SIZE, pgprot_val(pgprot_noncached_wc(__pgprot(0))));
  191. if (!spu->local_store) {
  192. pr_debug("%s:%d: ioremap local_store failed\n",
  193. __func__, __LINE__);
  194. goto fail_ioremap;
  195. }
  196. spu->problem = ioremap(spu->problem_phys,
  197. sizeof(struct spu_problem));
  198. if (!spu->problem) {
  199. pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
  200. goto fail_ioremap;
  201. }
  202. spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
  203. sizeof(struct spu_priv2));
  204. if (!spu->priv2) {
  205. pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
  206. goto fail_ioremap;
  207. }
  208. dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
  209. spu->problem_phys, spu->local_store_phys,
  210. spu_pdata(spu)->shadow_addr);
  211. dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
  212. (unsigned long)spu->problem, (unsigned long)spu->local_store,
  213. (unsigned long)spu_pdata(spu)->shadow);
  214. return 0;
  215. fail_ioremap:
  216. spu_unmap(spu);
  217. return -ENOMEM;
  218. }
  219. static int __init setup_interrupts(struct spu *spu)
  220. {
  221. int result;
  222. result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
  223. 0, &spu->irqs[0]);
  224. if (result)
  225. goto fail_alloc_0;
  226. result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
  227. 1, &spu->irqs[1]);
  228. if (result)
  229. goto fail_alloc_1;
  230. result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
  231. 2, &spu->irqs[2]);
  232. if (result)
  233. goto fail_alloc_2;
  234. return result;
  235. fail_alloc_2:
  236. ps3_spe_irq_destroy(spu->irqs[1]);
  237. fail_alloc_1:
  238. ps3_spe_irq_destroy(spu->irqs[0]);
  239. fail_alloc_0:
  240. spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
  241. return result;
  242. }
  243. static int __init enable_spu(struct spu *spu)
  244. {
  245. int result;
  246. result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
  247. spu_pdata(spu)->resource_id);
  248. if (result) {
  249. pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
  250. __func__, __LINE__, ps3_result(result));
  251. goto fail_enable;
  252. }
  253. result = setup_areas(spu);
  254. if (result)
  255. goto fail_areas;
  256. result = setup_interrupts(spu);
  257. if (result)
  258. goto fail_interrupts;
  259. return 0;
  260. fail_interrupts:
  261. spu_unmap(spu);
  262. fail_areas:
  263. lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
  264. fail_enable:
  265. return result;
  266. }
  267. static int ps3_destroy_spu(struct spu *spu)
  268. {
  269. int result;
  270. pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
  271. result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
  272. BUG_ON(result);
  273. ps3_spe_irq_destroy(spu->irqs[2]);
  274. ps3_spe_irq_destroy(spu->irqs[1]);
  275. ps3_spe_irq_destroy(spu->irqs[0]);
  276. spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
  277. spu_unmap(spu);
  278. result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
  279. BUG_ON(result);
  280. kfree(spu->pdata);
  281. spu->pdata = NULL;
  282. return 0;
  283. }
  284. static int __init ps3_create_spu(struct spu *spu, void *data)
  285. {
  286. int result;
  287. pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
  288. spu->pdata = kzalloc(sizeof(struct spu_pdata),
  289. GFP_KERNEL);
  290. if (!spu->pdata) {
  291. result = -ENOMEM;
  292. goto fail_malloc;
  293. }
  294. spu_pdata(spu)->resource_id = (unsigned long)data;
  295. /* Init cached reg values to HV defaults. */
  296. spu_pdata(spu)->cache.sr1 = 0x33;
  297. result = construct_spu(spu);
  298. if (result)
  299. goto fail_construct;
  300. /* For now, just go ahead and enable it. */
  301. result = enable_spu(spu);
  302. if (result)
  303. goto fail_enable;
  304. /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
  305. /* need something better here!!! */
  306. while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
  307. != SPE_EX_STATE_EXECUTED)
  308. (void)0;
  309. return result;
  310. fail_enable:
  311. fail_construct:
  312. ps3_destroy_spu(spu);
  313. fail_malloc:
  314. return result;
  315. }
  316. static int __init ps3_enumerate_spus(int (*fn)(void *data))
  317. {
  318. int result;
  319. unsigned int num_resource_id;
  320. unsigned int i;
  321. result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
  322. pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
  323. num_resource_id);
  324. /*
  325. * For now, just create logical spus equal to the number
  326. * of physical spus reserved for the partition.
  327. */
  328. for (i = 0; i < num_resource_id; i++) {
  329. enum ps3_spu_resource_type resource_type;
  330. unsigned int resource_id;
  331. result = ps3_repository_read_spu_resource_id(i,
  332. &resource_type, &resource_id);
  333. if (result)
  334. break;
  335. if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
  336. result = fn((void*)(unsigned long)resource_id);
  337. if (result)
  338. break;
  339. }
  340. }
  341. if (result) {
  342. printk(KERN_WARNING "%s:%d: Error initializing spus\n",
  343. __func__, __LINE__);
  344. return result;
  345. }
  346. return num_resource_id;
  347. }
  348. static int ps3_init_affinity(void)
  349. {
  350. return 0;
  351. }
  352. /**
  353. * ps3_enable_spu - Enable SPU run control.
  354. *
  355. * An outstanding enhancement for the PS3 would be to add a guard to check
  356. * for incorrect access to the spu problem state when the spu context is
  357. * disabled. This check could be implemented with a flag added to the spu
  358. * context that would inhibit mapping problem state pages, and a routine
  359. * to unmap spu problem state pages. When the spu is enabled with
  360. * ps3_enable_spu() the flag would be set allowing pages to be mapped,
  361. * and when the spu is disabled with ps3_disable_spu() the flag would be
  362. * cleared and the mapped problem state pages would be unmapped.
  363. */
  364. static void ps3_enable_spu(struct spu_context *ctx)
  365. {
  366. }
  367. static void ps3_disable_spu(struct spu_context *ctx)
  368. {
  369. ctx->ops->runcntl_stop(ctx);
  370. }
  371. const struct spu_management_ops spu_management_ps3_ops = {
  372. .enumerate_spus = ps3_enumerate_spus,
  373. .create_spu = ps3_create_spu,
  374. .destroy_spu = ps3_destroy_spu,
  375. .enable_spu = ps3_enable_spu,
  376. .disable_spu = ps3_disable_spu,
  377. .init_affinity = ps3_init_affinity,
  378. };
  379. /* spu_priv1_ops */
  380. static void int_mask_and(struct spu *spu, int class, u64 mask)
  381. {
  382. u64 old_mask;
  383. /* are these serialized by caller??? */
  384. old_mask = spu_int_mask_get(spu, class);
  385. spu_int_mask_set(spu, class, old_mask & mask);
  386. }
  387. static void int_mask_or(struct spu *spu, int class, u64 mask)
  388. {
  389. u64 old_mask;
  390. old_mask = spu_int_mask_get(spu, class);
  391. spu_int_mask_set(spu, class, old_mask | mask);
  392. }
  393. static void int_mask_set(struct spu *spu, int class, u64 mask)
  394. {
  395. spu_pdata(spu)->cache.masks[class] = mask;
  396. lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
  397. spu_pdata(spu)->cache.masks[class]);
  398. }
  399. static u64 int_mask_get(struct spu *spu, int class)
  400. {
  401. return spu_pdata(spu)->cache.masks[class];
  402. }
  403. static void int_stat_clear(struct spu *spu, int class, u64 stat)
  404. {
  405. /* Note that MFC_DSISR will be cleared when class1[MF] is set. */
  406. lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
  407. stat, 0);
  408. }
  409. static u64 int_stat_get(struct spu *spu, int class)
  410. {
  411. u64 stat;
  412. lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
  413. return stat;
  414. }
  415. static void cpu_affinity_set(struct spu *spu, int cpu)
  416. {
  417. /* No support. */
  418. }
  419. static u64 mfc_dar_get(struct spu *spu)
  420. {
  421. return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
  422. }
  423. static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
  424. {
  425. /* Nothing to do, cleared in int_stat_clear(). */
  426. }
  427. static u64 mfc_dsisr_get(struct spu *spu)
  428. {
  429. return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
  430. }
  431. static void mfc_sdr_setup(struct spu *spu)
  432. {
  433. /* Nothing to do. */
  434. }
  435. static void mfc_sr1_set(struct spu *spu, u64 sr1)
  436. {
  437. /* Check bits allowed by HV. */
  438. static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
  439. | MFC_STATE1_PROBLEM_STATE_MASK);
  440. BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
  441. spu_pdata(spu)->cache.sr1 = sr1;
  442. lv1_set_spe_privilege_state_area_1_register(
  443. spu_pdata(spu)->spe_id,
  444. offsetof(struct spu_priv1, mfc_sr1_RW),
  445. spu_pdata(spu)->cache.sr1);
  446. }
  447. static u64 mfc_sr1_get(struct spu *spu)
  448. {
  449. return spu_pdata(spu)->cache.sr1;
  450. }
  451. static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
  452. {
  453. spu_pdata(spu)->cache.tclass_id = tclass_id;
  454. lv1_set_spe_privilege_state_area_1_register(
  455. spu_pdata(spu)->spe_id,
  456. offsetof(struct spu_priv1, mfc_tclass_id_RW),
  457. spu_pdata(spu)->cache.tclass_id);
  458. }
  459. static u64 mfc_tclass_id_get(struct spu *spu)
  460. {
  461. return spu_pdata(spu)->cache.tclass_id;
  462. }
  463. static void tlb_invalidate(struct spu *spu)
  464. {
  465. /* Nothing to do. */
  466. }
  467. static void resource_allocation_groupID_set(struct spu *spu, u64 id)
  468. {
  469. /* No support. */
  470. }
  471. static u64 resource_allocation_groupID_get(struct spu *spu)
  472. {
  473. return 0; /* No support. */
  474. }
  475. static void resource_allocation_enable_set(struct spu *spu, u64 enable)
  476. {
  477. /* No support. */
  478. }
  479. static u64 resource_allocation_enable_get(struct spu *spu)
  480. {
  481. return 0; /* No support. */
  482. }
  483. const struct spu_priv1_ops spu_priv1_ps3_ops = {
  484. .int_mask_and = int_mask_and,
  485. .int_mask_or = int_mask_or,
  486. .int_mask_set = int_mask_set,
  487. .int_mask_get = int_mask_get,
  488. .int_stat_clear = int_stat_clear,
  489. .int_stat_get = int_stat_get,
  490. .cpu_affinity_set = cpu_affinity_set,
  491. .mfc_dar_get = mfc_dar_get,
  492. .mfc_dsisr_set = mfc_dsisr_set,
  493. .mfc_dsisr_get = mfc_dsisr_get,
  494. .mfc_sdr_setup = mfc_sdr_setup,
  495. .mfc_sr1_set = mfc_sr1_set,
  496. .mfc_sr1_get = mfc_sr1_get,
  497. .mfc_tclass_id_set = mfc_tclass_id_set,
  498. .mfc_tclass_id_get = mfc_tclass_id_get,
  499. .tlb_invalidate = tlb_invalidate,
  500. .resource_allocation_groupID_set = resource_allocation_groupID_set,
  501. .resource_allocation_groupID_get = resource_allocation_groupID_get,
  502. .resource_allocation_enable_set = resource_allocation_enable_set,
  503. .resource_allocation_enable_get = resource_allocation_enable_get,
  504. };
  505. void ps3_spu_set_platform(void)
  506. {
  507. spu_priv1_ops = &spu_priv1_ps3_ops;
  508. spu_management_ops = &spu_management_ps3_ops;
  509. }