twr_p102x.c 3.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146
  1. /*
  2. * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  3. *
  4. * Author: Michael Johnston <michael.johnston@freescale.com>
  5. *
  6. * Description:
  7. * TWR-P102x Board Setup
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/fsl/guts.h>
  18. #include <linux/pci.h>
  19. #include <linux/of_platform.h>
  20. #include <asm/pci-bridge.h>
  21. #include <asm/udbg.h>
  22. #include <asm/mpic.h>
  23. #include <soc/fsl/qe/qe.h>
  24. #include <soc/fsl/qe/qe_ic.h>
  25. #include <sysdev/fsl_soc.h>
  26. #include <sysdev/fsl_pci.h>
  27. #include "smp.h"
  28. #include "mpc85xx.h"
  29. static void __init twr_p1025_pic_init(void)
  30. {
  31. struct mpic *mpic;
  32. #ifdef CONFIG_QUICC_ENGINE
  33. struct device_node *np;
  34. #endif
  35. mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
  36. MPIC_SINGLE_DEST_CPU,
  37. 0, 256, " OpenPIC ");
  38. BUG_ON(mpic == NULL);
  39. mpic_init(mpic);
  40. #ifdef CONFIG_QUICC_ENGINE
  41. np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
  42. if (np) {
  43. qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
  44. qe_ic_cascade_high_mpic);
  45. of_node_put(np);
  46. } else
  47. pr_err("Could not find qe-ic node\n");
  48. #endif
  49. }
  50. /* ************************************************************************
  51. *
  52. * Setup the architecture
  53. *
  54. */
  55. static void __init twr_p1025_setup_arch(void)
  56. {
  57. #ifdef CONFIG_QUICC_ENGINE
  58. struct device_node *np;
  59. #endif
  60. if (ppc_md.progress)
  61. ppc_md.progress("twr_p1025_setup_arch()", 0);
  62. mpc85xx_smp_init();
  63. fsl_pci_assign_primary();
  64. #ifdef CONFIG_QUICC_ENGINE
  65. mpc85xx_qe_init();
  66. mpc85xx_qe_par_io_init();
  67. #if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
  68. if (machine_is(twr_p1025)) {
  69. struct ccsr_guts __iomem *guts;
  70. np = of_find_compatible_node(NULL, NULL, "fsl,p1021-guts");
  71. if (np) {
  72. guts = of_iomap(np, 0);
  73. if (!guts)
  74. pr_err("twr_p1025: could not map global utilities register\n");
  75. else {
  76. /* P1025 has pins muxed for QE and other functions. To
  77. * enable QE UEC mode, we need to set bit QE0 for UCC1
  78. * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
  79. * and QE12 for QE MII management signals in PMUXCR
  80. * register.
  81. * Set QE mux bits in PMUXCR */
  82. setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
  83. MPC85xx_PMUXCR_QE(3) |
  84. MPC85xx_PMUXCR_QE(9) |
  85. MPC85xx_PMUXCR_QE(12));
  86. iounmap(guts);
  87. #if IS_ENABLED(CONFIG_SERIAL_QE)
  88. /* On P1025TWR board, the UCC7 acted as UART port.
  89. * However, The UCC7's CTS pin is low level in default,
  90. * it will impact the transmission in full duplex
  91. * communication. So disable the Flow control pin PA18.
  92. * The UCC7 UART just can use RXD and TXD pins.
  93. */
  94. par_io_config_pin(0, 18, 0, 0, 0, 0);
  95. #endif
  96. /* Drive PB29 to CPLD low - CPLD will then change
  97. * muxing from LBC to QE */
  98. par_io_config_pin(1, 29, 1, 0, 0, 0);
  99. par_io_data_set(1, 29, 0);
  100. }
  101. of_node_put(np);
  102. }
  103. }
  104. #endif
  105. #endif /* CONFIG_QUICC_ENGINE */
  106. pr_info("TWR-P1025 board from Freescale Semiconductor\n");
  107. }
  108. machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
  109. static int __init twr_p1025_probe(void)
  110. {
  111. return of_machine_is_compatible("fsl,TWR-P1025");
  112. }
  113. define_machine(twr_p1025) {
  114. .name = "TWR-P1025",
  115. .probe = twr_p1025_probe,
  116. .setup_arch = twr_p1025_setup_arch,
  117. .init_IRQ = twr_p1025_pic_init,
  118. #ifdef CONFIG_PCI
  119. .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
  120. #endif
  121. .get_irq = mpic_get_irq,
  122. .calibrate_decr = generic_calibrate_decr,
  123. .progress = udbg_progress,
  124. };