suspend.c 9.0 KB

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  1. /*
  2. * MPC83xx suspend support
  3. *
  4. * Author: Scott Wood <scottwood@freescale.com>
  5. *
  6. * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License version 2 as published
  10. * by the Free Software Foundation.
  11. */
  12. #include <linux/pm.h>
  13. #include <linux/types.h>
  14. #include <linux/ioport.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/wait.h>
  17. #include <linux/kthread.h>
  18. #include <linux/freezer.h>
  19. #include <linux/suspend.h>
  20. #include <linux/fsl_devices.h>
  21. #include <linux/of_address.h>
  22. #include <linux/of_irq.h>
  23. #include <linux/of_platform.h>
  24. #include <linux/export.h>
  25. #include <asm/reg.h>
  26. #include <asm/io.h>
  27. #include <asm/time.h>
  28. #include <asm/mpc6xx.h>
  29. #include <asm/switch_to.h>
  30. #include <sysdev/fsl_soc.h>
  31. #define PMCCR1_NEXT_STATE 0x0C /* Next state for power management */
  32. #define PMCCR1_NEXT_STATE_SHIFT 2
  33. #define PMCCR1_CURR_STATE 0x03 /* Current state for power management*/
  34. #define IMMR_SYSCR_OFFSET 0x100
  35. #define IMMR_RCW_OFFSET 0x900
  36. #define RCW_PCI_HOST 0x80000000
  37. void mpc83xx_enter_deep_sleep(phys_addr_t immrbase);
  38. struct mpc83xx_pmc {
  39. u32 config;
  40. #define PMCCR_DLPEN 2 /* DDR SDRAM low power enable */
  41. #define PMCCR_SLPEN 1 /* System low power enable */
  42. u32 event;
  43. u32 mask;
  44. /* All but PMCI are deep-sleep only */
  45. #define PMCER_GPIO 0x100
  46. #define PMCER_PCI 0x080
  47. #define PMCER_USB 0x040
  48. #define PMCER_ETSEC1 0x020
  49. #define PMCER_ETSEC2 0x010
  50. #define PMCER_TIMER 0x008
  51. #define PMCER_INT1 0x004
  52. #define PMCER_INT2 0x002
  53. #define PMCER_PMCI 0x001
  54. #define PMCER_ALL 0x1FF
  55. /* deep-sleep only */
  56. u32 config1;
  57. #define PMCCR1_USE_STATE 0x80000000
  58. #define PMCCR1_PME_EN 0x00000080
  59. #define PMCCR1_ASSERT_PME 0x00000040
  60. #define PMCCR1_POWER_OFF 0x00000020
  61. /* deep-sleep only */
  62. u32 config2;
  63. };
  64. struct mpc83xx_rcw {
  65. u32 rcwlr;
  66. u32 rcwhr;
  67. };
  68. struct mpc83xx_clock {
  69. u32 spmr;
  70. u32 occr;
  71. u32 sccr;
  72. };
  73. struct mpc83xx_syscr {
  74. __be32 sgprl;
  75. __be32 sgprh;
  76. __be32 spridr;
  77. __be32 :32;
  78. __be32 spcr;
  79. __be32 sicrl;
  80. __be32 sicrh;
  81. };
  82. struct mpc83xx_saved {
  83. u32 sicrl;
  84. u32 sicrh;
  85. u32 sccr;
  86. };
  87. struct pmc_type {
  88. int has_deep_sleep;
  89. };
  90. static struct platform_device *pmc_dev;
  91. static int has_deep_sleep, deep_sleeping;
  92. static int pmc_irq;
  93. static struct mpc83xx_pmc __iomem *pmc_regs;
  94. static struct mpc83xx_clock __iomem *clock_regs;
  95. static struct mpc83xx_syscr __iomem *syscr_regs;
  96. static struct mpc83xx_saved saved_regs;
  97. static int is_pci_agent, wake_from_pci;
  98. static phys_addr_t immrbase;
  99. static int pci_pm_state;
  100. static DECLARE_WAIT_QUEUE_HEAD(agent_wq);
  101. int fsl_deep_sleep(void)
  102. {
  103. return deep_sleeping;
  104. }
  105. EXPORT_SYMBOL(fsl_deep_sleep);
  106. static int mpc83xx_change_state(void)
  107. {
  108. u32 curr_state;
  109. u32 reg_cfg1 = in_be32(&pmc_regs->config1);
  110. if (is_pci_agent) {
  111. pci_pm_state = (reg_cfg1 & PMCCR1_NEXT_STATE) >>
  112. PMCCR1_NEXT_STATE_SHIFT;
  113. curr_state = reg_cfg1 & PMCCR1_CURR_STATE;
  114. if (curr_state != pci_pm_state) {
  115. reg_cfg1 &= ~PMCCR1_CURR_STATE;
  116. reg_cfg1 |= pci_pm_state;
  117. out_be32(&pmc_regs->config1, reg_cfg1);
  118. wake_up(&agent_wq);
  119. return 1;
  120. }
  121. }
  122. return 0;
  123. }
  124. static irqreturn_t pmc_irq_handler(int irq, void *dev_id)
  125. {
  126. u32 event = in_be32(&pmc_regs->event);
  127. int ret = IRQ_NONE;
  128. if (mpc83xx_change_state())
  129. ret = IRQ_HANDLED;
  130. if (event) {
  131. out_be32(&pmc_regs->event, event);
  132. ret = IRQ_HANDLED;
  133. }
  134. return ret;
  135. }
  136. static void mpc83xx_suspend_restore_regs(void)
  137. {
  138. out_be32(&syscr_regs->sicrl, saved_regs.sicrl);
  139. out_be32(&syscr_regs->sicrh, saved_regs.sicrh);
  140. out_be32(&clock_regs->sccr, saved_regs.sccr);
  141. }
  142. static void mpc83xx_suspend_save_regs(void)
  143. {
  144. saved_regs.sicrl = in_be32(&syscr_regs->sicrl);
  145. saved_regs.sicrh = in_be32(&syscr_regs->sicrh);
  146. saved_regs.sccr = in_be32(&clock_regs->sccr);
  147. }
  148. static int mpc83xx_suspend_enter(suspend_state_t state)
  149. {
  150. int ret = -EAGAIN;
  151. /* Don't go to sleep if there's a race where pci_pm_state changes
  152. * between the agent thread checking it and the PM code disabling
  153. * interrupts.
  154. */
  155. if (wake_from_pci) {
  156. if (pci_pm_state != (deep_sleeping ? 3 : 2))
  157. goto out;
  158. out_be32(&pmc_regs->config1,
  159. in_be32(&pmc_regs->config1) | PMCCR1_PME_EN);
  160. }
  161. /* Put the system into low-power mode and the RAM
  162. * into self-refresh mode once the core goes to
  163. * sleep.
  164. */
  165. out_be32(&pmc_regs->config, PMCCR_SLPEN | PMCCR_DLPEN);
  166. /* If it has deep sleep (i.e. it's an 831x or compatible),
  167. * disable power to the core upon entering sleep mode. This will
  168. * require going through the boot firmware upon a wakeup event.
  169. */
  170. if (deep_sleeping) {
  171. mpc83xx_suspend_save_regs();
  172. out_be32(&pmc_regs->mask, PMCER_ALL);
  173. out_be32(&pmc_regs->config1,
  174. in_be32(&pmc_regs->config1) | PMCCR1_POWER_OFF);
  175. enable_kernel_fp();
  176. mpc83xx_enter_deep_sleep(immrbase);
  177. out_be32(&pmc_regs->config1,
  178. in_be32(&pmc_regs->config1) & ~PMCCR1_POWER_OFF);
  179. out_be32(&pmc_regs->mask, PMCER_PMCI);
  180. mpc83xx_suspend_restore_regs();
  181. } else {
  182. out_be32(&pmc_regs->mask, PMCER_PMCI);
  183. mpc6xx_enter_standby();
  184. }
  185. ret = 0;
  186. out:
  187. out_be32(&pmc_regs->config1,
  188. in_be32(&pmc_regs->config1) & ~PMCCR1_PME_EN);
  189. return ret;
  190. }
  191. static void mpc83xx_suspend_end(void)
  192. {
  193. deep_sleeping = 0;
  194. }
  195. static int mpc83xx_suspend_valid(suspend_state_t state)
  196. {
  197. return state == PM_SUSPEND_STANDBY || state == PM_SUSPEND_MEM;
  198. }
  199. static int mpc83xx_suspend_begin(suspend_state_t state)
  200. {
  201. switch (state) {
  202. case PM_SUSPEND_STANDBY:
  203. deep_sleeping = 0;
  204. return 0;
  205. case PM_SUSPEND_MEM:
  206. if (has_deep_sleep)
  207. deep_sleeping = 1;
  208. return 0;
  209. default:
  210. return -EINVAL;
  211. }
  212. }
  213. static int agent_thread_fn(void *data)
  214. {
  215. while (1) {
  216. wait_event_interruptible(agent_wq, pci_pm_state >= 2);
  217. try_to_freeze();
  218. if (signal_pending(current) || pci_pm_state < 2)
  219. continue;
  220. /* With a preemptible kernel (or SMP), this could race with
  221. * a userspace-driven suspend request. It's probably best
  222. * to avoid mixing the two with such a configuration (or
  223. * else fix it by adding a mutex to state_store that we can
  224. * synchronize with).
  225. */
  226. wake_from_pci = 1;
  227. pm_suspend(pci_pm_state == 3 ? PM_SUSPEND_MEM :
  228. PM_SUSPEND_STANDBY);
  229. wake_from_pci = 0;
  230. }
  231. return 0;
  232. }
  233. static void mpc83xx_set_agent(void)
  234. {
  235. out_be32(&pmc_regs->config1, PMCCR1_USE_STATE);
  236. out_be32(&pmc_regs->mask, PMCER_PMCI);
  237. kthread_run(agent_thread_fn, NULL, "PCI power mgt");
  238. }
  239. static int mpc83xx_is_pci_agent(void)
  240. {
  241. struct mpc83xx_rcw __iomem *rcw_regs;
  242. int ret;
  243. rcw_regs = ioremap(get_immrbase() + IMMR_RCW_OFFSET,
  244. sizeof(struct mpc83xx_rcw));
  245. if (!rcw_regs)
  246. return -ENOMEM;
  247. ret = !(in_be32(&rcw_regs->rcwhr) & RCW_PCI_HOST);
  248. iounmap(rcw_regs);
  249. return ret;
  250. }
  251. static const struct platform_suspend_ops mpc83xx_suspend_ops = {
  252. .valid = mpc83xx_suspend_valid,
  253. .begin = mpc83xx_suspend_begin,
  254. .enter = mpc83xx_suspend_enter,
  255. .end = mpc83xx_suspend_end,
  256. };
  257. static const struct of_device_id pmc_match[];
  258. static int pmc_probe(struct platform_device *ofdev)
  259. {
  260. const struct of_device_id *match;
  261. struct device_node *np = ofdev->dev.of_node;
  262. struct resource res;
  263. const struct pmc_type *type;
  264. int ret = 0;
  265. match = of_match_device(pmc_match, &ofdev->dev);
  266. if (!match)
  267. return -EINVAL;
  268. type = match->data;
  269. if (!of_device_is_available(np))
  270. return -ENODEV;
  271. has_deep_sleep = type->has_deep_sleep;
  272. immrbase = get_immrbase();
  273. pmc_dev = ofdev;
  274. is_pci_agent = mpc83xx_is_pci_agent();
  275. if (is_pci_agent < 0)
  276. return is_pci_agent;
  277. ret = of_address_to_resource(np, 0, &res);
  278. if (ret)
  279. return -ENODEV;
  280. pmc_irq = irq_of_parse_and_map(np, 0);
  281. if (pmc_irq) {
  282. ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
  283. "pmc", ofdev);
  284. if (ret)
  285. return -EBUSY;
  286. }
  287. pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
  288. if (!pmc_regs) {
  289. ret = -ENOMEM;
  290. goto out;
  291. }
  292. ret = of_address_to_resource(np, 1, &res);
  293. if (ret) {
  294. ret = -ENODEV;
  295. goto out_pmc;
  296. }
  297. clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
  298. if (!clock_regs) {
  299. ret = -ENOMEM;
  300. goto out_pmc;
  301. }
  302. if (has_deep_sleep) {
  303. syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
  304. sizeof(*syscr_regs));
  305. if (!syscr_regs) {
  306. ret = -ENOMEM;
  307. goto out_syscr;
  308. }
  309. }
  310. if (is_pci_agent)
  311. mpc83xx_set_agent();
  312. suspend_set_ops(&mpc83xx_suspend_ops);
  313. return 0;
  314. out_syscr:
  315. iounmap(clock_regs);
  316. out_pmc:
  317. iounmap(pmc_regs);
  318. out:
  319. if (pmc_irq)
  320. free_irq(pmc_irq, ofdev);
  321. return ret;
  322. }
  323. static int pmc_remove(struct platform_device *ofdev)
  324. {
  325. return -EPERM;
  326. };
  327. static struct pmc_type pmc_types[] = {
  328. {
  329. .has_deep_sleep = 1,
  330. },
  331. {
  332. .has_deep_sleep = 0,
  333. }
  334. };
  335. static const struct of_device_id pmc_match[] = {
  336. {
  337. .compatible = "fsl,mpc8313-pmc",
  338. .data = &pmc_types[0],
  339. },
  340. {
  341. .compatible = "fsl,mpc8349-pmc",
  342. .data = &pmc_types[1],
  343. },
  344. {}
  345. };
  346. static struct platform_driver pmc_driver = {
  347. .driver = {
  348. .name = "mpc83xx-pmc",
  349. .of_match_table = pmc_match,
  350. },
  351. .probe = pmc_probe,
  352. .remove = pmc_remove
  353. };
  354. static int pmc_init(void)
  355. {
  356. return platform_driver_register(&pmc_driver);
  357. }
  358. device_initcall(pmc_init);