km83xx.c 4.5 KB

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  1. /*
  2. * Copyright 2008-2011 DENX Software Engineering GmbH
  3. * Author: Heiko Schocher <hs@denx.de>
  4. *
  5. * Description:
  6. * Keymile 83xx platform specific routines.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/stddef.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/errno.h>
  17. #include <linux/reboot.h>
  18. #include <linux/pci.h>
  19. #include <linux/kdev_t.h>
  20. #include <linux/major.h>
  21. #include <linux/console.h>
  22. #include <linux/delay.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/root_dev.h>
  25. #include <linux/initrd.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/of_device.h>
  28. #include <linux/atomic.h>
  29. #include <linux/time.h>
  30. #include <linux/io.h>
  31. #include <asm/machdep.h>
  32. #include <asm/ipic.h>
  33. #include <asm/irq.h>
  34. #include <asm/prom.h>
  35. #include <asm/udbg.h>
  36. #include <sysdev/fsl_soc.h>
  37. #include <sysdev/fsl_pci.h>
  38. #include <soc/fsl/qe/qe.h>
  39. #include <soc/fsl/qe/qe_ic.h>
  40. #include "mpc83xx.h"
  41. #define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */
  42. static void quirk_mpc8360e_qe_enet10(void)
  43. {
  44. /*
  45. * handle mpc8360E Erratum QE_ENET10:
  46. * RGMII AC values do not meet the specification
  47. */
  48. uint svid = mfspr(SPRN_SVR);
  49. struct device_node *np_par;
  50. struct resource res;
  51. void __iomem *base;
  52. int ret;
  53. np_par = of_find_node_by_name(NULL, "par_io");
  54. if (np_par == NULL) {
  55. pr_warn("%s couldn;t find par_io node\n", __func__);
  56. return;
  57. }
  58. /* Map Parallel I/O ports registers */
  59. ret = of_address_to_resource(np_par, 0, &res);
  60. if (ret) {
  61. pr_warn("%s couldn;t map par_io registers\n", __func__);
  62. return;
  63. }
  64. base = ioremap(res.start, res.end - res.start + 1);
  65. /*
  66. * set output delay adjustments to default values according
  67. * table 5 in Errata Rev. 5, 9/2011:
  68. *
  69. * write 0b01 to UCC1 bits 18:19
  70. * write 0b01 to UCC2 option 1 bits 4:5
  71. * write 0b01 to UCC2 option 2 bits 16:17
  72. */
  73. clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
  74. /*
  75. * set output delay adjustments to default values according
  76. * table 3-13 in Reference Manual Rev.3 05/2010:
  77. *
  78. * write 0b01 to UCC2 option 2 bits 16:17
  79. * write 0b0101 to UCC1 bits 20:23
  80. * write 0b0101 to UCC2 option 1 bits 24:27
  81. */
  82. clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
  83. if (SVR_REV(svid) == 0x0021) {
  84. /*
  85. * UCC2 option 1: write 0b1010 to bits 24:27
  86. * at address IMMRBAR+0x14AC
  87. */
  88. clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
  89. } else if (SVR_REV(svid) == 0x0020) {
  90. /*
  91. * UCC1: write 0b11 to bits 18:19
  92. * at address IMMRBAR+0x14A8
  93. */
  94. setbits32((base + 0xa8), 0x00003000);
  95. /*
  96. * UCC2 option 1: write 0b11 to bits 4:5
  97. * at address IMMRBAR+0x14A8
  98. */
  99. setbits32((base + 0xa8), 0x0c000000);
  100. /*
  101. * UCC2 option 2: write 0b11 to bits 16:17
  102. * at address IMMRBAR+0x14AC
  103. */
  104. setbits32((base + 0xac), 0x0000c000);
  105. }
  106. iounmap(base);
  107. of_node_put(np_par);
  108. }
  109. /* ************************************************************************
  110. *
  111. * Setup the architecture
  112. *
  113. */
  114. static void __init mpc83xx_km_setup_arch(void)
  115. {
  116. #ifdef CONFIG_QUICC_ENGINE
  117. struct device_node *np;
  118. #endif
  119. mpc83xx_setup_arch();
  120. #ifdef CONFIG_QUICC_ENGINE
  121. np = of_find_node_by_name(NULL, "par_io");
  122. if (np != NULL) {
  123. par_io_init(np);
  124. of_node_put(np);
  125. for_each_node_by_name(np, "spi")
  126. par_io_of_config(np);
  127. for_each_node_by_name(np, "ucc")
  128. par_io_of_config(np);
  129. /* Only apply this quirk when par_io is available */
  130. np = of_find_compatible_node(NULL, "network", "ucc_geth");
  131. if (np != NULL) {
  132. quirk_mpc8360e_qe_enet10();
  133. of_node_put(np);
  134. }
  135. }
  136. #endif /* CONFIG_QUICC_ENGINE */
  137. }
  138. machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
  139. /* list of the supported boards */
  140. static char *board[] __initdata = {
  141. "Keymile,KMETER1",
  142. "Keymile,kmpbec8321",
  143. NULL
  144. };
  145. /*
  146. * Called very early, MMU is off, device-tree isn't unflattened
  147. */
  148. static int __init mpc83xx_km_probe(void)
  149. {
  150. int i = 0;
  151. while (board[i]) {
  152. if (of_machine_is_compatible(board[i]))
  153. break;
  154. i++;
  155. }
  156. return (board[i] != NULL);
  157. }
  158. define_machine(mpc83xx_km) {
  159. .name = "mpc83xx-km-platform",
  160. .probe = mpc83xx_km_probe,
  161. .setup_arch = mpc83xx_km_setup_arch,
  162. .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
  163. .get_irq = ipic_get_irq,
  164. .restart = mpc83xx_restart,
  165. .time_init = mpc83xx_time_init,
  166. .calibrate_decr = generic_calibrate_decr,
  167. .progress = udbg_progress,
  168. };