power8-events-list.h 3.2 KB

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  1. /*
  2. * Performance counter support for POWER8 processors.
  3. *
  4. * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. /*
  12. * Power8 event codes.
  13. */
  14. EVENT(PM_CYC, 0x0001e)
  15. EVENT(PM_GCT_NOSLOT_CYC, 0x100f8)
  16. EVENT(PM_CMPLU_STALL, 0x4000a)
  17. EVENT(PM_INST_CMPL, 0x00002)
  18. EVENT(PM_BRU_FIN, 0x10068)
  19. EVENT(PM_BR_MPRED_CMPL, 0x400f6)
  20. /* All L1 D cache load references counted at finish, gated by reject */
  21. EVENT(PM_LD_REF_L1, 0x100ee)
  22. /* Load Missed L1 */
  23. EVENT(PM_LD_MISS_L1, 0x3e054)
  24. /* Store Missed L1 */
  25. EVENT(PM_ST_MISS_L1, 0x300f0)
  26. /* L1 cache data prefetches */
  27. EVENT(PM_L1_PREF, 0x0d8b8)
  28. /* Instruction fetches from L1 */
  29. EVENT(PM_INST_FROM_L1, 0x04080)
  30. /* Demand iCache Miss */
  31. EVENT(PM_L1_ICACHE_MISS, 0x200fd)
  32. /* Instruction Demand sectors wriittent into IL1 */
  33. EVENT(PM_L1_DEMAND_WRITE, 0x0408c)
  34. /* Instruction prefetch written into IL1 */
  35. EVENT(PM_IC_PREF_WRITE, 0x0408e)
  36. /* The data cache was reloaded from local core's L3 due to a demand load */
  37. EVENT(PM_DATA_FROM_L3, 0x4c042)
  38. /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
  39. EVENT(PM_DATA_FROM_L3MISS, 0x300fe)
  40. /* All successful D-side store dispatches for this thread */
  41. EVENT(PM_L2_ST, 0x17080)
  42. /* All successful D-side store dispatches for this thread that were L2 Miss */
  43. EVENT(PM_L2_ST_MISS, 0x17082)
  44. /* Total HW L3 prefetches(Load+store) */
  45. EVENT(PM_L3_PREF_ALL, 0x4e052)
  46. /* Data PTEG reload */
  47. EVENT(PM_DTLB_MISS, 0x300fc)
  48. /* ITLB Reloaded */
  49. EVENT(PM_ITLB_MISS, 0x400fc)
  50. /* Run_Instructions */
  51. EVENT(PM_RUN_INST_CMPL, 0x500fa)
  52. /* Alternate event code for PM_RUN_INST_CMPL */
  53. EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa)
  54. /* Run_cycles */
  55. EVENT(PM_RUN_CYC, 0x600f4)
  56. /* Alternate event code for Run_cycles */
  57. EVENT(PM_RUN_CYC_ALT, 0x200f4)
  58. /* Marked store completed */
  59. EVENT(PM_MRK_ST_CMPL, 0x10134)
  60. /* Alternate event code for Marked store completed */
  61. EVENT(PM_MRK_ST_CMPL_ALT, 0x301e2)
  62. /* Marked two path branch */
  63. EVENT(PM_BR_MRK_2PATH, 0x10138)
  64. /* Alternate event code for PM_BR_MRK_2PATH */
  65. EVENT(PM_BR_MRK_2PATH_ALT, 0x40138)
  66. /* L3 castouts in Mepf state */
  67. EVENT(PM_L3_CO_MEPF, 0x18082)
  68. /* Alternate event code for PM_L3_CO_MEPF */
  69. EVENT(PM_L3_CO_MEPF_ALT, 0x3e05e)
  70. /* Data cache was reloaded from a location other than L2 due to a marked load */
  71. EVENT(PM_MRK_DATA_FROM_L2MISS, 0x1d14e)
  72. /* Alternate event code for PM_MRK_DATA_FROM_L2MISS */
  73. EVENT(PM_MRK_DATA_FROM_L2MISS_ALT, 0x401e8)
  74. /* Alternate event code for PM_CMPLU_STALL */
  75. EVENT(PM_CMPLU_STALL_ALT, 0x1e054)
  76. /* Two path branch */
  77. EVENT(PM_BR_2PATH, 0x20036)
  78. /* Alternate event code for PM_BR_2PATH */
  79. EVENT(PM_BR_2PATH_ALT, 0x40036)
  80. /* # PPC Dispatched */
  81. EVENT(PM_INST_DISP, 0x200f2)
  82. /* Alternate event code for PM_INST_DISP */
  83. EVENT(PM_INST_DISP_ALT, 0x300f2)
  84. /* Marked filter Match */
  85. EVENT(PM_MRK_FILT_MATCH, 0x2013c)
  86. /* Alternate event code for PM_MRK_FILT_MATCH */
  87. EVENT(PM_MRK_FILT_MATCH_ALT, 0x3012e)
  88. /* Alternate event code for PM_LD_MISS_L1 */
  89. EVENT(PM_LD_MISS_L1_ALT, 0x400f0)