idma.c 9.5 KB

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  1. /*
  2. * sound/soc/samsung/idma.c
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * I2S0's Internal DMA driver
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/dma-mapping.h>
  17. #include <linux/slab.h>
  18. #include <linux/module.h>
  19. #include <sound/pcm.h>
  20. #include <sound/pcm_params.h>
  21. #include <sound/soc.h>
  22. #include "i2s.h"
  23. #include "idma.h"
  24. #include "i2s-regs.h"
  25. #define ST_RUNNING (1<<0)
  26. #define ST_OPENED (1<<1)
  27. static const struct snd_pcm_hardware idma_hardware = {
  28. .info = SNDRV_PCM_INFO_INTERLEAVED |
  29. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  30. SNDRV_PCM_INFO_MMAP |
  31. SNDRV_PCM_INFO_MMAP_VALID |
  32. SNDRV_PCM_INFO_PAUSE |
  33. SNDRV_PCM_INFO_RESUME,
  34. .buffer_bytes_max = MAX_IDMA_BUFFER,
  35. .period_bytes_min = 128,
  36. .period_bytes_max = MAX_IDMA_PERIOD,
  37. .periods_min = 1,
  38. .periods_max = 2,
  39. };
  40. struct idma_ctrl {
  41. spinlock_t lock;
  42. int state;
  43. dma_addr_t start;
  44. dma_addr_t pos;
  45. dma_addr_t end;
  46. dma_addr_t period;
  47. dma_addr_t periodsz;
  48. void *token;
  49. void (*cb)(void *dt, int bytes_xfer);
  50. };
  51. static struct idma_info {
  52. spinlock_t lock;
  53. void __iomem *regs;
  54. dma_addr_t lp_tx_addr;
  55. } idma;
  56. static int idma_irq;
  57. static void idma_getpos(dma_addr_t *src)
  58. {
  59. *src = idma.lp_tx_addr +
  60. (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
  61. }
  62. static int idma_enqueue(struct snd_pcm_substream *substream)
  63. {
  64. struct snd_pcm_runtime *runtime = substream->runtime;
  65. struct idma_ctrl *prtd = substream->runtime->private_data;
  66. u32 val;
  67. spin_lock(&prtd->lock);
  68. prtd->token = (void *) substream;
  69. spin_unlock(&prtd->lock);
  70. /* Internal DMA Level0 Interrupt Address */
  71. val = idma.lp_tx_addr + prtd->periodsz;
  72. writel(val, idma.regs + I2SLVL0ADDR);
  73. /* Start address0 of I2S internal DMA operation. */
  74. val = idma.lp_tx_addr;
  75. writel(val, idma.regs + I2SSTR0);
  76. /*
  77. * Transfer block size for I2S internal DMA.
  78. * Should decide transfer size before start dma operation
  79. */
  80. val = readl(idma.regs + I2SSIZE);
  81. val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT);
  82. val |= (((runtime->dma_bytes >> 2) &
  83. I2SSIZE_TRNMSK) << I2SSIZE_SHIFT);
  84. writel(val, idma.regs + I2SSIZE);
  85. val = readl(idma.regs + I2SAHB);
  86. val |= AHB_INTENLVL0;
  87. writel(val, idma.regs + I2SAHB);
  88. return 0;
  89. }
  90. static void idma_setcallbk(struct snd_pcm_substream *substream,
  91. void (*cb)(void *, int))
  92. {
  93. struct idma_ctrl *prtd = substream->runtime->private_data;
  94. spin_lock(&prtd->lock);
  95. prtd->cb = cb;
  96. spin_unlock(&prtd->lock);
  97. }
  98. static void idma_control(int op)
  99. {
  100. u32 val = readl(idma.regs + I2SAHB);
  101. spin_lock(&idma.lock);
  102. switch (op) {
  103. case LPAM_DMA_START:
  104. val |= (AHB_INTENLVL0 | AHB_DMAEN);
  105. break;
  106. case LPAM_DMA_STOP:
  107. val &= ~(AHB_INTENLVL0 | AHB_DMAEN);
  108. break;
  109. default:
  110. spin_unlock(&idma.lock);
  111. return;
  112. }
  113. writel(val, idma.regs + I2SAHB);
  114. spin_unlock(&idma.lock);
  115. }
  116. static void idma_done(void *id, int bytes_xfer)
  117. {
  118. struct snd_pcm_substream *substream = id;
  119. struct idma_ctrl *prtd = substream->runtime->private_data;
  120. if (prtd && (prtd->state & ST_RUNNING))
  121. snd_pcm_period_elapsed(substream);
  122. }
  123. static int idma_hw_params(struct snd_pcm_substream *substream,
  124. struct snd_pcm_hw_params *params)
  125. {
  126. struct snd_pcm_runtime *runtime = substream->runtime;
  127. struct idma_ctrl *prtd = substream->runtime->private_data;
  128. u32 mod = readl(idma.regs + I2SMOD);
  129. u32 ahb = readl(idma.regs + I2SAHB);
  130. ahb |= (AHB_DMARLD | AHB_INTMASK);
  131. mod |= MOD_TXS_IDMA;
  132. writel(ahb, idma.regs + I2SAHB);
  133. writel(mod, idma.regs + I2SMOD);
  134. snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
  135. runtime->dma_bytes = params_buffer_bytes(params);
  136. prtd->start = prtd->pos = runtime->dma_addr;
  137. prtd->period = params_periods(params);
  138. prtd->periodsz = params_period_bytes(params);
  139. prtd->end = runtime->dma_addr + runtime->dma_bytes;
  140. idma_setcallbk(substream, idma_done);
  141. return 0;
  142. }
  143. static int idma_hw_free(struct snd_pcm_substream *substream)
  144. {
  145. snd_pcm_set_runtime_buffer(substream, NULL);
  146. return 0;
  147. }
  148. static int idma_prepare(struct snd_pcm_substream *substream)
  149. {
  150. struct idma_ctrl *prtd = substream->runtime->private_data;
  151. prtd->pos = prtd->start;
  152. /* flush the DMA channel */
  153. idma_control(LPAM_DMA_STOP);
  154. idma_enqueue(substream);
  155. return 0;
  156. }
  157. static int idma_trigger(struct snd_pcm_substream *substream, int cmd)
  158. {
  159. struct idma_ctrl *prtd = substream->runtime->private_data;
  160. int ret = 0;
  161. spin_lock(&prtd->lock);
  162. switch (cmd) {
  163. case SNDRV_PCM_TRIGGER_RESUME:
  164. case SNDRV_PCM_TRIGGER_START:
  165. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  166. prtd->state |= ST_RUNNING;
  167. idma_control(LPAM_DMA_START);
  168. break;
  169. case SNDRV_PCM_TRIGGER_SUSPEND:
  170. case SNDRV_PCM_TRIGGER_STOP:
  171. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  172. prtd->state &= ~ST_RUNNING;
  173. idma_control(LPAM_DMA_STOP);
  174. break;
  175. default:
  176. ret = -EINVAL;
  177. break;
  178. }
  179. spin_unlock(&prtd->lock);
  180. return ret;
  181. }
  182. static snd_pcm_uframes_t
  183. idma_pointer(struct snd_pcm_substream *substream)
  184. {
  185. struct snd_pcm_runtime *runtime = substream->runtime;
  186. struct idma_ctrl *prtd = runtime->private_data;
  187. dma_addr_t src;
  188. unsigned long res;
  189. spin_lock(&prtd->lock);
  190. idma_getpos(&src);
  191. res = src - prtd->start;
  192. spin_unlock(&prtd->lock);
  193. return bytes_to_frames(substream->runtime, res);
  194. }
  195. static int idma_mmap(struct snd_pcm_substream *substream,
  196. struct vm_area_struct *vma)
  197. {
  198. struct snd_pcm_runtime *runtime = substream->runtime;
  199. unsigned long size, offset;
  200. int ret;
  201. /* From snd_pcm_lib_mmap_iomem */
  202. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  203. size = vma->vm_end - vma->vm_start;
  204. offset = vma->vm_pgoff << PAGE_SHIFT;
  205. ret = io_remap_pfn_range(vma, vma->vm_start,
  206. (runtime->dma_addr + offset) >> PAGE_SHIFT,
  207. size, vma->vm_page_prot);
  208. return ret;
  209. }
  210. static irqreturn_t iis_irq(int irqno, void *dev_id)
  211. {
  212. struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
  213. u32 iisahb, val, addr;
  214. iisahb = readl(idma.regs + I2SAHB);
  215. val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
  216. if (val) {
  217. iisahb |= val;
  218. writel(iisahb, idma.regs + I2SAHB);
  219. addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
  220. addr += prtd->periodsz;
  221. addr %= (u32)(prtd->end - prtd->start);
  222. addr += idma.lp_tx_addr;
  223. writel(addr, idma.regs + I2SLVL0ADDR);
  224. if (prtd->cb)
  225. prtd->cb(prtd->token, prtd->period);
  226. }
  227. return IRQ_HANDLED;
  228. }
  229. static int idma_open(struct snd_pcm_substream *substream)
  230. {
  231. struct snd_pcm_runtime *runtime = substream->runtime;
  232. struct idma_ctrl *prtd;
  233. int ret;
  234. snd_soc_set_runtime_hwparams(substream, &idma_hardware);
  235. prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL);
  236. if (prtd == NULL)
  237. return -ENOMEM;
  238. ret = request_irq(idma_irq, iis_irq, 0, "i2s", prtd);
  239. if (ret < 0) {
  240. pr_err("fail to claim i2s irq , ret = %d\n", ret);
  241. kfree(prtd);
  242. return ret;
  243. }
  244. spin_lock_init(&prtd->lock);
  245. runtime->private_data = prtd;
  246. return 0;
  247. }
  248. static int idma_close(struct snd_pcm_substream *substream)
  249. {
  250. struct snd_pcm_runtime *runtime = substream->runtime;
  251. struct idma_ctrl *prtd = runtime->private_data;
  252. free_irq(idma_irq, prtd);
  253. if (!prtd)
  254. pr_err("idma_close called with prtd == NULL\n");
  255. kfree(prtd);
  256. return 0;
  257. }
  258. static struct snd_pcm_ops idma_ops = {
  259. .open = idma_open,
  260. .close = idma_close,
  261. .ioctl = snd_pcm_lib_ioctl,
  262. .trigger = idma_trigger,
  263. .pointer = idma_pointer,
  264. .mmap = idma_mmap,
  265. .hw_params = idma_hw_params,
  266. .hw_free = idma_hw_free,
  267. .prepare = idma_prepare,
  268. };
  269. static void idma_free(struct snd_pcm *pcm)
  270. {
  271. struct snd_pcm_substream *substream;
  272. struct snd_dma_buffer *buf;
  273. substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  274. if (!substream)
  275. return;
  276. buf = &substream->dma_buffer;
  277. if (!buf->area)
  278. return;
  279. iounmap((void __iomem *)buf->area);
  280. buf->area = NULL;
  281. buf->addr = 0;
  282. }
  283. static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream)
  284. {
  285. struct snd_pcm_substream *substream = pcm->streams[stream].substream;
  286. struct snd_dma_buffer *buf = &substream->dma_buffer;
  287. buf->dev.dev = pcm->card->dev;
  288. buf->private_data = NULL;
  289. /* Assign PCM buffer pointers */
  290. buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
  291. buf->addr = idma.lp_tx_addr;
  292. buf->bytes = idma_hardware.buffer_bytes_max;
  293. buf->area = (unsigned char * __force)ioremap(buf->addr, buf->bytes);
  294. return 0;
  295. }
  296. static int idma_new(struct snd_soc_pcm_runtime *rtd)
  297. {
  298. struct snd_card *card = rtd->card->snd_card;
  299. struct snd_pcm *pcm = rtd->pcm;
  300. int ret;
  301. ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
  302. if (ret)
  303. return ret;
  304. if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
  305. ret = preallocate_idma_buffer(pcm,
  306. SNDRV_PCM_STREAM_PLAYBACK);
  307. }
  308. return ret;
  309. }
  310. void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr)
  311. {
  312. spin_lock_init(&idma.lock);
  313. idma.regs = regs;
  314. idma.lp_tx_addr = addr;
  315. }
  316. EXPORT_SYMBOL_GPL(idma_reg_addr_init);
  317. static struct snd_soc_platform_driver asoc_idma_platform = {
  318. .ops = &idma_ops,
  319. .pcm_new = idma_new,
  320. .pcm_free = idma_free,
  321. };
  322. static int asoc_idma_platform_probe(struct platform_device *pdev)
  323. {
  324. idma_irq = platform_get_irq(pdev, 0);
  325. if (idma_irq < 0)
  326. return idma_irq;
  327. return devm_snd_soc_register_platform(&pdev->dev, &asoc_idma_platform);
  328. }
  329. static struct platform_driver asoc_idma_driver = {
  330. .driver = {
  331. .name = "samsung-idma",
  332. },
  333. .probe = asoc_idma_platform_probe,
  334. };
  335. module_platform_driver(asoc_idma_driver);
  336. MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
  337. MODULE_DESCRIPTION("Samsung ASoC IDMA Driver");
  338. MODULE_LICENSE("GPL");