rockchip_spdif.h 1.8 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364
  1. /*
  2. * ALSA SoC Audio Layer - Rockchip SPDIF transceiver driver
  3. *
  4. * Copyright (c) 2015 Collabora Ltd.
  5. * Author: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #ifndef _ROCKCHIP_SPDIF_H
  12. #define _ROCKCHIP_SPDIF_H
  13. /*
  14. * CFGR
  15. * transfer configuration register
  16. */
  17. #define SPDIF_CFGR_CLK_DIV_SHIFT (16)
  18. #define SPDIF_CFGR_CLK_DIV_MASK (0xff << SPDIF_CFGR_CLK_DIV_SHIFT)
  19. #define SPDIF_CFGR_CLK_DIV(x) (x << SPDIF_CFGR_CLK_DIV_SHIFT)
  20. #define SPDIF_CFGR_HALFWORD_SHIFT 2
  21. #define SPDIF_CFGR_HALFWORD_DISABLE (0 << SPDIF_CFGR_HALFWORD_SHIFT)
  22. #define SPDIF_CFGR_HALFWORD_ENABLE (1 << SPDIF_CFGR_HALFWORD_SHIFT)
  23. #define SPDIF_CFGR_VDW_SHIFT 0
  24. #define SPDIF_CFGR_VDW(x) (x << SPDIF_CFGR_VDW_SHIFT)
  25. #define SDPIF_CFGR_VDW_MASK (0xf << SPDIF_CFGR_VDW_SHIFT)
  26. #define SPDIF_CFGR_VDW_16 SPDIF_CFGR_VDW(0x0)
  27. #define SPDIF_CFGR_VDW_20 SPDIF_CFGR_VDW(0x1)
  28. #define SPDIF_CFGR_VDW_24 SPDIF_CFGR_VDW(0x2)
  29. /*
  30. * DMACR
  31. * DMA control register
  32. */
  33. #define SPDIF_DMACR_TDE_SHIFT 5
  34. #define SPDIF_DMACR_TDE_DISABLE (0 << SPDIF_DMACR_TDE_SHIFT)
  35. #define SPDIF_DMACR_TDE_ENABLE (1 << SPDIF_DMACR_TDE_SHIFT)
  36. #define SPDIF_DMACR_TDL_SHIFT 0
  37. #define SPDIF_DMACR_TDL(x) ((x) << SPDIF_DMACR_TDL_SHIFT)
  38. #define SPDIF_DMACR_TDL_MASK (0x1f << SPDIF_DMACR_TDL_SHIFT)
  39. /*
  40. * XFER
  41. * Transfer control register
  42. */
  43. #define SPDIF_XFER_TXS_SHIFT 0
  44. #define SPDIF_XFER_TXS_STOP (0 << SPDIF_XFER_TXS_SHIFT)
  45. #define SPDIF_XFER_TXS_START (1 << SPDIF_XFER_TXS_SHIFT)
  46. #define SPDIF_CFGR (0x0000)
  47. #define SPDIF_SDBLR (0x0004)
  48. #define SPDIF_DMACR (0x0008)
  49. #define SPDIF_INTCR (0x000c)
  50. #define SPDIF_INTSR (0x0010)
  51. #define SPDIF_XFER (0x0018)
  52. #define SPDIF_SMPDR (0x0020)
  53. #endif /* _ROCKCHIP_SPDIF_H */