omap-dmic.c 12 KB

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  1. /*
  2. * omap-dmic.c -- OMAP ASoC DMIC DAI driver
  3. *
  4. * Copyright (C) 2010 - 2011 Texas Instruments
  5. *
  6. * Author: David Lambert <dlambert@ti.com>
  7. * Misael Lopez Cruz <misael.lopez@ti.com>
  8. * Liam Girdwood <lrg@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/err.h>
  30. #include <linux/clk.h>
  31. #include <linux/io.h>
  32. #include <linux/slab.h>
  33. #include <linux/pm_runtime.h>
  34. #include <linux/of_device.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/initval.h>
  39. #include <sound/soc.h>
  40. #include <sound/dmaengine_pcm.h>
  41. #include <sound/omap-pcm.h>
  42. #include "omap-dmic.h"
  43. struct omap_dmic {
  44. struct device *dev;
  45. void __iomem *io_base;
  46. struct clk *fclk;
  47. int fclk_freq;
  48. int out_freq;
  49. int clk_div;
  50. int sysclk;
  51. int threshold;
  52. u32 ch_enabled;
  53. bool active;
  54. struct mutex mutex;
  55. struct snd_dmaengine_dai_dma_data dma_data;
  56. };
  57. static inline void omap_dmic_write(struct omap_dmic *dmic, u16 reg, u32 val)
  58. {
  59. writel_relaxed(val, dmic->io_base + reg);
  60. }
  61. static inline int omap_dmic_read(struct omap_dmic *dmic, u16 reg)
  62. {
  63. return readl_relaxed(dmic->io_base + reg);
  64. }
  65. static inline void omap_dmic_start(struct omap_dmic *dmic)
  66. {
  67. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  68. /* Configure DMA controller */
  69. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_SET_REG,
  70. OMAP_DMIC_DMA_ENABLE);
  71. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl | dmic->ch_enabled);
  72. }
  73. static inline void omap_dmic_stop(struct omap_dmic *dmic)
  74. {
  75. u32 ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  76. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  77. ctrl & ~OMAP_DMIC_UP_ENABLE_MASK);
  78. /* Disable DMA request generation */
  79. omap_dmic_write(dmic, OMAP_DMIC_DMAENABLE_CLR_REG,
  80. OMAP_DMIC_DMA_ENABLE);
  81. }
  82. static inline int dmic_is_enabled(struct omap_dmic *dmic)
  83. {
  84. return omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG) &
  85. OMAP_DMIC_UP_ENABLE_MASK;
  86. }
  87. static int omap_dmic_dai_startup(struct snd_pcm_substream *substream,
  88. struct snd_soc_dai *dai)
  89. {
  90. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  91. int ret = 0;
  92. mutex_lock(&dmic->mutex);
  93. if (!dai->active)
  94. dmic->active = 1;
  95. else
  96. ret = -EBUSY;
  97. mutex_unlock(&dmic->mutex);
  98. return ret;
  99. }
  100. static void omap_dmic_dai_shutdown(struct snd_pcm_substream *substream,
  101. struct snd_soc_dai *dai)
  102. {
  103. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  104. mutex_lock(&dmic->mutex);
  105. if (!dai->active)
  106. dmic->active = 0;
  107. mutex_unlock(&dmic->mutex);
  108. }
  109. static int omap_dmic_select_divider(struct omap_dmic *dmic, int sample_rate)
  110. {
  111. int divider = -EINVAL;
  112. /*
  113. * 192KHz rate is only supported with 19.2MHz/3.84MHz clock
  114. * configuration.
  115. */
  116. if (sample_rate == 192000) {
  117. if (dmic->fclk_freq == 19200000 && dmic->out_freq == 3840000)
  118. divider = 0x6; /* Divider: 5 (192KHz sampling rate) */
  119. else
  120. dev_err(dmic->dev,
  121. "invalid clock configuration for 192KHz\n");
  122. return divider;
  123. }
  124. switch (dmic->out_freq) {
  125. case 1536000:
  126. if (dmic->fclk_freq != 24576000)
  127. goto div_err;
  128. divider = 0x4; /* Divider: 16 */
  129. break;
  130. case 2400000:
  131. switch (dmic->fclk_freq) {
  132. case 12000000:
  133. divider = 0x5; /* Divider: 5 */
  134. break;
  135. case 19200000:
  136. divider = 0x0; /* Divider: 8 */
  137. break;
  138. case 24000000:
  139. divider = 0x2; /* Divider: 10 */
  140. break;
  141. default:
  142. goto div_err;
  143. }
  144. break;
  145. case 3072000:
  146. if (dmic->fclk_freq != 24576000)
  147. goto div_err;
  148. divider = 0x3; /* Divider: 8 */
  149. break;
  150. case 3840000:
  151. if (dmic->fclk_freq != 19200000)
  152. goto div_err;
  153. divider = 0x1; /* Divider: 5 (96KHz sampling rate) */
  154. break;
  155. default:
  156. dev_err(dmic->dev, "invalid out frequency: %dHz\n",
  157. dmic->out_freq);
  158. break;
  159. }
  160. return divider;
  161. div_err:
  162. dev_err(dmic->dev, "invalid out frequency %dHz for %dHz input\n",
  163. dmic->out_freq, dmic->fclk_freq);
  164. return -EINVAL;
  165. }
  166. static int omap_dmic_dai_hw_params(struct snd_pcm_substream *substream,
  167. struct snd_pcm_hw_params *params,
  168. struct snd_soc_dai *dai)
  169. {
  170. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  171. struct snd_dmaengine_dai_dma_data *dma_data;
  172. int channels;
  173. dmic->clk_div = omap_dmic_select_divider(dmic, params_rate(params));
  174. if (dmic->clk_div < 0) {
  175. dev_err(dmic->dev, "no valid divider for %dHz from %dHz\n",
  176. dmic->out_freq, dmic->fclk_freq);
  177. return -EINVAL;
  178. }
  179. dmic->ch_enabled = 0;
  180. channels = params_channels(params);
  181. switch (channels) {
  182. case 6:
  183. dmic->ch_enabled |= OMAP_DMIC_UP3_ENABLE;
  184. case 4:
  185. dmic->ch_enabled |= OMAP_DMIC_UP2_ENABLE;
  186. case 2:
  187. dmic->ch_enabled |= OMAP_DMIC_UP1_ENABLE;
  188. break;
  189. default:
  190. dev_err(dmic->dev, "invalid number of legacy channels\n");
  191. return -EINVAL;
  192. }
  193. /* packet size is threshold * channels */
  194. dma_data = snd_soc_dai_get_dma_data(dai, substream);
  195. dma_data->maxburst = dmic->threshold * channels;
  196. return 0;
  197. }
  198. static int omap_dmic_dai_prepare(struct snd_pcm_substream *substream,
  199. struct snd_soc_dai *dai)
  200. {
  201. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  202. u32 ctrl;
  203. /* Configure uplink threshold */
  204. omap_dmic_write(dmic, OMAP_DMIC_FIFO_CTRL_REG, dmic->threshold);
  205. ctrl = omap_dmic_read(dmic, OMAP_DMIC_CTRL_REG);
  206. /* Set dmic out format */
  207. ctrl &= ~(OMAP_DMIC_FORMAT | OMAP_DMIC_POLAR_MASK);
  208. ctrl |= (OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  209. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  210. /* Configure dmic clock divider */
  211. ctrl &= ~OMAP_DMIC_CLK_DIV_MASK;
  212. ctrl |= OMAP_DMIC_CLK_DIV(dmic->clk_div);
  213. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, ctrl);
  214. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG,
  215. ctrl | OMAP_DMICOUTFORMAT_LJUST | OMAP_DMIC_POLAR1 |
  216. OMAP_DMIC_POLAR2 | OMAP_DMIC_POLAR3);
  217. return 0;
  218. }
  219. static int omap_dmic_dai_trigger(struct snd_pcm_substream *substream,
  220. int cmd, struct snd_soc_dai *dai)
  221. {
  222. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  223. switch (cmd) {
  224. case SNDRV_PCM_TRIGGER_START:
  225. omap_dmic_start(dmic);
  226. break;
  227. case SNDRV_PCM_TRIGGER_STOP:
  228. omap_dmic_stop(dmic);
  229. break;
  230. default:
  231. break;
  232. }
  233. return 0;
  234. }
  235. static int omap_dmic_select_fclk(struct omap_dmic *dmic, int clk_id,
  236. unsigned int freq)
  237. {
  238. struct clk *parent_clk;
  239. char *parent_clk_name;
  240. int ret = 0;
  241. switch (freq) {
  242. case 12000000:
  243. case 19200000:
  244. case 24000000:
  245. case 24576000:
  246. break;
  247. default:
  248. dev_err(dmic->dev, "invalid input frequency: %dHz\n", freq);
  249. dmic->fclk_freq = 0;
  250. return -EINVAL;
  251. }
  252. if (dmic->sysclk == clk_id) {
  253. dmic->fclk_freq = freq;
  254. return 0;
  255. }
  256. /* re-parent not allowed if a stream is ongoing */
  257. if (dmic->active && dmic_is_enabled(dmic)) {
  258. dev_err(dmic->dev, "can't re-parent when DMIC active\n");
  259. return -EBUSY;
  260. }
  261. switch (clk_id) {
  262. case OMAP_DMIC_SYSCLK_PAD_CLKS:
  263. parent_clk_name = "pad_clks_ck";
  264. break;
  265. case OMAP_DMIC_SYSCLK_SLIMBLUS_CLKS:
  266. parent_clk_name = "slimbus_clk";
  267. break;
  268. case OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS:
  269. parent_clk_name = "dmic_sync_mux_ck";
  270. break;
  271. default:
  272. dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id);
  273. return -EINVAL;
  274. }
  275. parent_clk = clk_get(dmic->dev, parent_clk_name);
  276. if (IS_ERR(parent_clk)) {
  277. dev_err(dmic->dev, "can't get %s\n", parent_clk_name);
  278. return -ENODEV;
  279. }
  280. mutex_lock(&dmic->mutex);
  281. if (dmic->active) {
  282. /* disable clock while reparenting */
  283. pm_runtime_put_sync(dmic->dev);
  284. ret = clk_set_parent(dmic->fclk, parent_clk);
  285. pm_runtime_get_sync(dmic->dev);
  286. } else {
  287. ret = clk_set_parent(dmic->fclk, parent_clk);
  288. }
  289. mutex_unlock(&dmic->mutex);
  290. if (ret < 0) {
  291. dev_err(dmic->dev, "re-parent failed\n");
  292. goto err_busy;
  293. }
  294. dmic->sysclk = clk_id;
  295. dmic->fclk_freq = freq;
  296. err_busy:
  297. clk_put(parent_clk);
  298. return ret;
  299. }
  300. static int omap_dmic_select_outclk(struct omap_dmic *dmic, int clk_id,
  301. unsigned int freq)
  302. {
  303. int ret = 0;
  304. if (clk_id != OMAP_DMIC_ABE_DMIC_CLK) {
  305. dev_err(dmic->dev, "output clk_id (%d) not supported\n",
  306. clk_id);
  307. return -EINVAL;
  308. }
  309. switch (freq) {
  310. case 1536000:
  311. case 2400000:
  312. case 3072000:
  313. case 3840000:
  314. dmic->out_freq = freq;
  315. break;
  316. default:
  317. dev_err(dmic->dev, "invalid out frequency: %dHz\n", freq);
  318. dmic->out_freq = 0;
  319. ret = -EINVAL;
  320. }
  321. return ret;
  322. }
  323. static int omap_dmic_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
  324. unsigned int freq, int dir)
  325. {
  326. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  327. if (dir == SND_SOC_CLOCK_IN)
  328. return omap_dmic_select_fclk(dmic, clk_id, freq);
  329. else if (dir == SND_SOC_CLOCK_OUT)
  330. return omap_dmic_select_outclk(dmic, clk_id, freq);
  331. dev_err(dmic->dev, "invalid clock direction (%d)\n", dir);
  332. return -EINVAL;
  333. }
  334. static const struct snd_soc_dai_ops omap_dmic_dai_ops = {
  335. .startup = omap_dmic_dai_startup,
  336. .shutdown = omap_dmic_dai_shutdown,
  337. .hw_params = omap_dmic_dai_hw_params,
  338. .prepare = omap_dmic_dai_prepare,
  339. .trigger = omap_dmic_dai_trigger,
  340. .set_sysclk = omap_dmic_set_dai_sysclk,
  341. };
  342. static int omap_dmic_probe(struct snd_soc_dai *dai)
  343. {
  344. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  345. pm_runtime_enable(dmic->dev);
  346. /* Disable lines while request is ongoing */
  347. pm_runtime_get_sync(dmic->dev);
  348. omap_dmic_write(dmic, OMAP_DMIC_CTRL_REG, 0x00);
  349. pm_runtime_put_sync(dmic->dev);
  350. /* Configure DMIC threshold value */
  351. dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
  352. snd_soc_dai_init_dma_data(dai, NULL, &dmic->dma_data);
  353. return 0;
  354. }
  355. static int omap_dmic_remove(struct snd_soc_dai *dai)
  356. {
  357. struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
  358. pm_runtime_disable(dmic->dev);
  359. return 0;
  360. }
  361. static struct snd_soc_dai_driver omap_dmic_dai = {
  362. .name = "omap-dmic",
  363. .probe = omap_dmic_probe,
  364. .remove = omap_dmic_remove,
  365. .capture = {
  366. .channels_min = 2,
  367. .channels_max = 6,
  368. .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
  369. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  370. .sig_bits = 24,
  371. },
  372. .ops = &omap_dmic_dai_ops,
  373. };
  374. static const struct snd_soc_component_driver omap_dmic_component = {
  375. .name = "omap-dmic",
  376. };
  377. static int asoc_dmic_probe(struct platform_device *pdev)
  378. {
  379. struct omap_dmic *dmic;
  380. struct resource *res;
  381. int ret;
  382. dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
  383. if (!dmic)
  384. return -ENOMEM;
  385. platform_set_drvdata(pdev, dmic);
  386. dmic->dev = &pdev->dev;
  387. dmic->sysclk = OMAP_DMIC_SYSCLK_SYNC_MUX_CLKS;
  388. mutex_init(&dmic->mutex);
  389. dmic->fclk = devm_clk_get(dmic->dev, "fck");
  390. if (IS_ERR(dmic->fclk)) {
  391. dev_err(dmic->dev, "cant get fck\n");
  392. return -ENODEV;
  393. }
  394. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
  395. if (!res) {
  396. dev_err(dmic->dev, "invalid dma memory resource\n");
  397. return -ENODEV;
  398. }
  399. dmic->dma_data.addr = res->start + OMAP_DMIC_DATA_REG;
  400. dmic->dma_data.filter_data = "up_link";
  401. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
  402. dmic->io_base = devm_ioremap_resource(&pdev->dev, res);
  403. if (IS_ERR(dmic->io_base))
  404. return PTR_ERR(dmic->io_base);
  405. ret = devm_snd_soc_register_component(&pdev->dev,
  406. &omap_dmic_component,
  407. &omap_dmic_dai, 1);
  408. if (ret)
  409. return ret;
  410. ret = omap_pcm_platform_register(&pdev->dev);
  411. if (ret)
  412. return ret;
  413. return 0;
  414. }
  415. static const struct of_device_id omap_dmic_of_match[] = {
  416. { .compatible = "ti,omap4-dmic", },
  417. { }
  418. };
  419. MODULE_DEVICE_TABLE(of, omap_dmic_of_match);
  420. static struct platform_driver asoc_dmic_driver = {
  421. .driver = {
  422. .name = "omap-dmic",
  423. .of_match_table = omap_dmic_of_match,
  424. },
  425. .probe = asoc_dmic_probe,
  426. };
  427. module_platform_driver(asoc_dmic_driver);
  428. MODULE_ALIAS("platform:omap-dmic");
  429. MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
  430. MODULE_DESCRIPTION("OMAP DMIC ASoC Interface");
  431. MODULE_LICENSE("GPL");