tfa9879.h 6.1 KB

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  1. /*
  2. * tfa9879.h -- driver for NXP Semiconductors TFA9879
  3. *
  4. * Copyright (C) 2014 Axentia Technologies AB
  5. * Author: Peter Rosin <peda@axentia.se>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. */
  13. #ifndef _TFA9879_H
  14. #define _TFA9879_H
  15. #define TFA9879_DEVICE_CONTROL 0x00
  16. #define TFA9879_SERIAL_INTERFACE_1 0x01
  17. #define TFA9879_PCM_IOM2_FORMAT_1 0x02
  18. #define TFA9879_SERIAL_INTERFACE_2 0x03
  19. #define TFA9879_PCM_IOM2_FORMAT_2 0x04
  20. #define TFA9879_EQUALIZER_A1 0x05
  21. #define TFA9879_EQUALIZER_A2 0x06
  22. #define TFA9879_EQUALIZER_B1 0x07
  23. #define TFA9879_EQUALIZER_B2 0x08
  24. #define TFA9879_EQUALIZER_C1 0x09
  25. #define TFA9879_EQUALIZER_C2 0x0a
  26. #define TFA9879_EQUALIZER_D1 0x0b
  27. #define TFA9879_EQUALIZER_D2 0x0c
  28. #define TFA9879_EQUALIZER_E1 0x0d
  29. #define TFA9879_EQUALIZER_E2 0x0e
  30. #define TFA9879_BYPASS_CONTROL 0x0f
  31. #define TFA9879_DYNAMIC_RANGE_COMPR 0x10
  32. #define TFA9879_BASS_TREBLE 0x11
  33. #define TFA9879_HIGH_PASS_FILTER 0x12
  34. #define TFA9879_VOLUME_CONTROL 0x13
  35. #define TFA9879_MISC_CONTROL 0x14
  36. #define TFA9879_MISC_STATUS 0x15
  37. /* TFA9879_DEVICE_CONTROL */
  38. #define TFA9879_INPUT_SEL_MASK 0x0010
  39. #define TFA9879_INPUT_SEL_SHIFT 4
  40. #define TFA9879_OPMODE_MASK 0x0008
  41. #define TFA9879_OPMODE_SHIFT 3
  42. #define TFA9879_RESET_MASK 0x0002
  43. #define TFA9879_RESET_SHIFT 1
  44. #define TFA9879_POWERUP_MASK 0x0001
  45. #define TFA9879_POWERUP_SHIFT 0
  46. /* TFA9879_SERIAL_INTERFACE */
  47. #define TFA9879_MONO_SEL_MASK 0x0c00
  48. #define TFA9879_MONO_SEL_SHIFT 10
  49. #define TFA9879_MONO_SEL_LEFT 0
  50. #define TFA9879_MONO_SEL_RIGHT 1
  51. #define TFA9879_MONO_SEL_BOTH 2
  52. #define TFA9879_I2S_FS_MASK 0x03c0
  53. #define TFA9879_I2S_FS_SHIFT 6
  54. #define TFA9879_I2S_FS_8000 0
  55. #define TFA9879_I2S_FS_11025 1
  56. #define TFA9879_I2S_FS_12000 2
  57. #define TFA9879_I2S_FS_16000 3
  58. #define TFA9879_I2S_FS_22050 4
  59. #define TFA9879_I2S_FS_24000 5
  60. #define TFA9879_I2S_FS_32000 6
  61. #define TFA9879_I2S_FS_44100 7
  62. #define TFA9879_I2S_FS_48000 8
  63. #define TFA9879_I2S_FS_64000 9
  64. #define TFA9879_I2S_FS_88200 10
  65. #define TFA9879_I2S_FS_96000 11
  66. #define TFA9879_I2S_SET_MASK 0x0038
  67. #define TFA9879_I2S_SET_SHIFT 3
  68. #define TFA9879_I2S_SET_MSB_J_24 2
  69. #define TFA9879_I2S_SET_I2S_24 3
  70. #define TFA9879_I2S_SET_LSB_J_16 4
  71. #define TFA9879_I2S_SET_LSB_J_18 5
  72. #define TFA9879_I2S_SET_LSB_J_20 6
  73. #define TFA9879_I2S_SET_LSB_J_24 7
  74. #define TFA9879_SCK_POL_MASK 0x0004
  75. #define TFA9879_SCK_POL_SHIFT 2
  76. #define TFA9879_SCK_POL_NORMAL 0
  77. #define TFA9879_SCK_POL_INVERSE 1
  78. #define TFA9879_I_MODE_MASK 0x0003
  79. #define TFA9879_I_MODE_SHIFT 0
  80. #define TFA9879_I_MODE_I2S 0
  81. #define TFA9879_I_MODE_PCM_IOM2_SHORT 1
  82. #define TFA9879_I_MODE_PCM_IOM2_LONG 2
  83. /* TFA9879_PCM_IOM2_FORMAT */
  84. #define TFA9879_PCM_FS_MASK 0x0800
  85. #define TFA9879_PCM_FS_SHIFT 11
  86. #define TFA9879_A_LAW_MASK 0x0400
  87. #define TFA9879_A_LAW_SHIFT 10
  88. #define TFA9879_PCM_COMP_MASK 0x0200
  89. #define TFA9879_PCM_COMP_SHIFT 9
  90. #define TFA9879_PCM_DL_MASK 0x0100
  91. #define TFA9879_PCM_DL_SHIFT 8
  92. #define TFA9879_D1_SLOT_MASK 0x00f0
  93. #define TFA9879_D1_SLOT_SHIFT 4
  94. #define TFA9879_D2_SLOT_MASK 0x000f
  95. #define TFA9879_D2_SLOT_SHIFT 0
  96. /* TFA9879_EQUALIZER_X1 */
  97. #define TFA9879_T1_MASK 0x8000
  98. #define TFA9879_T1_SHIFT 15
  99. #define TFA9879_K1M_MASK 0x7ff0
  100. #define TFA9879_K1M_SHIFT 4
  101. #define TFA9879_K1E_MASK 0x000f
  102. #define TFA9879_K1E_SHIFT 0
  103. /* TFA9879_EQUALIZER_X2 */
  104. #define TFA9879_T2_MASK 0x8000
  105. #define TFA9879_T2_SHIFT 15
  106. #define TFA9879_K2M_MASK 0x7800
  107. #define TFA9879_K2M_SHIFT 11
  108. #define TFA9879_K2E_MASK 0x0700
  109. #define TFA9879_K2E_SHIFT 8
  110. #define TFA9879_K0_MASK 0x00fe
  111. #define TFA9879_K0_SHIFT 1
  112. #define TFA9879_S_MASK 0x0001
  113. #define TFA9879_S_SHIFT 0
  114. /* TFA9879_BYPASS_CONTROL */
  115. #define TFA9879_L_OCP_MASK 0x00c0
  116. #define TFA9879_L_OCP_SHIFT 6
  117. #define TFA9879_L_OTP_MASK 0x0030
  118. #define TFA9879_L_OTP_SHIFT 4
  119. #define TFA9879_CLIPCTRL_MASK 0x0008
  120. #define TFA9879_CLIPCTRL_SHIFT 3
  121. #define TFA9879_HPF_BP_MASK 0x0004
  122. #define TFA9879_HPF_BP_SHIFT 2
  123. #define TFA9879_DRC_BP_MASK 0x0002
  124. #define TFA9879_DRC_BP_SHIFT 1
  125. #define TFA9879_EQ_BP_MASK 0x0001
  126. #define TFA9879_EQ_BP_SHIFT 0
  127. /* TFA9879_DYNAMIC_RANGE_COMPR */
  128. #define TFA9879_AT_LVL_MASK 0xf000
  129. #define TFA9879_AT_LVL_SHIFT 12
  130. #define TFA9879_AT_RATE_MASK 0x0f00
  131. #define TFA9879_AT_RATE_SHIFT 8
  132. #define TFA9879_RL_LVL_MASK 0x00f0
  133. #define TFA9879_RL_LVL_SHIFT 4
  134. #define TFA9879_RL_RATE_MASK 0x000f
  135. #define TFA9879_RL_RATE_SHIFT 0
  136. /* TFA9879_BASS_TREBLE */
  137. #define TFA9879_G_TRBLE_MASK 0x3e00
  138. #define TFA9879_G_TRBLE_SHIFT 9
  139. #define TFA9879_F_TRBLE_MASK 0x0180
  140. #define TFA9879_F_TRBLE_SHIFT 7
  141. #define TFA9879_G_BASS_MASK 0x007c
  142. #define TFA9879_G_BASS_SHIFT 2
  143. #define TFA9879_F_BASS_MASK 0x0003
  144. #define TFA9879_F_BASS_SHIFT 0
  145. /* TFA9879_HIGH_PASS_FILTER */
  146. #define TFA9879_HP_CTRL_MASK 0x00ff
  147. #define TFA9879_HP_CTRL_SHIFT 0
  148. /* TFA9879_VOLUME_CONTROL */
  149. #define TFA9879_ZR_CRSS_MASK 0x1000
  150. #define TFA9879_ZR_CRSS_SHIFT 12
  151. #define TFA9879_VOL_MASK 0x00ff
  152. #define TFA9879_VOL_SHIFT 0
  153. /* TFA9879_MISC_CONTROL */
  154. #define TFA9879_DE_PHAS_MASK 0x0c00
  155. #define TFA9879_DE_PHAS_SHIFT 10
  156. #define TFA9879_H_MUTE_MASK 0x0200
  157. #define TFA9879_H_MUTE_SHIFT 9
  158. #define TFA9879_S_MUTE_MASK 0x0100
  159. #define TFA9879_S_MUTE_SHIFT 8
  160. #define TFA9879_P_LIM_MASK 0x00ff
  161. #define TFA9879_P_LIM_SHIFT 0
  162. /* TFA9879_MISC_STATUS */
  163. #define TFA9879_PS_MASK 0x4000
  164. #define TFA9879_PS_SHIFT 14
  165. #define TFA9879_PORA_MASK 0x2000
  166. #define TFA9879_PORA_SHIFT 13
  167. #define TFA9879_AMP_MASK 0x0600
  168. #define TFA9879_AMP_SHIFT 9
  169. #define TFA9879_IBP_2_MASK 0x0100
  170. #define TFA9879_IBP_2_SHIFT 8
  171. #define TFA9879_OFP_2_MASK 0x0080
  172. #define TFA9879_OFP_2_SHIFT 7
  173. #define TFA9879_UFP_2_MASK 0x0040
  174. #define TFA9879_UFP_2_SHIFT 6
  175. #define TFA9879_IBP_1_MASK 0x0020
  176. #define TFA9879_IBP_1_SHIFT 5
  177. #define TFA9879_OFP_1_MASK 0x0010
  178. #define TFA9879_OFP_1_SHIFT 4
  179. #define TFA9879_UFP_1_MASK 0x0008
  180. #define TFA9879_UFP_1_SHIFT 3
  181. #define TFA9879_OCPOKA_MASK 0x0004
  182. #define TFA9879_OCPOKA_SHIFT 2
  183. #define TFA9879_OCPOKB_MASK 0x0002
  184. #define TFA9879_OCPOKB_SHIFT 1
  185. #define TFA9879_OTPOK_MASK 0x0001
  186. #define TFA9879_OTPOK_SHIFT 0
  187. #endif