rt298.c 32 KB

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  1. /*
  2. * rt298.c -- RT298 ALSA SoC audio codec driver
  3. *
  4. * Copyright 2015 Realtek Semiconductor Corp.
  5. * Author: Bard Liao <bardliao@realtek.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/dmi.h>
  20. #include <linux/acpi.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/jack.h>
  29. #include <linux/workqueue.h>
  30. #include <sound/rt298.h>
  31. #include "rl6347a.h"
  32. #include "rt298.h"
  33. #define RT298_VENDOR_ID 0x10ec0298
  34. struct rt298_priv {
  35. struct reg_default *index_cache;
  36. int index_cache_size;
  37. struct regmap *regmap;
  38. struct snd_soc_codec *codec;
  39. struct rt298_platform_data pdata;
  40. struct i2c_client *i2c;
  41. struct snd_soc_jack *jack;
  42. struct delayed_work jack_detect_work;
  43. int sys_clk;
  44. int clk_id;
  45. int is_hp_in;
  46. };
  47. static const struct reg_default rt298_index_def[] = {
  48. { 0x01, 0xa5a8 },
  49. { 0x02, 0x8e95 },
  50. { 0x03, 0x0002 },
  51. { 0x04, 0xaf67 },
  52. { 0x08, 0x200f },
  53. { 0x09, 0xd010 },
  54. { 0x0a, 0x0100 },
  55. { 0x0b, 0x0000 },
  56. { 0x0d, 0x2800 },
  57. { 0x0f, 0x0022 },
  58. { 0x19, 0x0217 },
  59. { 0x20, 0x0020 },
  60. { 0x33, 0x0208 },
  61. { 0x46, 0x0300 },
  62. { 0x49, 0x4004 },
  63. { 0x4f, 0x50c9 },
  64. { 0x50, 0x3000 },
  65. { 0x63, 0x1b02 },
  66. { 0x67, 0x1111 },
  67. { 0x68, 0x1016 },
  68. { 0x69, 0x273f },
  69. };
  70. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt298_index_def)
  71. static const struct reg_default rt298_reg[] = {
  72. { 0x00170500, 0x00000400 },
  73. { 0x00220000, 0x00000031 },
  74. { 0x00239000, 0x0000007f },
  75. { 0x0023a000, 0x0000007f },
  76. { 0x00270500, 0x00000400 },
  77. { 0x00370500, 0x00000400 },
  78. { 0x00870500, 0x00000400 },
  79. { 0x00920000, 0x00000031 },
  80. { 0x00935000, 0x000000c3 },
  81. { 0x00936000, 0x000000c3 },
  82. { 0x00970500, 0x00000400 },
  83. { 0x00b37000, 0x00000097 },
  84. { 0x00b37200, 0x00000097 },
  85. { 0x00b37300, 0x00000097 },
  86. { 0x00c37000, 0x00000000 },
  87. { 0x00c37100, 0x00000080 },
  88. { 0x01270500, 0x00000400 },
  89. { 0x01370500, 0x00000400 },
  90. { 0x01371f00, 0x411111f0 },
  91. { 0x01439000, 0x00000080 },
  92. { 0x0143a000, 0x00000080 },
  93. { 0x01470700, 0x00000000 },
  94. { 0x01470500, 0x00000400 },
  95. { 0x01470c00, 0x00000000 },
  96. { 0x01470100, 0x00000000 },
  97. { 0x01837000, 0x00000000 },
  98. { 0x01870500, 0x00000400 },
  99. { 0x02050000, 0x00000000 },
  100. { 0x02139000, 0x00000080 },
  101. { 0x0213a000, 0x00000080 },
  102. { 0x02170100, 0x00000000 },
  103. { 0x02170500, 0x00000400 },
  104. { 0x02170700, 0x00000000 },
  105. { 0x02270100, 0x00000000 },
  106. { 0x02370100, 0x00000000 },
  107. { 0x01870700, 0x00000020 },
  108. { 0x00830000, 0x000000c3 },
  109. { 0x00930000, 0x000000c3 },
  110. { 0x01270700, 0x00000000 },
  111. };
  112. static bool rt298_volatile_register(struct device *dev, unsigned int reg)
  113. {
  114. switch (reg) {
  115. case 0 ... 0xff:
  116. case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  117. case RT298_GET_HP_SENSE:
  118. case RT298_GET_MIC1_SENSE:
  119. case RT298_PROC_COEF:
  120. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
  121. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
  122. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
  123. return true;
  124. default:
  125. return false;
  126. }
  127. }
  128. static bool rt298_readable_register(struct device *dev, unsigned int reg)
  129. {
  130. switch (reg) {
  131. case 0 ... 0xff:
  132. case RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  133. case RT298_GET_HP_SENSE:
  134. case RT298_GET_MIC1_SENSE:
  135. case RT298_SET_AUDIO_POWER:
  136. case RT298_SET_HPO_POWER:
  137. case RT298_SET_SPK_POWER:
  138. case RT298_SET_DMIC1_POWER:
  139. case RT298_SPK_MUX:
  140. case RT298_HPO_MUX:
  141. case RT298_ADC0_MUX:
  142. case RT298_ADC1_MUX:
  143. case RT298_SET_MIC1:
  144. case RT298_SET_PIN_HPO:
  145. case RT298_SET_PIN_SPK:
  146. case RT298_SET_PIN_DMIC1:
  147. case RT298_SPK_EAPD:
  148. case RT298_SET_AMP_GAIN_HPO:
  149. case RT298_SET_DMIC2_DEFAULT:
  150. case RT298_DACL_GAIN:
  151. case RT298_DACR_GAIN:
  152. case RT298_ADCL_GAIN:
  153. case RT298_ADCR_GAIN:
  154. case RT298_MIC_GAIN:
  155. case RT298_SPOL_GAIN:
  156. case RT298_SPOR_GAIN:
  157. case RT298_HPOL_GAIN:
  158. case RT298_HPOR_GAIN:
  159. case RT298_F_DAC_SWITCH:
  160. case RT298_F_RECMIX_SWITCH:
  161. case RT298_REC_MIC_SWITCH:
  162. case RT298_REC_I2S_SWITCH:
  163. case RT298_REC_LINE_SWITCH:
  164. case RT298_REC_BEEP_SWITCH:
  165. case RT298_DAC_FORMAT:
  166. case RT298_ADC_FORMAT:
  167. case RT298_COEF_INDEX:
  168. case RT298_PROC_COEF:
  169. case RT298_SET_AMP_GAIN_ADC_IN1:
  170. case RT298_SET_AMP_GAIN_ADC_IN2:
  171. case RT298_SET_POWER(RT298_DAC_OUT1):
  172. case RT298_SET_POWER(RT298_DAC_OUT2):
  173. case RT298_SET_POWER(RT298_ADC_IN1):
  174. case RT298_SET_POWER(RT298_ADC_IN2):
  175. case RT298_SET_POWER(RT298_DMIC2):
  176. case RT298_SET_POWER(RT298_MIC1):
  177. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_MIC1, 0):
  178. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_SPK_OUT, 0):
  179. case VERB_CMD(AC_VERB_GET_EAPD_BTLENABLE, RT298_HP_OUT, 0):
  180. return true;
  181. default:
  182. return false;
  183. }
  184. }
  185. #ifdef CONFIG_PM
  186. static void rt298_index_sync(struct snd_soc_codec *codec)
  187. {
  188. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  189. int i;
  190. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  191. snd_soc_write(codec, rt298->index_cache[i].reg,
  192. rt298->index_cache[i].def);
  193. }
  194. }
  195. #endif
  196. static int rt298_support_power_controls[] = {
  197. RT298_DAC_OUT1,
  198. RT298_DAC_OUT2,
  199. RT298_ADC_IN1,
  200. RT298_ADC_IN2,
  201. RT298_MIC1,
  202. RT298_DMIC1,
  203. RT298_DMIC2,
  204. RT298_SPK_OUT,
  205. RT298_HP_OUT,
  206. };
  207. #define RT298_POWER_REG_LEN ARRAY_SIZE(rt298_support_power_controls)
  208. static int rt298_jack_detect(struct rt298_priv *rt298, bool *hp, bool *mic)
  209. {
  210. struct snd_soc_dapm_context *dapm;
  211. unsigned int val, buf;
  212. *hp = false;
  213. *mic = false;
  214. if (!rt298->codec)
  215. return -EINVAL;
  216. dapm = snd_soc_codec_get_dapm(rt298->codec);
  217. if (rt298->pdata.cbj_en) {
  218. regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
  219. *hp = buf & 0x80000000;
  220. if (*hp == rt298->is_hp_in)
  221. return -1;
  222. rt298->is_hp_in = *hp;
  223. if (*hp) {
  224. /* power on HV,VERF */
  225. regmap_update_bits(rt298->regmap,
  226. RT298_DC_GAIN, 0x200, 0x200);
  227. snd_soc_dapm_force_enable_pin(dapm, "HV");
  228. snd_soc_dapm_force_enable_pin(dapm, "VREF");
  229. /* power LDO1 */
  230. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  231. snd_soc_dapm_sync(dapm);
  232. regmap_update_bits(rt298->regmap,
  233. RT298_POWER_CTRL1, 0x1001, 0);
  234. regmap_update_bits(rt298->regmap,
  235. RT298_POWER_CTRL2, 0x4, 0x4);
  236. regmap_write(rt298->regmap, RT298_SET_MIC1, 0x24);
  237. msleep(50);
  238. regmap_update_bits(rt298->regmap,
  239. RT298_CBJ_CTRL1, 0xfcc0, 0xd400);
  240. msleep(300);
  241. regmap_read(rt298->regmap, RT298_CBJ_CTRL2, &val);
  242. if (0x0070 == (val & 0x0070)) {
  243. *mic = true;
  244. } else {
  245. regmap_update_bits(rt298->regmap,
  246. RT298_CBJ_CTRL1, 0xfcc0, 0xe400);
  247. msleep(300);
  248. regmap_read(rt298->regmap,
  249. RT298_CBJ_CTRL2, &val);
  250. if (0x0070 == (val & 0x0070))
  251. *mic = true;
  252. else
  253. *mic = false;
  254. }
  255. regmap_update_bits(rt298->regmap,
  256. RT298_DC_GAIN, 0x200, 0x0);
  257. } else {
  258. *mic = false;
  259. regmap_write(rt298->regmap, RT298_SET_MIC1, 0x20);
  260. regmap_update_bits(rt298->regmap,
  261. RT298_CBJ_CTRL1, 0x0400, 0x0000);
  262. }
  263. } else {
  264. regmap_read(rt298->regmap, RT298_GET_HP_SENSE, &buf);
  265. *hp = buf & 0x80000000;
  266. regmap_read(rt298->regmap, RT298_GET_MIC1_SENSE, &buf);
  267. *mic = buf & 0x80000000;
  268. }
  269. snd_soc_dapm_disable_pin(dapm, "HV");
  270. snd_soc_dapm_disable_pin(dapm, "VREF");
  271. if (!*hp)
  272. snd_soc_dapm_disable_pin(dapm, "LDO1");
  273. snd_soc_dapm_sync(dapm);
  274. pr_debug("*hp = %d *mic = %d\n", *hp, *mic);
  275. return 0;
  276. }
  277. static void rt298_jack_detect_work(struct work_struct *work)
  278. {
  279. struct rt298_priv *rt298 =
  280. container_of(work, struct rt298_priv, jack_detect_work.work);
  281. int status = 0;
  282. bool hp = false;
  283. bool mic = false;
  284. if (rt298_jack_detect(rt298, &hp, &mic) < 0)
  285. return;
  286. if (hp == true)
  287. status |= SND_JACK_HEADPHONE;
  288. if (mic == true)
  289. status |= SND_JACK_MICROPHONE;
  290. snd_soc_jack_report(rt298->jack, status,
  291. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  292. }
  293. int rt298_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
  294. {
  295. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  296. rt298->jack = jack;
  297. /* Send an initial empty report */
  298. snd_soc_jack_report(rt298->jack, 0,
  299. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  300. return 0;
  301. }
  302. EXPORT_SYMBOL_GPL(rt298_mic_detect);
  303. static int is_mclk_mode(struct snd_soc_dapm_widget *source,
  304. struct snd_soc_dapm_widget *sink)
  305. {
  306. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
  307. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  308. if (rt298->clk_id == RT298_SCLK_S_MCLK)
  309. return 1;
  310. else
  311. return 0;
  312. }
  313. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  314. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  315. static const struct snd_kcontrol_new rt298_snd_controls[] = {
  316. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT298_DACL_GAIN,
  317. RT298_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  318. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT298_ADCL_GAIN,
  319. RT298_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  320. SOC_SINGLE_TLV("AMIC Volume", RT298_MIC_GAIN,
  321. 0, 0x3, 0, mic_vol_tlv),
  322. SOC_DOUBLE_R("Speaker Playback Switch", RT298_SPOL_GAIN,
  323. RT298_SPOR_GAIN, RT298_MUTE_SFT, 1, 1),
  324. };
  325. /* Digital Mixer */
  326. static const struct snd_kcontrol_new rt298_front_mix[] = {
  327. SOC_DAPM_SINGLE("DAC Switch", RT298_F_DAC_SWITCH,
  328. RT298_MUTE_SFT, 1, 1),
  329. SOC_DAPM_SINGLE("RECMIX Switch", RT298_F_RECMIX_SWITCH,
  330. RT298_MUTE_SFT, 1, 1),
  331. };
  332. /* Analog Input Mixer */
  333. static const struct snd_kcontrol_new rt298_rec_mix[] = {
  334. SOC_DAPM_SINGLE("Mic1 Switch", RT298_REC_MIC_SWITCH,
  335. RT298_MUTE_SFT, 1, 1),
  336. SOC_DAPM_SINGLE("I2S Switch", RT298_REC_I2S_SWITCH,
  337. RT298_MUTE_SFT, 1, 1),
  338. SOC_DAPM_SINGLE("Line1 Switch", RT298_REC_LINE_SWITCH,
  339. RT298_MUTE_SFT, 1, 1),
  340. SOC_DAPM_SINGLE("Beep Switch", RT298_REC_BEEP_SWITCH,
  341. RT298_MUTE_SFT, 1, 1),
  342. };
  343. static const struct snd_kcontrol_new spo_enable_control =
  344. SOC_DAPM_SINGLE("Switch", RT298_SET_PIN_SPK,
  345. RT298_SET_PIN_SFT, 1, 0);
  346. static const struct snd_kcontrol_new hpol_enable_control =
  347. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOL_GAIN,
  348. RT298_MUTE_SFT, 1, 1);
  349. static const struct snd_kcontrol_new hpor_enable_control =
  350. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT298_HPOR_GAIN,
  351. RT298_MUTE_SFT, 1, 1);
  352. /* ADC0 source */
  353. static const char * const rt298_adc_src[] = {
  354. "Mic", "RECMIX", "Dmic"
  355. };
  356. static const int rt298_adc_values[] = {
  357. 0, 4, 5,
  358. };
  359. static SOC_VALUE_ENUM_SINGLE_DECL(
  360. rt298_adc0_enum, RT298_ADC0_MUX, RT298_ADC_SEL_SFT,
  361. RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
  362. static const struct snd_kcontrol_new rt298_adc0_mux =
  363. SOC_DAPM_ENUM("ADC 0 source", rt298_adc0_enum);
  364. static SOC_VALUE_ENUM_SINGLE_DECL(
  365. rt298_adc1_enum, RT298_ADC1_MUX, RT298_ADC_SEL_SFT,
  366. RT298_ADC_SEL_MASK, rt298_adc_src, rt298_adc_values);
  367. static const struct snd_kcontrol_new rt298_adc1_mux =
  368. SOC_DAPM_ENUM("ADC 1 source", rt298_adc1_enum);
  369. static const char * const rt298_dac_src[] = {
  370. "Front", "Surround"
  371. };
  372. /* HP-OUT source */
  373. static SOC_ENUM_SINGLE_DECL(rt298_hpo_enum, RT298_HPO_MUX,
  374. 0, rt298_dac_src);
  375. static const struct snd_kcontrol_new rt298_hpo_mux =
  376. SOC_DAPM_ENUM("HPO source", rt298_hpo_enum);
  377. /* SPK-OUT source */
  378. static SOC_ENUM_SINGLE_DECL(rt298_spo_enum, RT298_SPK_MUX,
  379. 0, rt298_dac_src);
  380. static const struct snd_kcontrol_new rt298_spo_mux =
  381. SOC_DAPM_ENUM("SPO source", rt298_spo_enum);
  382. static int rt298_spk_event(struct snd_soc_dapm_widget *w,
  383. struct snd_kcontrol *kcontrol, int event)
  384. {
  385. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  386. switch (event) {
  387. case SND_SOC_DAPM_POST_PMU:
  388. snd_soc_write(codec,
  389. RT298_SPK_EAPD, RT298_SET_EAPD_HIGH);
  390. break;
  391. case SND_SOC_DAPM_PRE_PMD:
  392. snd_soc_write(codec,
  393. RT298_SPK_EAPD, RT298_SET_EAPD_LOW);
  394. break;
  395. default:
  396. return 0;
  397. }
  398. return 0;
  399. }
  400. static int rt298_set_dmic1_event(struct snd_soc_dapm_widget *w,
  401. struct snd_kcontrol *kcontrol, int event)
  402. {
  403. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  404. switch (event) {
  405. case SND_SOC_DAPM_POST_PMU:
  406. snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0x20);
  407. break;
  408. case SND_SOC_DAPM_PRE_PMD:
  409. snd_soc_write(codec, RT298_SET_PIN_DMIC1, 0);
  410. break;
  411. default:
  412. return 0;
  413. }
  414. return 0;
  415. }
  416. static int rt298_adc_event(struct snd_soc_dapm_widget *w,
  417. struct snd_kcontrol *kcontrol, int event)
  418. {
  419. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  420. unsigned int nid;
  421. nid = (w->reg >> 20) & 0xff;
  422. switch (event) {
  423. case SND_SOC_DAPM_POST_PMU:
  424. snd_soc_update_bits(codec,
  425. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  426. 0x7080, 0x7000);
  427. /* If MCLK doesn't exist, reset AD filter */
  428. if (!(snd_soc_read(codec, RT298_VAD_CTRL) & 0x200)) {
  429. pr_info("NO MCLK\n");
  430. switch (nid) {
  431. case RT298_ADC_IN1:
  432. snd_soc_update_bits(codec,
  433. RT298_D_FILTER_CTRL, 0x2, 0x2);
  434. mdelay(10);
  435. snd_soc_update_bits(codec,
  436. RT298_D_FILTER_CTRL, 0x2, 0x0);
  437. break;
  438. case RT298_ADC_IN2:
  439. snd_soc_update_bits(codec,
  440. RT298_D_FILTER_CTRL, 0x4, 0x4);
  441. mdelay(10);
  442. snd_soc_update_bits(codec,
  443. RT298_D_FILTER_CTRL, 0x4, 0x0);
  444. break;
  445. }
  446. }
  447. break;
  448. case SND_SOC_DAPM_PRE_PMD:
  449. snd_soc_update_bits(codec,
  450. VERB_CMD(AC_VERB_SET_AMP_GAIN_MUTE, nid, 0),
  451. 0x7080, 0x7080);
  452. break;
  453. default:
  454. return 0;
  455. }
  456. return 0;
  457. }
  458. static int rt298_mic1_event(struct snd_soc_dapm_widget *w,
  459. struct snd_kcontrol *kcontrol, int event)
  460. {
  461. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  462. switch (event) {
  463. case SND_SOC_DAPM_PRE_PMU:
  464. snd_soc_update_bits(codec,
  465. RT298_A_BIAS_CTRL3, 0xc000, 0x8000);
  466. snd_soc_update_bits(codec,
  467. RT298_A_BIAS_CTRL2, 0xc000, 0x8000);
  468. break;
  469. case SND_SOC_DAPM_POST_PMD:
  470. snd_soc_update_bits(codec,
  471. RT298_A_BIAS_CTRL3, 0xc000, 0x0000);
  472. snd_soc_update_bits(codec,
  473. RT298_A_BIAS_CTRL2, 0xc000, 0x0000);
  474. break;
  475. default:
  476. return 0;
  477. }
  478. return 0;
  479. }
  480. static const struct snd_soc_dapm_widget rt298_dapm_widgets[] = {
  481. SND_SOC_DAPM_SUPPLY_S("HV", 1, RT298_POWER_CTRL1,
  482. 12, 1, NULL, 0),
  483. SND_SOC_DAPM_SUPPLY("VREF", RT298_POWER_CTRL1,
  484. 0, 1, NULL, 0),
  485. SND_SOC_DAPM_SUPPLY_S("BG_MBIAS", 1, RT298_POWER_CTRL2,
  486. 1, 0, NULL, 0),
  487. SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT298_POWER_CTRL2,
  488. 2, 0, NULL, 0),
  489. SND_SOC_DAPM_SUPPLY_S("LDO2", 1, RT298_POWER_CTRL2,
  490. 3, 0, NULL, 0),
  491. SND_SOC_DAPM_SUPPLY_S("VREF1", 1, RT298_POWER_CTRL2,
  492. 4, 1, NULL, 0),
  493. SND_SOC_DAPM_SUPPLY_S("LV", 2, RT298_POWER_CTRL1,
  494. 13, 1, NULL, 0),
  495. SND_SOC_DAPM_SUPPLY("MCLK MODE", RT298_PLL_CTRL1,
  496. 5, 0, NULL, 0),
  497. SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
  498. 0, 0, rt298_mic1_event, SND_SOC_DAPM_PRE_PMU |
  499. SND_SOC_DAPM_POST_PMD),
  500. /* Input Lines */
  501. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  502. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  503. SND_SOC_DAPM_INPUT("MIC1"),
  504. SND_SOC_DAPM_INPUT("LINE1"),
  505. SND_SOC_DAPM_INPUT("Beep"),
  506. /* DMIC */
  507. SND_SOC_DAPM_PGA_E("DMIC1", RT298_SET_POWER(RT298_DMIC1), 0, 1,
  508. NULL, 0, rt298_set_dmic1_event,
  509. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  510. SND_SOC_DAPM_PGA("DMIC2", RT298_SET_POWER(RT298_DMIC2), 0, 1,
  511. NULL, 0),
  512. SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
  513. 0, 0, NULL, 0),
  514. /* REC Mixer */
  515. SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
  516. rt298_rec_mix, ARRAY_SIZE(rt298_rec_mix)),
  517. /* ADCs */
  518. SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
  519. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  520. /* ADC Mux */
  521. SND_SOC_DAPM_MUX_E("ADC 0 Mux", RT298_SET_POWER(RT298_ADC_IN1), 0, 1,
  522. &rt298_adc0_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
  523. SND_SOC_DAPM_POST_PMU),
  524. SND_SOC_DAPM_MUX_E("ADC 1 Mux", RT298_SET_POWER(RT298_ADC_IN2), 0, 1,
  525. &rt298_adc1_mux, rt298_adc_event, SND_SOC_DAPM_PRE_PMD |
  526. SND_SOC_DAPM_POST_PMU),
  527. /* Audio Interface */
  528. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  529. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  530. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  531. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  532. /* Output Side */
  533. /* DACs */
  534. SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
  535. SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
  536. /* Output Mux */
  537. SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt298_spo_mux),
  538. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt298_hpo_mux),
  539. SND_SOC_DAPM_SUPPLY("HP Power", RT298_SET_PIN_HPO,
  540. RT298_SET_PIN_SFT, 0, NULL, 0),
  541. /* Output Mixer */
  542. SND_SOC_DAPM_MIXER("Front", RT298_SET_POWER(RT298_DAC_OUT1), 0, 1,
  543. rt298_front_mix, ARRAY_SIZE(rt298_front_mix)),
  544. SND_SOC_DAPM_PGA("Surround", RT298_SET_POWER(RT298_DAC_OUT2), 0, 1,
  545. NULL, 0),
  546. /* Output Pga */
  547. SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
  548. &spo_enable_control, rt298_spk_event,
  549. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  550. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  551. &hpol_enable_control),
  552. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  553. &hpor_enable_control),
  554. /* Output Lines */
  555. SND_SOC_DAPM_OUTPUT("SPOL"),
  556. SND_SOC_DAPM_OUTPUT("SPOR"),
  557. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  558. SND_SOC_DAPM_OUTPUT("SPDIF"),
  559. };
  560. static const struct snd_soc_dapm_route rt298_dapm_routes[] = {
  561. {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
  562. {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
  563. {"Front", NULL, "MCLK MODE", is_mclk_mode},
  564. {"Surround", NULL, "MCLK MODE", is_mclk_mode},
  565. {"HP Power", NULL, "LDO1"},
  566. {"HP Power", NULL, "LDO2"},
  567. {"HP Power", NULL, "LV"},
  568. {"HP Power", NULL, "VREF1"},
  569. {"HP Power", NULL, "BG_MBIAS"},
  570. {"MIC1", NULL, "LDO1"},
  571. {"MIC1", NULL, "LDO2"},
  572. {"MIC1", NULL, "HV"},
  573. {"MIC1", NULL, "LV"},
  574. {"MIC1", NULL, "VREF"},
  575. {"MIC1", NULL, "VREF1"},
  576. {"MIC1", NULL, "BG_MBIAS"},
  577. {"MIC1", NULL, "MIC1 Input Buffer"},
  578. {"SPO", NULL, "LDO1"},
  579. {"SPO", NULL, "LDO2"},
  580. {"SPO", NULL, "HV"},
  581. {"SPO", NULL, "LV"},
  582. {"SPO", NULL, "VREF"},
  583. {"SPO", NULL, "VREF1"},
  584. {"SPO", NULL, "BG_MBIAS"},
  585. {"DMIC1", NULL, "DMIC1 Pin"},
  586. {"DMIC2", NULL, "DMIC2 Pin"},
  587. {"DMIC1", NULL, "DMIC Receiver"},
  588. {"DMIC2", NULL, "DMIC Receiver"},
  589. {"RECMIX", "Beep Switch", "Beep"},
  590. {"RECMIX", "Line1 Switch", "LINE1"},
  591. {"RECMIX", "Mic1 Switch", "MIC1"},
  592. {"ADC 0 Mux", "Dmic", "DMIC1"},
  593. {"ADC 0 Mux", "RECMIX", "RECMIX"},
  594. {"ADC 0 Mux", "Mic", "MIC1"},
  595. {"ADC 1 Mux", "Dmic", "DMIC2"},
  596. {"ADC 1 Mux", "RECMIX", "RECMIX"},
  597. {"ADC 1 Mux", "Mic", "MIC1"},
  598. {"ADC 0", NULL, "ADC 0 Mux"},
  599. {"ADC 1", NULL, "ADC 1 Mux"},
  600. {"AIF1TX", NULL, "ADC 0"},
  601. {"AIF2TX", NULL, "ADC 1"},
  602. {"DAC 0", NULL, "AIF1RX"},
  603. {"DAC 1", NULL, "AIF2RX"},
  604. {"Front", "DAC Switch", "DAC 0"},
  605. {"Front", "RECMIX Switch", "RECMIX"},
  606. {"Surround", NULL, "DAC 1"},
  607. {"SPK Mux", "Front", "Front"},
  608. {"SPK Mux", "Surround", "Surround"},
  609. {"HPO Mux", "Front", "Front"},
  610. {"HPO Mux", "Surround", "Surround"},
  611. {"SPO", "Switch", "SPK Mux"},
  612. {"HPO L", "Switch", "HPO Mux"},
  613. {"HPO R", "Switch", "HPO Mux"},
  614. {"HPO L", NULL, "HP Power"},
  615. {"HPO R", NULL, "HP Power"},
  616. {"SPOL", NULL, "SPO"},
  617. {"SPOR", NULL, "SPO"},
  618. {"HPO Pin", NULL, "HPO L"},
  619. {"HPO Pin", NULL, "HPO R"},
  620. };
  621. static int rt298_hw_params(struct snd_pcm_substream *substream,
  622. struct snd_pcm_hw_params *params,
  623. struct snd_soc_dai *dai)
  624. {
  625. struct snd_soc_codec *codec = dai->codec;
  626. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  627. unsigned int val = 0;
  628. int d_len_code;
  629. switch (params_rate(params)) {
  630. /* bit 14 0:48K 1:44.1K */
  631. case 44100:
  632. case 48000:
  633. break;
  634. default:
  635. dev_err(codec->dev, "Unsupported sample rate %d\n",
  636. params_rate(params));
  637. return -EINVAL;
  638. }
  639. switch (rt298->sys_clk) {
  640. case 12288000:
  641. case 24576000:
  642. if (params_rate(params) != 48000) {
  643. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  644. params_rate(params), rt298->sys_clk);
  645. return -EINVAL;
  646. }
  647. break;
  648. case 11289600:
  649. case 22579200:
  650. if (params_rate(params) != 44100) {
  651. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  652. params_rate(params), rt298->sys_clk);
  653. return -EINVAL;
  654. }
  655. break;
  656. }
  657. if (params_channels(params) <= 16) {
  658. /* bit 3:0 Number of Channel */
  659. val |= (params_channels(params) - 1);
  660. } else {
  661. dev_err(codec->dev, "Unsupported channels %d\n",
  662. params_channels(params));
  663. return -EINVAL;
  664. }
  665. d_len_code = 0;
  666. switch (params_width(params)) {
  667. /* bit 6:4 Bits per Sample */
  668. case 16:
  669. d_len_code = 0;
  670. val |= (0x1 << 4);
  671. break;
  672. case 32:
  673. d_len_code = 2;
  674. val |= (0x4 << 4);
  675. break;
  676. case 20:
  677. d_len_code = 1;
  678. val |= (0x2 << 4);
  679. break;
  680. case 24:
  681. d_len_code = 2;
  682. val |= (0x3 << 4);
  683. break;
  684. case 8:
  685. d_len_code = 3;
  686. break;
  687. default:
  688. return -EINVAL;
  689. }
  690. snd_soc_update_bits(codec,
  691. RT298_I2S_CTRL1, 0x0018, d_len_code << 3);
  692. dev_dbg(codec->dev, "format val = 0x%x\n", val);
  693. snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x407f, val);
  694. snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x407f, val);
  695. return 0;
  696. }
  697. static int rt298_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  698. {
  699. struct snd_soc_codec *codec = dai->codec;
  700. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  701. case SND_SOC_DAIFMT_CBM_CFM:
  702. snd_soc_update_bits(codec,
  703. RT298_I2S_CTRL1, 0x800, 0x800);
  704. break;
  705. case SND_SOC_DAIFMT_CBS_CFS:
  706. snd_soc_update_bits(codec,
  707. RT298_I2S_CTRL1, 0x800, 0x0);
  708. break;
  709. default:
  710. return -EINVAL;
  711. }
  712. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  713. case SND_SOC_DAIFMT_I2S:
  714. snd_soc_update_bits(codec,
  715. RT298_I2S_CTRL1, 0x300, 0x0);
  716. break;
  717. case SND_SOC_DAIFMT_LEFT_J:
  718. snd_soc_update_bits(codec,
  719. RT298_I2S_CTRL1, 0x300, 0x1 << 8);
  720. break;
  721. case SND_SOC_DAIFMT_DSP_A:
  722. snd_soc_update_bits(codec,
  723. RT298_I2S_CTRL1, 0x300, 0x2 << 8);
  724. break;
  725. case SND_SOC_DAIFMT_DSP_B:
  726. snd_soc_update_bits(codec,
  727. RT298_I2S_CTRL1, 0x300, 0x3 << 8);
  728. break;
  729. default:
  730. return -EINVAL;
  731. }
  732. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  733. snd_soc_update_bits(codec, RT298_DAC_FORMAT, 0x8000, 0);
  734. snd_soc_update_bits(codec, RT298_ADC_FORMAT, 0x8000, 0);
  735. return 0;
  736. }
  737. static int rt298_set_dai_sysclk(struct snd_soc_dai *dai,
  738. int clk_id, unsigned int freq, int dir)
  739. {
  740. struct snd_soc_codec *codec = dai->codec;
  741. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  742. dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
  743. if (RT298_SCLK_S_MCLK == clk_id) {
  744. snd_soc_update_bits(codec,
  745. RT298_I2S_CTRL2, 0x0100, 0x0);
  746. snd_soc_update_bits(codec,
  747. RT298_PLL_CTRL1, 0x20, 0x20);
  748. } else {
  749. snd_soc_update_bits(codec,
  750. RT298_I2S_CTRL2, 0x0100, 0x0100);
  751. snd_soc_update_bits(codec,
  752. RT298_PLL_CTRL1, 0x20, 0x0);
  753. }
  754. switch (freq) {
  755. case 19200000:
  756. if (RT298_SCLK_S_MCLK == clk_id) {
  757. dev_err(codec->dev, "Should not use MCLK\n");
  758. return -EINVAL;
  759. }
  760. snd_soc_update_bits(codec,
  761. RT298_I2S_CTRL2, 0x40, 0x40);
  762. break;
  763. case 24000000:
  764. if (RT298_SCLK_S_MCLK == clk_id) {
  765. dev_err(codec->dev, "Should not use MCLK\n");
  766. return -EINVAL;
  767. }
  768. snd_soc_update_bits(codec,
  769. RT298_I2S_CTRL2, 0x40, 0x0);
  770. break;
  771. case 12288000:
  772. case 11289600:
  773. snd_soc_update_bits(codec,
  774. RT298_I2S_CTRL2, 0x8, 0x0);
  775. snd_soc_update_bits(codec,
  776. RT298_CLK_DIV, 0xfc1e, 0x0004);
  777. break;
  778. case 24576000:
  779. case 22579200:
  780. snd_soc_update_bits(codec,
  781. RT298_I2S_CTRL2, 0x8, 0x8);
  782. snd_soc_update_bits(codec,
  783. RT298_CLK_DIV, 0xfc1e, 0x5406);
  784. break;
  785. default:
  786. dev_err(codec->dev, "Unsupported system clock\n");
  787. return -EINVAL;
  788. }
  789. rt298->sys_clk = freq;
  790. rt298->clk_id = clk_id;
  791. return 0;
  792. }
  793. static int rt298_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  794. {
  795. struct snd_soc_codec *codec = dai->codec;
  796. dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
  797. if (50 == ratio)
  798. snd_soc_update_bits(codec,
  799. RT298_I2S_CTRL1, 0x1000, 0x1000);
  800. else
  801. snd_soc_update_bits(codec,
  802. RT298_I2S_CTRL1, 0x1000, 0x0);
  803. return 0;
  804. }
  805. static int rt298_set_bias_level(struct snd_soc_codec *codec,
  806. enum snd_soc_bias_level level)
  807. {
  808. switch (level) {
  809. case SND_SOC_BIAS_PREPARE:
  810. if (SND_SOC_BIAS_STANDBY ==
  811. snd_soc_codec_get_bias_level(codec)) {
  812. snd_soc_write(codec,
  813. RT298_SET_AUDIO_POWER, AC_PWRST_D0);
  814. snd_soc_update_bits(codec, 0x0d, 0x200, 0x200);
  815. snd_soc_update_bits(codec, 0x52, 0x80, 0x0);
  816. mdelay(20);
  817. snd_soc_update_bits(codec, 0x0d, 0x200, 0x0);
  818. snd_soc_update_bits(codec, 0x52, 0x80, 0x80);
  819. }
  820. break;
  821. case SND_SOC_BIAS_STANDBY:
  822. snd_soc_write(codec,
  823. RT298_SET_AUDIO_POWER, AC_PWRST_D3);
  824. break;
  825. default:
  826. break;
  827. }
  828. return 0;
  829. }
  830. static irqreturn_t rt298_irq(int irq, void *data)
  831. {
  832. struct rt298_priv *rt298 = data;
  833. bool hp = false;
  834. bool mic = false;
  835. int ret, status = 0;
  836. ret = rt298_jack_detect(rt298, &hp, &mic);
  837. /* Clear IRQ */
  838. regmap_update_bits(rt298->regmap, RT298_IRQ_CTRL, 0x1, 0x1);
  839. if (ret == 0) {
  840. if (hp == true)
  841. status |= SND_JACK_HEADPHONE;
  842. if (mic == true)
  843. status |= SND_JACK_MICROPHONE;
  844. snd_soc_jack_report(rt298->jack, status,
  845. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  846. pm_wakeup_event(&rt298->i2c->dev, 300);
  847. }
  848. return IRQ_HANDLED;
  849. }
  850. static int rt298_probe(struct snd_soc_codec *codec)
  851. {
  852. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  853. rt298->codec = codec;
  854. if (rt298->i2c->irq) {
  855. regmap_update_bits(rt298->regmap,
  856. RT298_IRQ_CTRL, 0x2, 0x2);
  857. INIT_DELAYED_WORK(&rt298->jack_detect_work,
  858. rt298_jack_detect_work);
  859. schedule_delayed_work(&rt298->jack_detect_work,
  860. msecs_to_jiffies(1250));
  861. }
  862. return 0;
  863. }
  864. static int rt298_remove(struct snd_soc_codec *codec)
  865. {
  866. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  867. cancel_delayed_work_sync(&rt298->jack_detect_work);
  868. return 0;
  869. }
  870. #ifdef CONFIG_PM
  871. static int rt298_suspend(struct snd_soc_codec *codec)
  872. {
  873. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  874. rt298->is_hp_in = -1;
  875. regcache_cache_only(rt298->regmap, true);
  876. regcache_mark_dirty(rt298->regmap);
  877. return 0;
  878. }
  879. static int rt298_resume(struct snd_soc_codec *codec)
  880. {
  881. struct rt298_priv *rt298 = snd_soc_codec_get_drvdata(codec);
  882. regcache_cache_only(rt298->regmap, false);
  883. rt298_index_sync(codec);
  884. regcache_sync(rt298->regmap);
  885. return 0;
  886. }
  887. #else
  888. #define rt298_suspend NULL
  889. #define rt298_resume NULL
  890. #endif
  891. #define RT298_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  892. #define RT298_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  893. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  894. static const struct snd_soc_dai_ops rt298_aif_dai_ops = {
  895. .hw_params = rt298_hw_params,
  896. .set_fmt = rt298_set_dai_fmt,
  897. .set_sysclk = rt298_set_dai_sysclk,
  898. .set_bclk_ratio = rt298_set_bclk_ratio,
  899. };
  900. static struct snd_soc_dai_driver rt298_dai[] = {
  901. {
  902. .name = "rt298-aif1",
  903. .id = RT298_AIF1,
  904. .playback = {
  905. .stream_name = "AIF1 Playback",
  906. .channels_min = 1,
  907. .channels_max = 2,
  908. .rates = RT298_STEREO_RATES,
  909. .formats = RT298_FORMATS,
  910. },
  911. .capture = {
  912. .stream_name = "AIF1 Capture",
  913. .channels_min = 1,
  914. .channels_max = 2,
  915. .rates = RT298_STEREO_RATES,
  916. .formats = RT298_FORMATS,
  917. },
  918. .ops = &rt298_aif_dai_ops,
  919. .symmetric_rates = 1,
  920. },
  921. {
  922. .name = "rt298-aif2",
  923. .id = RT298_AIF2,
  924. .playback = {
  925. .stream_name = "AIF2 Playback",
  926. .channels_min = 1,
  927. .channels_max = 2,
  928. .rates = RT298_STEREO_RATES,
  929. .formats = RT298_FORMATS,
  930. },
  931. .capture = {
  932. .stream_name = "AIF2 Capture",
  933. .channels_min = 1,
  934. .channels_max = 2,
  935. .rates = RT298_STEREO_RATES,
  936. .formats = RT298_FORMATS,
  937. },
  938. .ops = &rt298_aif_dai_ops,
  939. .symmetric_rates = 1,
  940. },
  941. };
  942. static struct snd_soc_codec_driver soc_codec_dev_rt298 = {
  943. .probe = rt298_probe,
  944. .remove = rt298_remove,
  945. .suspend = rt298_suspend,
  946. .resume = rt298_resume,
  947. .set_bias_level = rt298_set_bias_level,
  948. .idle_bias_off = true,
  949. .component_driver = {
  950. .controls = rt298_snd_controls,
  951. .num_controls = ARRAY_SIZE(rt298_snd_controls),
  952. .dapm_widgets = rt298_dapm_widgets,
  953. .num_dapm_widgets = ARRAY_SIZE(rt298_dapm_widgets),
  954. .dapm_routes = rt298_dapm_routes,
  955. .num_dapm_routes = ARRAY_SIZE(rt298_dapm_routes),
  956. },
  957. };
  958. static const struct regmap_config rt298_regmap = {
  959. .reg_bits = 32,
  960. .val_bits = 32,
  961. .max_register = 0x02370100,
  962. .volatile_reg = rt298_volatile_register,
  963. .readable_reg = rt298_readable_register,
  964. .reg_write = rl6347a_hw_write,
  965. .reg_read = rl6347a_hw_read,
  966. .cache_type = REGCACHE_RBTREE,
  967. .reg_defaults = rt298_reg,
  968. .num_reg_defaults = ARRAY_SIZE(rt298_reg),
  969. };
  970. static const struct i2c_device_id rt298_i2c_id[] = {
  971. {"rt298", 0},
  972. {}
  973. };
  974. MODULE_DEVICE_TABLE(i2c, rt298_i2c_id);
  975. static const struct acpi_device_id rt298_acpi_match[] = {
  976. { "INT343A", 0 },
  977. {},
  978. };
  979. MODULE_DEVICE_TABLE(acpi, rt298_acpi_match);
  980. static const struct dmi_system_id force_combo_jack_table[] = {
  981. {
  982. .ident = "Intel Broxton P",
  983. .matches = {
  984. DMI_MATCH(DMI_SYS_VENDOR, "Intel Corp"),
  985. DMI_MATCH(DMI_PRODUCT_NAME, "Broxton P")
  986. }
  987. },
  988. { }
  989. };
  990. static int rt298_i2c_probe(struct i2c_client *i2c,
  991. const struct i2c_device_id *id)
  992. {
  993. struct rt298_platform_data *pdata = dev_get_platdata(&i2c->dev);
  994. struct rt298_priv *rt298;
  995. struct device *dev = &i2c->dev;
  996. const struct acpi_device_id *acpiid;
  997. int i, ret;
  998. rt298 = devm_kzalloc(&i2c->dev, sizeof(*rt298),
  999. GFP_KERNEL);
  1000. if (NULL == rt298)
  1001. return -ENOMEM;
  1002. rt298->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt298_regmap);
  1003. if (IS_ERR(rt298->regmap)) {
  1004. ret = PTR_ERR(rt298->regmap);
  1005. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  1006. ret);
  1007. return ret;
  1008. }
  1009. regmap_read(rt298->regmap,
  1010. RT298_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &ret);
  1011. if (ret != RT298_VENDOR_ID) {
  1012. dev_err(&i2c->dev,
  1013. "Device with ID register %#x is not rt298\n", ret);
  1014. return -ENODEV;
  1015. }
  1016. rt298->index_cache = devm_kmemdup(&i2c->dev, rt298_index_def,
  1017. sizeof(rt298_index_def), GFP_KERNEL);
  1018. if (!rt298->index_cache)
  1019. return -ENOMEM;
  1020. rt298->index_cache_size = INDEX_CACHE_SIZE;
  1021. rt298->i2c = i2c;
  1022. i2c_set_clientdata(i2c, rt298);
  1023. /* restore codec default */
  1024. for (i = 0; i < INDEX_CACHE_SIZE; i++)
  1025. regmap_write(rt298->regmap, rt298->index_cache[i].reg,
  1026. rt298->index_cache[i].def);
  1027. for (i = 0; i < ARRAY_SIZE(rt298_reg); i++)
  1028. regmap_write(rt298->regmap, rt298_reg[i].reg,
  1029. rt298_reg[i].def);
  1030. if (pdata)
  1031. rt298->pdata = *pdata;
  1032. /* enable jack combo mode on supported devices */
  1033. acpiid = acpi_match_device(dev->driver->acpi_match_table, dev);
  1034. if (acpiid && acpiid->driver_data) {
  1035. rt298->pdata = *(struct rt298_platform_data *)
  1036. acpiid->driver_data;
  1037. }
  1038. if (dmi_check_system(force_combo_jack_table)) {
  1039. rt298->pdata.cbj_en = true;
  1040. rt298->pdata.gpio2_en = false;
  1041. }
  1042. /* VREF Charging */
  1043. regmap_update_bits(rt298->regmap, 0x04, 0x80, 0x80);
  1044. regmap_update_bits(rt298->regmap, 0x1b, 0x860, 0x860);
  1045. /* Vref2 */
  1046. regmap_update_bits(rt298->regmap, 0x08, 0x20, 0x20);
  1047. regmap_write(rt298->regmap, RT298_SET_AUDIO_POWER, AC_PWRST_D3);
  1048. for (i = 0; i < RT298_POWER_REG_LEN; i++)
  1049. regmap_write(rt298->regmap,
  1050. RT298_SET_POWER(rt298_support_power_controls[i]),
  1051. AC_PWRST_D1);
  1052. if (!rt298->pdata.cbj_en) {
  1053. regmap_write(rt298->regmap, RT298_CBJ_CTRL2, 0x0000);
  1054. regmap_write(rt298->regmap, RT298_MIC1_DET_CTRL, 0x0816);
  1055. regmap_update_bits(rt298->regmap,
  1056. RT298_CBJ_CTRL1, 0xf000, 0xb000);
  1057. } else {
  1058. regmap_update_bits(rt298->regmap,
  1059. RT298_CBJ_CTRL1, 0xf000, 0x5000);
  1060. }
  1061. mdelay(10);
  1062. if (!rt298->pdata.gpio2_en)
  1063. regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0x40);
  1064. else
  1065. regmap_write(rt298->regmap, RT298_SET_DMIC2_DEFAULT, 0);
  1066. mdelay(10);
  1067. regmap_write(rt298->regmap, RT298_MISC_CTRL1, 0x0000);
  1068. regmap_update_bits(rt298->regmap,
  1069. RT298_WIND_FILTER_CTRL, 0x0082, 0x0082);
  1070. regmap_write(rt298->regmap, RT298_UNSOLICITED_INLINE_CMD, 0x81);
  1071. regmap_write(rt298->regmap, RT298_UNSOLICITED_HP_OUT, 0x82);
  1072. regmap_write(rt298->regmap, RT298_UNSOLICITED_MIC1, 0x84);
  1073. regmap_update_bits(rt298->regmap, RT298_IRQ_FLAG_CTRL, 0x2, 0x2);
  1074. rt298->is_hp_in = -1;
  1075. if (rt298->i2c->irq) {
  1076. ret = request_threaded_irq(rt298->i2c->irq, NULL, rt298_irq,
  1077. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt298", rt298);
  1078. if (ret != 0) {
  1079. dev_err(&i2c->dev,
  1080. "Failed to reguest IRQ: %d\n", ret);
  1081. return ret;
  1082. }
  1083. }
  1084. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt298,
  1085. rt298_dai, ARRAY_SIZE(rt298_dai));
  1086. return ret;
  1087. }
  1088. static int rt298_i2c_remove(struct i2c_client *i2c)
  1089. {
  1090. struct rt298_priv *rt298 = i2c_get_clientdata(i2c);
  1091. if (i2c->irq)
  1092. free_irq(i2c->irq, rt298);
  1093. snd_soc_unregister_codec(&i2c->dev);
  1094. return 0;
  1095. }
  1096. static struct i2c_driver rt298_i2c_driver = {
  1097. .driver = {
  1098. .name = "rt298",
  1099. .acpi_match_table = ACPI_PTR(rt298_acpi_match),
  1100. },
  1101. .probe = rt298_i2c_probe,
  1102. .remove = rt298_i2c_remove,
  1103. .id_table = rt298_i2c_id,
  1104. };
  1105. module_i2c_driver(rt298_i2c_driver);
  1106. MODULE_DESCRIPTION("ASoC RT298 driver");
  1107. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1108. MODULE_LICENSE("GPL");