rt286.c 31 KB

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  1. /*
  2. * rt286.c -- RT286 ALSA SoC audio codec driver
  3. *
  4. * Copyright 2013 Realtek Semiconductor Corp.
  5. * Author: Bard Liao <bardliao@realtek.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/moduleparam.h>
  13. #include <linux/init.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm.h>
  16. #include <linux/i2c.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/spi/spi.h>
  19. #include <linux/dmi.h>
  20. #include <linux/acpi.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/pcm_params.h>
  24. #include <sound/soc.h>
  25. #include <sound/soc-dapm.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/jack.h>
  29. #include <linux/workqueue.h>
  30. #include <sound/rt286.h>
  31. #include "rl6347a.h"
  32. #include "rt286.h"
  33. #define RT286_VENDOR_ID 0x10ec0286
  34. #define RT288_VENDOR_ID 0x10ec0288
  35. struct rt286_priv {
  36. struct reg_default *index_cache;
  37. int index_cache_size;
  38. struct regmap *regmap;
  39. struct snd_soc_codec *codec;
  40. struct rt286_platform_data pdata;
  41. struct i2c_client *i2c;
  42. struct snd_soc_jack *jack;
  43. struct delayed_work jack_detect_work;
  44. int sys_clk;
  45. int clk_id;
  46. };
  47. static const struct reg_default rt286_index_def[] = {
  48. { 0x01, 0xaaaa },
  49. { 0x02, 0x8aaa },
  50. { 0x03, 0x0002 },
  51. { 0x04, 0xaf01 },
  52. { 0x08, 0x000d },
  53. { 0x09, 0xd810 },
  54. { 0x0a, 0x0120 },
  55. { 0x0b, 0x0000 },
  56. { 0x0d, 0x2800 },
  57. { 0x0f, 0x0000 },
  58. { 0x19, 0x0a17 },
  59. { 0x20, 0x0020 },
  60. { 0x33, 0x0208 },
  61. { 0x49, 0x0004 },
  62. { 0x4f, 0x50e9 },
  63. { 0x50, 0x2000 },
  64. { 0x63, 0x2902 },
  65. { 0x67, 0x1111 },
  66. { 0x68, 0x1016 },
  67. { 0x69, 0x273f },
  68. };
  69. #define INDEX_CACHE_SIZE ARRAY_SIZE(rt286_index_def)
  70. static const struct reg_default rt286_reg[] = {
  71. { 0x00170500, 0x00000400 },
  72. { 0x00220000, 0x00000031 },
  73. { 0x00239000, 0x0000007f },
  74. { 0x0023a000, 0x0000007f },
  75. { 0x00270500, 0x00000400 },
  76. { 0x00370500, 0x00000400 },
  77. { 0x00870500, 0x00000400 },
  78. { 0x00920000, 0x00000031 },
  79. { 0x00935000, 0x000000c3 },
  80. { 0x00936000, 0x000000c3 },
  81. { 0x00970500, 0x00000400 },
  82. { 0x00b37000, 0x00000097 },
  83. { 0x00b37200, 0x00000097 },
  84. { 0x00b37300, 0x00000097 },
  85. { 0x00c37000, 0x00000000 },
  86. { 0x00c37100, 0x00000080 },
  87. { 0x01270500, 0x00000400 },
  88. { 0x01370500, 0x00000400 },
  89. { 0x01371f00, 0x411111f0 },
  90. { 0x01439000, 0x00000080 },
  91. { 0x0143a000, 0x00000080 },
  92. { 0x01470700, 0x00000000 },
  93. { 0x01470500, 0x00000400 },
  94. { 0x01470c00, 0x00000000 },
  95. { 0x01470100, 0x00000000 },
  96. { 0x01837000, 0x00000000 },
  97. { 0x01870500, 0x00000400 },
  98. { 0x02050000, 0x00000000 },
  99. { 0x02139000, 0x00000080 },
  100. { 0x0213a000, 0x00000080 },
  101. { 0x02170100, 0x00000000 },
  102. { 0x02170500, 0x00000400 },
  103. { 0x02170700, 0x00000000 },
  104. { 0x02270100, 0x00000000 },
  105. { 0x02370100, 0x00000000 },
  106. { 0x01870700, 0x00000020 },
  107. { 0x00830000, 0x000000c3 },
  108. { 0x00930000, 0x000000c3 },
  109. { 0x01270700, 0x00000000 },
  110. };
  111. static bool rt286_volatile_register(struct device *dev, unsigned int reg)
  112. {
  113. switch (reg) {
  114. case 0 ... 0xff:
  115. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  116. case RT286_GET_HP_SENSE:
  117. case RT286_GET_MIC1_SENSE:
  118. case RT286_PROC_COEF:
  119. return true;
  120. default:
  121. return false;
  122. }
  123. }
  124. static bool rt286_readable_register(struct device *dev, unsigned int reg)
  125. {
  126. switch (reg) {
  127. case 0 ... 0xff:
  128. case RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID):
  129. case RT286_GET_HP_SENSE:
  130. case RT286_GET_MIC1_SENSE:
  131. case RT286_SET_AUDIO_POWER:
  132. case RT286_SET_HPO_POWER:
  133. case RT286_SET_SPK_POWER:
  134. case RT286_SET_DMIC1_POWER:
  135. case RT286_SPK_MUX:
  136. case RT286_HPO_MUX:
  137. case RT286_ADC0_MUX:
  138. case RT286_ADC1_MUX:
  139. case RT286_SET_MIC1:
  140. case RT286_SET_PIN_HPO:
  141. case RT286_SET_PIN_SPK:
  142. case RT286_SET_PIN_DMIC1:
  143. case RT286_SPK_EAPD:
  144. case RT286_SET_AMP_GAIN_HPO:
  145. case RT286_SET_DMIC2_DEFAULT:
  146. case RT286_DACL_GAIN:
  147. case RT286_DACR_GAIN:
  148. case RT286_ADCL_GAIN:
  149. case RT286_ADCR_GAIN:
  150. case RT286_MIC_GAIN:
  151. case RT286_SPOL_GAIN:
  152. case RT286_SPOR_GAIN:
  153. case RT286_HPOL_GAIN:
  154. case RT286_HPOR_GAIN:
  155. case RT286_F_DAC_SWITCH:
  156. case RT286_F_RECMIX_SWITCH:
  157. case RT286_REC_MIC_SWITCH:
  158. case RT286_REC_I2S_SWITCH:
  159. case RT286_REC_LINE_SWITCH:
  160. case RT286_REC_BEEP_SWITCH:
  161. case RT286_DAC_FORMAT:
  162. case RT286_ADC_FORMAT:
  163. case RT286_COEF_INDEX:
  164. case RT286_PROC_COEF:
  165. case RT286_SET_AMP_GAIN_ADC_IN1:
  166. case RT286_SET_AMP_GAIN_ADC_IN2:
  167. case RT286_SET_POWER(RT286_DAC_OUT1):
  168. case RT286_SET_POWER(RT286_DAC_OUT2):
  169. case RT286_SET_POWER(RT286_ADC_IN1):
  170. case RT286_SET_POWER(RT286_ADC_IN2):
  171. case RT286_SET_POWER(RT286_DMIC2):
  172. case RT286_SET_POWER(RT286_MIC1):
  173. return true;
  174. default:
  175. return false;
  176. }
  177. }
  178. #ifdef CONFIG_PM
  179. static void rt286_index_sync(struct snd_soc_codec *codec)
  180. {
  181. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  182. int i;
  183. for (i = 0; i < INDEX_CACHE_SIZE; i++) {
  184. snd_soc_write(codec, rt286->index_cache[i].reg,
  185. rt286->index_cache[i].def);
  186. }
  187. }
  188. #endif
  189. static int rt286_support_power_controls[] = {
  190. RT286_DAC_OUT1,
  191. RT286_DAC_OUT2,
  192. RT286_ADC_IN1,
  193. RT286_ADC_IN2,
  194. RT286_MIC1,
  195. RT286_DMIC1,
  196. RT286_DMIC2,
  197. RT286_SPK_OUT,
  198. RT286_HP_OUT,
  199. };
  200. #define RT286_POWER_REG_LEN ARRAY_SIZE(rt286_support_power_controls)
  201. static int rt286_jack_detect(struct rt286_priv *rt286, bool *hp, bool *mic)
  202. {
  203. struct snd_soc_dapm_context *dapm;
  204. unsigned int val, buf;
  205. *hp = false;
  206. *mic = false;
  207. if (!rt286->codec)
  208. return -EINVAL;
  209. dapm = snd_soc_codec_get_dapm(rt286->codec);
  210. if (rt286->pdata.cbj_en) {
  211. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  212. *hp = buf & 0x80000000;
  213. if (*hp) {
  214. /* power on HV,VERF */
  215. regmap_update_bits(rt286->regmap,
  216. RT286_DC_GAIN, 0x200, 0x200);
  217. snd_soc_dapm_force_enable_pin(dapm, "HV");
  218. snd_soc_dapm_force_enable_pin(dapm, "VREF");
  219. /* power LDO1 */
  220. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  221. snd_soc_dapm_sync(dapm);
  222. regmap_write(rt286->regmap, RT286_SET_MIC1, 0x24);
  223. msleep(50);
  224. regmap_update_bits(rt286->regmap,
  225. RT286_CBJ_CTRL1, 0xfcc0, 0xd400);
  226. msleep(300);
  227. regmap_read(rt286->regmap, RT286_CBJ_CTRL2, &val);
  228. if (0x0070 == (val & 0x0070)) {
  229. *mic = true;
  230. } else {
  231. regmap_update_bits(rt286->regmap,
  232. RT286_CBJ_CTRL1, 0xfcc0, 0xe400);
  233. msleep(300);
  234. regmap_read(rt286->regmap,
  235. RT286_CBJ_CTRL2, &val);
  236. if (0x0070 == (val & 0x0070))
  237. *mic = true;
  238. else
  239. *mic = false;
  240. }
  241. regmap_update_bits(rt286->regmap,
  242. RT286_DC_GAIN, 0x200, 0x0);
  243. } else {
  244. *mic = false;
  245. regmap_write(rt286->regmap, RT286_SET_MIC1, 0x20);
  246. regmap_update_bits(rt286->regmap,
  247. RT286_CBJ_CTRL1, 0x0400, 0x0000);
  248. }
  249. } else {
  250. regmap_read(rt286->regmap, RT286_GET_HP_SENSE, &buf);
  251. *hp = buf & 0x80000000;
  252. regmap_read(rt286->regmap, RT286_GET_MIC1_SENSE, &buf);
  253. *mic = buf & 0x80000000;
  254. }
  255. snd_soc_dapm_disable_pin(dapm, "HV");
  256. snd_soc_dapm_disable_pin(dapm, "VREF");
  257. if (!*hp)
  258. snd_soc_dapm_disable_pin(dapm, "LDO1");
  259. snd_soc_dapm_sync(dapm);
  260. return 0;
  261. }
  262. static void rt286_jack_detect_work(struct work_struct *work)
  263. {
  264. struct rt286_priv *rt286 =
  265. container_of(work, struct rt286_priv, jack_detect_work.work);
  266. int status = 0;
  267. bool hp = false;
  268. bool mic = false;
  269. rt286_jack_detect(rt286, &hp, &mic);
  270. if (hp == true)
  271. status |= SND_JACK_HEADPHONE;
  272. if (mic == true)
  273. status |= SND_JACK_MICROPHONE;
  274. snd_soc_jack_report(rt286->jack, status,
  275. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  276. }
  277. int rt286_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
  278. {
  279. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  280. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  281. rt286->jack = jack;
  282. if (jack) {
  283. /* enable IRQ */
  284. if (rt286->jack->status & SND_JACK_HEADPHONE)
  285. snd_soc_dapm_force_enable_pin(dapm, "LDO1");
  286. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x2);
  287. /* Send an initial empty report */
  288. snd_soc_jack_report(rt286->jack, rt286->jack->status,
  289. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  290. } else {
  291. /* disable IRQ */
  292. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x2, 0x0);
  293. snd_soc_dapm_disable_pin(dapm, "LDO1");
  294. }
  295. snd_soc_dapm_sync(dapm);
  296. return 0;
  297. }
  298. EXPORT_SYMBOL_GPL(rt286_mic_detect);
  299. static int is_mclk_mode(struct snd_soc_dapm_widget *source,
  300. struct snd_soc_dapm_widget *sink)
  301. {
  302. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
  303. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  304. if (rt286->clk_id == RT286_SCLK_S_MCLK)
  305. return 1;
  306. else
  307. return 0;
  308. }
  309. static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6350, 50, 0);
  310. static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 1000, 0);
  311. static const struct snd_kcontrol_new rt286_snd_controls[] = {
  312. SOC_DOUBLE_R_TLV("DAC0 Playback Volume", RT286_DACL_GAIN,
  313. RT286_DACR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  314. SOC_DOUBLE_R("ADC0 Capture Switch", RT286_ADCL_GAIN,
  315. RT286_ADCR_GAIN, 7, 1, 1),
  316. SOC_DOUBLE_R_TLV("ADC0 Capture Volume", RT286_ADCL_GAIN,
  317. RT286_ADCR_GAIN, 0, 0x7f, 0, out_vol_tlv),
  318. SOC_SINGLE_TLV("AMIC Volume", RT286_MIC_GAIN,
  319. 0, 0x3, 0, mic_vol_tlv),
  320. SOC_DOUBLE_R("Speaker Playback Switch", RT286_SPOL_GAIN,
  321. RT286_SPOR_GAIN, RT286_MUTE_SFT, 1, 1),
  322. };
  323. /* Digital Mixer */
  324. static const struct snd_kcontrol_new rt286_front_mix[] = {
  325. SOC_DAPM_SINGLE("DAC Switch", RT286_F_DAC_SWITCH,
  326. RT286_MUTE_SFT, 1, 1),
  327. SOC_DAPM_SINGLE("RECMIX Switch", RT286_F_RECMIX_SWITCH,
  328. RT286_MUTE_SFT, 1, 1),
  329. };
  330. /* Analog Input Mixer */
  331. static const struct snd_kcontrol_new rt286_rec_mix[] = {
  332. SOC_DAPM_SINGLE("Mic1 Switch", RT286_REC_MIC_SWITCH,
  333. RT286_MUTE_SFT, 1, 1),
  334. SOC_DAPM_SINGLE("I2S Switch", RT286_REC_I2S_SWITCH,
  335. RT286_MUTE_SFT, 1, 1),
  336. SOC_DAPM_SINGLE("Line1 Switch", RT286_REC_LINE_SWITCH,
  337. RT286_MUTE_SFT, 1, 1),
  338. SOC_DAPM_SINGLE("Beep Switch", RT286_REC_BEEP_SWITCH,
  339. RT286_MUTE_SFT, 1, 1),
  340. };
  341. static const struct snd_kcontrol_new spo_enable_control =
  342. SOC_DAPM_SINGLE("Switch", RT286_SET_PIN_SPK,
  343. RT286_SET_PIN_SFT, 1, 0);
  344. static const struct snd_kcontrol_new hpol_enable_control =
  345. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOL_GAIN,
  346. RT286_MUTE_SFT, 1, 1);
  347. static const struct snd_kcontrol_new hpor_enable_control =
  348. SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT286_HPOR_GAIN,
  349. RT286_MUTE_SFT, 1, 1);
  350. /* ADC0 source */
  351. static const char * const rt286_adc_src[] = {
  352. "Mic", "RECMIX", "Dmic"
  353. };
  354. static const int rt286_adc_values[] = {
  355. 0, 4, 5,
  356. };
  357. static SOC_VALUE_ENUM_SINGLE_DECL(
  358. rt286_adc0_enum, RT286_ADC0_MUX, RT286_ADC_SEL_SFT,
  359. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  360. static const struct snd_kcontrol_new rt286_adc0_mux =
  361. SOC_DAPM_ENUM("ADC 0 source", rt286_adc0_enum);
  362. static SOC_VALUE_ENUM_SINGLE_DECL(
  363. rt286_adc1_enum, RT286_ADC1_MUX, RT286_ADC_SEL_SFT,
  364. RT286_ADC_SEL_MASK, rt286_adc_src, rt286_adc_values);
  365. static const struct snd_kcontrol_new rt286_adc1_mux =
  366. SOC_DAPM_ENUM("ADC 1 source", rt286_adc1_enum);
  367. static const char * const rt286_dac_src[] = {
  368. "Front", "Surround"
  369. };
  370. /* HP-OUT source */
  371. static SOC_ENUM_SINGLE_DECL(rt286_hpo_enum, RT286_HPO_MUX,
  372. 0, rt286_dac_src);
  373. static const struct snd_kcontrol_new rt286_hpo_mux =
  374. SOC_DAPM_ENUM("HPO source", rt286_hpo_enum);
  375. /* SPK-OUT source */
  376. static SOC_ENUM_SINGLE_DECL(rt286_spo_enum, RT286_SPK_MUX,
  377. 0, rt286_dac_src);
  378. static const struct snd_kcontrol_new rt286_spo_mux =
  379. SOC_DAPM_ENUM("SPO source", rt286_spo_enum);
  380. static int rt286_spk_event(struct snd_soc_dapm_widget *w,
  381. struct snd_kcontrol *kcontrol, int event)
  382. {
  383. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  384. switch (event) {
  385. case SND_SOC_DAPM_POST_PMU:
  386. snd_soc_write(codec,
  387. RT286_SPK_EAPD, RT286_SET_EAPD_HIGH);
  388. break;
  389. case SND_SOC_DAPM_PRE_PMD:
  390. snd_soc_write(codec,
  391. RT286_SPK_EAPD, RT286_SET_EAPD_LOW);
  392. break;
  393. default:
  394. return 0;
  395. }
  396. return 0;
  397. }
  398. static int rt286_set_dmic1_event(struct snd_soc_dapm_widget *w,
  399. struct snd_kcontrol *kcontrol, int event)
  400. {
  401. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  402. switch (event) {
  403. case SND_SOC_DAPM_POST_PMU:
  404. snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0x20);
  405. break;
  406. case SND_SOC_DAPM_PRE_PMD:
  407. snd_soc_write(codec, RT286_SET_PIN_DMIC1, 0);
  408. break;
  409. default:
  410. return 0;
  411. }
  412. return 0;
  413. }
  414. static int rt286_ldo2_event(struct snd_soc_dapm_widget *w,
  415. struct snd_kcontrol *kcontrol, int event)
  416. {
  417. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  418. switch (event) {
  419. case SND_SOC_DAPM_POST_PMU:
  420. snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x08);
  421. break;
  422. case SND_SOC_DAPM_PRE_PMD:
  423. snd_soc_update_bits(codec, RT286_POWER_CTRL2, 0x38, 0x30);
  424. break;
  425. default:
  426. return 0;
  427. }
  428. return 0;
  429. }
  430. static int rt286_mic1_event(struct snd_soc_dapm_widget *w,
  431. struct snd_kcontrol *kcontrol, int event)
  432. {
  433. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  434. switch (event) {
  435. case SND_SOC_DAPM_PRE_PMU:
  436. snd_soc_update_bits(codec,
  437. RT286_A_BIAS_CTRL3, 0xc000, 0x8000);
  438. snd_soc_update_bits(codec,
  439. RT286_A_BIAS_CTRL2, 0xc000, 0x8000);
  440. break;
  441. case SND_SOC_DAPM_POST_PMD:
  442. snd_soc_update_bits(codec,
  443. RT286_A_BIAS_CTRL3, 0xc000, 0x0000);
  444. snd_soc_update_bits(codec,
  445. RT286_A_BIAS_CTRL2, 0xc000, 0x0000);
  446. break;
  447. default:
  448. return 0;
  449. }
  450. return 0;
  451. }
  452. static const struct snd_soc_dapm_widget rt286_dapm_widgets[] = {
  453. SND_SOC_DAPM_SUPPLY_S("HV", 1, RT286_POWER_CTRL1,
  454. 12, 1, NULL, 0),
  455. SND_SOC_DAPM_SUPPLY("VREF", RT286_POWER_CTRL1,
  456. 0, 1, NULL, 0),
  457. SND_SOC_DAPM_SUPPLY_S("LDO1", 1, RT286_POWER_CTRL2,
  458. 2, 0, NULL, 0),
  459. SND_SOC_DAPM_SUPPLY_S("LDO2", 2, RT286_POWER_CTRL1,
  460. 13, 1, rt286_ldo2_event, SND_SOC_DAPM_PRE_PMD |
  461. SND_SOC_DAPM_POST_PMU),
  462. SND_SOC_DAPM_SUPPLY("MCLK MODE", RT286_PLL_CTRL1,
  463. 5, 0, NULL, 0),
  464. SND_SOC_DAPM_SUPPLY("MIC1 Input Buffer", SND_SOC_NOPM,
  465. 0, 0, rt286_mic1_event, SND_SOC_DAPM_PRE_PMU |
  466. SND_SOC_DAPM_POST_PMD),
  467. /* Input Lines */
  468. SND_SOC_DAPM_INPUT("DMIC1 Pin"),
  469. SND_SOC_DAPM_INPUT("DMIC2 Pin"),
  470. SND_SOC_DAPM_INPUT("MIC1"),
  471. SND_SOC_DAPM_INPUT("LINE1"),
  472. SND_SOC_DAPM_INPUT("Beep"),
  473. /* DMIC */
  474. SND_SOC_DAPM_PGA_E("DMIC1", RT286_SET_POWER(RT286_DMIC1), 0, 1,
  475. NULL, 0, rt286_set_dmic1_event,
  476. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  477. SND_SOC_DAPM_PGA("DMIC2", RT286_SET_POWER(RT286_DMIC2), 0, 1,
  478. NULL, 0),
  479. SND_SOC_DAPM_SUPPLY("DMIC Receiver", SND_SOC_NOPM,
  480. 0, 0, NULL, 0),
  481. /* REC Mixer */
  482. SND_SOC_DAPM_MIXER("RECMIX", SND_SOC_NOPM, 0, 0,
  483. rt286_rec_mix, ARRAY_SIZE(rt286_rec_mix)),
  484. /* ADCs */
  485. SND_SOC_DAPM_ADC("ADC 0", NULL, SND_SOC_NOPM, 0, 0),
  486. SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM, 0, 0),
  487. /* ADC Mux */
  488. SND_SOC_DAPM_MUX("ADC 0 Mux", RT286_SET_POWER(RT286_ADC_IN1), 0, 1,
  489. &rt286_adc0_mux),
  490. SND_SOC_DAPM_MUX("ADC 1 Mux", RT286_SET_POWER(RT286_ADC_IN2), 0, 1,
  491. &rt286_adc1_mux),
  492. /* Audio Interface */
  493. SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
  494. SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
  495. SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
  496. SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
  497. /* Output Side */
  498. /* DACs */
  499. SND_SOC_DAPM_DAC("DAC 0", NULL, SND_SOC_NOPM, 0, 0),
  500. SND_SOC_DAPM_DAC("DAC 1", NULL, SND_SOC_NOPM, 0, 0),
  501. /* Output Mux */
  502. SND_SOC_DAPM_MUX("SPK Mux", SND_SOC_NOPM, 0, 0, &rt286_spo_mux),
  503. SND_SOC_DAPM_MUX("HPO Mux", SND_SOC_NOPM, 0, 0, &rt286_hpo_mux),
  504. SND_SOC_DAPM_SUPPLY("HP Power", RT286_SET_PIN_HPO,
  505. RT286_SET_PIN_SFT, 0, NULL, 0),
  506. /* Output Mixer */
  507. SND_SOC_DAPM_MIXER("Front", RT286_SET_POWER(RT286_DAC_OUT1), 0, 1,
  508. rt286_front_mix, ARRAY_SIZE(rt286_front_mix)),
  509. SND_SOC_DAPM_PGA("Surround", RT286_SET_POWER(RT286_DAC_OUT2), 0, 1,
  510. NULL, 0),
  511. /* Output Pga */
  512. SND_SOC_DAPM_SWITCH_E("SPO", SND_SOC_NOPM, 0, 0,
  513. &spo_enable_control, rt286_spk_event,
  514. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
  515. SND_SOC_DAPM_SWITCH("HPO L", SND_SOC_NOPM, 0, 0,
  516. &hpol_enable_control),
  517. SND_SOC_DAPM_SWITCH("HPO R", SND_SOC_NOPM, 0, 0,
  518. &hpor_enable_control),
  519. /* Output Lines */
  520. SND_SOC_DAPM_OUTPUT("SPOL"),
  521. SND_SOC_DAPM_OUTPUT("SPOR"),
  522. SND_SOC_DAPM_OUTPUT("HPO Pin"),
  523. SND_SOC_DAPM_OUTPUT("SPDIF"),
  524. };
  525. static const struct snd_soc_dapm_route rt286_dapm_routes[] = {
  526. {"ADC 0", NULL, "MCLK MODE", is_mclk_mode},
  527. {"ADC 1", NULL, "MCLK MODE", is_mclk_mode},
  528. {"Front", NULL, "MCLK MODE", is_mclk_mode},
  529. {"Surround", NULL, "MCLK MODE", is_mclk_mode},
  530. {"HP Power", NULL, "LDO1"},
  531. {"HP Power", NULL, "LDO2"},
  532. {"MIC1", NULL, "LDO1"},
  533. {"MIC1", NULL, "LDO2"},
  534. {"MIC1", NULL, "HV"},
  535. {"MIC1", NULL, "VREF"},
  536. {"MIC1", NULL, "MIC1 Input Buffer"},
  537. {"SPO", NULL, "LDO1"},
  538. {"SPO", NULL, "LDO2"},
  539. {"SPO", NULL, "HV"},
  540. {"SPO", NULL, "VREF"},
  541. {"DMIC1", NULL, "DMIC1 Pin"},
  542. {"DMIC2", NULL, "DMIC2 Pin"},
  543. {"DMIC1", NULL, "DMIC Receiver"},
  544. {"DMIC2", NULL, "DMIC Receiver"},
  545. {"RECMIX", "Beep Switch", "Beep"},
  546. {"RECMIX", "Line1 Switch", "LINE1"},
  547. {"RECMIX", "Mic1 Switch", "MIC1"},
  548. {"ADC 0 Mux", "Dmic", "DMIC1"},
  549. {"ADC 0 Mux", "RECMIX", "RECMIX"},
  550. {"ADC 0 Mux", "Mic", "MIC1"},
  551. {"ADC 1 Mux", "Dmic", "DMIC2"},
  552. {"ADC 1 Mux", "RECMIX", "RECMIX"},
  553. {"ADC 1 Mux", "Mic", "MIC1"},
  554. {"ADC 0", NULL, "ADC 0 Mux"},
  555. {"ADC 1", NULL, "ADC 1 Mux"},
  556. {"AIF1TX", NULL, "ADC 0"},
  557. {"AIF2TX", NULL, "ADC 1"},
  558. {"DAC 0", NULL, "AIF1RX"},
  559. {"DAC 1", NULL, "AIF2RX"},
  560. {"Front", "DAC Switch", "DAC 0"},
  561. {"Front", "RECMIX Switch", "RECMIX"},
  562. {"Surround", NULL, "DAC 1"},
  563. {"SPK Mux", "Front", "Front"},
  564. {"SPK Mux", "Surround", "Surround"},
  565. {"HPO Mux", "Front", "Front"},
  566. {"HPO Mux", "Surround", "Surround"},
  567. {"SPO", "Switch", "SPK Mux"},
  568. {"HPO L", "Switch", "HPO Mux"},
  569. {"HPO R", "Switch", "HPO Mux"},
  570. {"HPO L", NULL, "HP Power"},
  571. {"HPO R", NULL, "HP Power"},
  572. {"SPOL", NULL, "SPO"},
  573. {"SPOR", NULL, "SPO"},
  574. {"HPO Pin", NULL, "HPO L"},
  575. {"HPO Pin", NULL, "HPO R"},
  576. };
  577. static int rt286_hw_params(struct snd_pcm_substream *substream,
  578. struct snd_pcm_hw_params *params,
  579. struct snd_soc_dai *dai)
  580. {
  581. struct snd_soc_codec *codec = dai->codec;
  582. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  583. unsigned int val = 0;
  584. int d_len_code;
  585. switch (params_rate(params)) {
  586. /* bit 14 0:48K 1:44.1K */
  587. case 44100:
  588. val |= 0x4000;
  589. break;
  590. case 48000:
  591. break;
  592. default:
  593. dev_err(codec->dev, "Unsupported sample rate %d\n",
  594. params_rate(params));
  595. return -EINVAL;
  596. }
  597. switch (rt286->sys_clk) {
  598. case 12288000:
  599. case 24576000:
  600. if (params_rate(params) != 48000) {
  601. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  602. params_rate(params), rt286->sys_clk);
  603. return -EINVAL;
  604. }
  605. break;
  606. case 11289600:
  607. case 22579200:
  608. if (params_rate(params) != 44100) {
  609. dev_err(codec->dev, "Sys_clk is not matched (%d %d)\n",
  610. params_rate(params), rt286->sys_clk);
  611. return -EINVAL;
  612. }
  613. break;
  614. }
  615. if (params_channels(params) <= 16) {
  616. /* bit 3:0 Number of Channel */
  617. val |= (params_channels(params) - 1);
  618. } else {
  619. dev_err(codec->dev, "Unsupported channels %d\n",
  620. params_channels(params));
  621. return -EINVAL;
  622. }
  623. d_len_code = 0;
  624. switch (params_width(params)) {
  625. /* bit 6:4 Bits per Sample */
  626. case 16:
  627. d_len_code = 0;
  628. val |= (0x1 << 4);
  629. break;
  630. case 32:
  631. d_len_code = 2;
  632. val |= (0x4 << 4);
  633. break;
  634. case 20:
  635. d_len_code = 1;
  636. val |= (0x2 << 4);
  637. break;
  638. case 24:
  639. d_len_code = 2;
  640. val |= (0x3 << 4);
  641. break;
  642. case 8:
  643. d_len_code = 3;
  644. break;
  645. default:
  646. return -EINVAL;
  647. }
  648. snd_soc_update_bits(codec,
  649. RT286_I2S_CTRL1, 0x0018, d_len_code << 3);
  650. dev_dbg(codec->dev, "format val = 0x%x\n", val);
  651. snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x407f, val);
  652. snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x407f, val);
  653. return 0;
  654. }
  655. static int rt286_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  656. {
  657. struct snd_soc_codec *codec = dai->codec;
  658. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  659. case SND_SOC_DAIFMT_CBM_CFM:
  660. snd_soc_update_bits(codec,
  661. RT286_I2S_CTRL1, 0x800, 0x800);
  662. break;
  663. case SND_SOC_DAIFMT_CBS_CFS:
  664. snd_soc_update_bits(codec,
  665. RT286_I2S_CTRL1, 0x800, 0x0);
  666. break;
  667. default:
  668. return -EINVAL;
  669. }
  670. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  671. case SND_SOC_DAIFMT_I2S:
  672. snd_soc_update_bits(codec,
  673. RT286_I2S_CTRL1, 0x300, 0x0);
  674. break;
  675. case SND_SOC_DAIFMT_LEFT_J:
  676. snd_soc_update_bits(codec,
  677. RT286_I2S_CTRL1, 0x300, 0x1 << 8);
  678. break;
  679. case SND_SOC_DAIFMT_DSP_A:
  680. snd_soc_update_bits(codec,
  681. RT286_I2S_CTRL1, 0x300, 0x2 << 8);
  682. break;
  683. case SND_SOC_DAIFMT_DSP_B:
  684. snd_soc_update_bits(codec,
  685. RT286_I2S_CTRL1, 0x300, 0x3 << 8);
  686. break;
  687. default:
  688. return -EINVAL;
  689. }
  690. /* bit 15 Stream Type 0:PCM 1:Non-PCM */
  691. snd_soc_update_bits(codec, RT286_DAC_FORMAT, 0x8000, 0);
  692. snd_soc_update_bits(codec, RT286_ADC_FORMAT, 0x8000, 0);
  693. return 0;
  694. }
  695. static int rt286_set_dai_sysclk(struct snd_soc_dai *dai,
  696. int clk_id, unsigned int freq, int dir)
  697. {
  698. struct snd_soc_codec *codec = dai->codec;
  699. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  700. dev_dbg(codec->dev, "%s freq=%d\n", __func__, freq);
  701. if (RT286_SCLK_S_MCLK == clk_id) {
  702. snd_soc_update_bits(codec,
  703. RT286_I2S_CTRL2, 0x0100, 0x0);
  704. snd_soc_update_bits(codec,
  705. RT286_PLL_CTRL1, 0x20, 0x20);
  706. } else {
  707. snd_soc_update_bits(codec,
  708. RT286_I2S_CTRL2, 0x0100, 0x0100);
  709. snd_soc_update_bits(codec,
  710. RT286_PLL_CTRL, 0x4, 0x4);
  711. snd_soc_update_bits(codec,
  712. RT286_PLL_CTRL1, 0x20, 0x0);
  713. }
  714. switch (freq) {
  715. case 19200000:
  716. if (RT286_SCLK_S_MCLK == clk_id) {
  717. dev_err(codec->dev, "Should not use MCLK\n");
  718. return -EINVAL;
  719. }
  720. snd_soc_update_bits(codec,
  721. RT286_I2S_CTRL2, 0x40, 0x40);
  722. break;
  723. case 24000000:
  724. if (RT286_SCLK_S_MCLK == clk_id) {
  725. dev_err(codec->dev, "Should not use MCLK\n");
  726. return -EINVAL;
  727. }
  728. snd_soc_update_bits(codec,
  729. RT286_I2S_CTRL2, 0x40, 0x0);
  730. break;
  731. case 12288000:
  732. case 11289600:
  733. snd_soc_update_bits(codec,
  734. RT286_I2S_CTRL2, 0x8, 0x0);
  735. snd_soc_update_bits(codec,
  736. RT286_CLK_DIV, 0xfc1e, 0x0004);
  737. break;
  738. case 24576000:
  739. case 22579200:
  740. snd_soc_update_bits(codec,
  741. RT286_I2S_CTRL2, 0x8, 0x8);
  742. snd_soc_update_bits(codec,
  743. RT286_CLK_DIV, 0xfc1e, 0x5406);
  744. break;
  745. default:
  746. dev_err(codec->dev, "Unsupported system clock\n");
  747. return -EINVAL;
  748. }
  749. rt286->sys_clk = freq;
  750. rt286->clk_id = clk_id;
  751. return 0;
  752. }
  753. static int rt286_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
  754. {
  755. struct snd_soc_codec *codec = dai->codec;
  756. dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
  757. if (50 == ratio)
  758. snd_soc_update_bits(codec,
  759. RT286_I2S_CTRL1, 0x1000, 0x1000);
  760. else
  761. snd_soc_update_bits(codec,
  762. RT286_I2S_CTRL1, 0x1000, 0x0);
  763. return 0;
  764. }
  765. static int rt286_set_bias_level(struct snd_soc_codec *codec,
  766. enum snd_soc_bias_level level)
  767. {
  768. switch (level) {
  769. case SND_SOC_BIAS_PREPARE:
  770. if (SND_SOC_BIAS_STANDBY == snd_soc_codec_get_bias_level(codec)) {
  771. snd_soc_write(codec,
  772. RT286_SET_AUDIO_POWER, AC_PWRST_D0);
  773. snd_soc_update_bits(codec,
  774. RT286_DC_GAIN, 0x200, 0x200);
  775. }
  776. break;
  777. case SND_SOC_BIAS_ON:
  778. mdelay(10);
  779. snd_soc_update_bits(codec,
  780. RT286_DC_GAIN, 0x200, 0x0);
  781. break;
  782. case SND_SOC_BIAS_STANDBY:
  783. snd_soc_write(codec,
  784. RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  785. break;
  786. default:
  787. break;
  788. }
  789. return 0;
  790. }
  791. static irqreturn_t rt286_irq(int irq, void *data)
  792. {
  793. struct rt286_priv *rt286 = data;
  794. bool hp = false;
  795. bool mic = false;
  796. int status = 0;
  797. rt286_jack_detect(rt286, &hp, &mic);
  798. /* Clear IRQ */
  799. regmap_update_bits(rt286->regmap, RT286_IRQ_CTRL, 0x1, 0x1);
  800. if (hp == true)
  801. status |= SND_JACK_HEADPHONE;
  802. if (mic == true)
  803. status |= SND_JACK_MICROPHONE;
  804. snd_soc_jack_report(rt286->jack, status,
  805. SND_JACK_MICROPHONE | SND_JACK_HEADPHONE);
  806. pm_wakeup_event(&rt286->i2c->dev, 300);
  807. return IRQ_HANDLED;
  808. }
  809. static int rt286_probe(struct snd_soc_codec *codec)
  810. {
  811. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  812. rt286->codec = codec;
  813. if (rt286->i2c->irq) {
  814. regmap_update_bits(rt286->regmap,
  815. RT286_IRQ_CTRL, 0x2, 0x2);
  816. INIT_DELAYED_WORK(&rt286->jack_detect_work,
  817. rt286_jack_detect_work);
  818. schedule_delayed_work(&rt286->jack_detect_work,
  819. msecs_to_jiffies(1250));
  820. }
  821. return 0;
  822. }
  823. static int rt286_remove(struct snd_soc_codec *codec)
  824. {
  825. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  826. cancel_delayed_work_sync(&rt286->jack_detect_work);
  827. return 0;
  828. }
  829. #ifdef CONFIG_PM
  830. static int rt286_suspend(struct snd_soc_codec *codec)
  831. {
  832. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  833. regcache_cache_only(rt286->regmap, true);
  834. regcache_mark_dirty(rt286->regmap);
  835. return 0;
  836. }
  837. static int rt286_resume(struct snd_soc_codec *codec)
  838. {
  839. struct rt286_priv *rt286 = snd_soc_codec_get_drvdata(codec);
  840. regcache_cache_only(rt286->regmap, false);
  841. rt286_index_sync(codec);
  842. regcache_sync(rt286->regmap);
  843. return 0;
  844. }
  845. #else
  846. #define rt286_suspend NULL
  847. #define rt286_resume NULL
  848. #endif
  849. #define RT286_STEREO_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  850. #define RT286_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  851. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
  852. static const struct snd_soc_dai_ops rt286_aif_dai_ops = {
  853. .hw_params = rt286_hw_params,
  854. .set_fmt = rt286_set_dai_fmt,
  855. .set_sysclk = rt286_set_dai_sysclk,
  856. .set_bclk_ratio = rt286_set_bclk_ratio,
  857. };
  858. static struct snd_soc_dai_driver rt286_dai[] = {
  859. {
  860. .name = "rt286-aif1",
  861. .id = RT286_AIF1,
  862. .playback = {
  863. .stream_name = "AIF1 Playback",
  864. .channels_min = 1,
  865. .channels_max = 2,
  866. .rates = RT286_STEREO_RATES,
  867. .formats = RT286_FORMATS,
  868. },
  869. .capture = {
  870. .stream_name = "AIF1 Capture",
  871. .channels_min = 1,
  872. .channels_max = 2,
  873. .rates = RT286_STEREO_RATES,
  874. .formats = RT286_FORMATS,
  875. },
  876. .ops = &rt286_aif_dai_ops,
  877. .symmetric_rates = 1,
  878. },
  879. {
  880. .name = "rt286-aif2",
  881. .id = RT286_AIF2,
  882. .playback = {
  883. .stream_name = "AIF2 Playback",
  884. .channels_min = 1,
  885. .channels_max = 2,
  886. .rates = RT286_STEREO_RATES,
  887. .formats = RT286_FORMATS,
  888. },
  889. .capture = {
  890. .stream_name = "AIF2 Capture",
  891. .channels_min = 1,
  892. .channels_max = 2,
  893. .rates = RT286_STEREO_RATES,
  894. .formats = RT286_FORMATS,
  895. },
  896. .ops = &rt286_aif_dai_ops,
  897. .symmetric_rates = 1,
  898. },
  899. };
  900. static struct snd_soc_codec_driver soc_codec_dev_rt286 = {
  901. .probe = rt286_probe,
  902. .remove = rt286_remove,
  903. .suspend = rt286_suspend,
  904. .resume = rt286_resume,
  905. .set_bias_level = rt286_set_bias_level,
  906. .idle_bias_off = true,
  907. .component_driver = {
  908. .controls = rt286_snd_controls,
  909. .num_controls = ARRAY_SIZE(rt286_snd_controls),
  910. .dapm_widgets = rt286_dapm_widgets,
  911. .num_dapm_widgets = ARRAY_SIZE(rt286_dapm_widgets),
  912. .dapm_routes = rt286_dapm_routes,
  913. .num_dapm_routes = ARRAY_SIZE(rt286_dapm_routes),
  914. },
  915. };
  916. static const struct regmap_config rt286_regmap = {
  917. .reg_bits = 32,
  918. .val_bits = 32,
  919. .max_register = 0x02370100,
  920. .volatile_reg = rt286_volatile_register,
  921. .readable_reg = rt286_readable_register,
  922. .reg_write = rl6347a_hw_write,
  923. .reg_read = rl6347a_hw_read,
  924. .cache_type = REGCACHE_RBTREE,
  925. .reg_defaults = rt286_reg,
  926. .num_reg_defaults = ARRAY_SIZE(rt286_reg),
  927. };
  928. static const struct i2c_device_id rt286_i2c_id[] = {
  929. {"rt286", 0},
  930. {"rt288", 0},
  931. {}
  932. };
  933. MODULE_DEVICE_TABLE(i2c, rt286_i2c_id);
  934. static const struct acpi_device_id rt286_acpi_match[] = {
  935. { "INT343A", 0 },
  936. {},
  937. };
  938. MODULE_DEVICE_TABLE(acpi, rt286_acpi_match);
  939. static const struct dmi_system_id force_combo_jack_table[] = {
  940. {
  941. .ident = "Intel Wilson Beach",
  942. .matches = {
  943. DMI_MATCH(DMI_BOARD_NAME, "Wilson Beach SDS")
  944. }
  945. },
  946. {
  947. .ident = "Intel Skylake RVP",
  948. .matches = {
  949. DMI_MATCH(DMI_PRODUCT_NAME, "Skylake Client platform")
  950. }
  951. },
  952. {
  953. .ident = "Intel Kabylake RVP",
  954. .matches = {
  955. DMI_MATCH(DMI_PRODUCT_NAME, "Kabylake Client platform")
  956. }
  957. },
  958. {
  959. .ident = "Thinkpad Helix 2nd",
  960. .matches = {
  961. DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
  962. DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad Helix 2nd")
  963. }
  964. },
  965. { }
  966. };
  967. static const struct dmi_system_id dmi_dell_dino[] = {
  968. {
  969. .ident = "Dell Dino",
  970. .matches = {
  971. DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
  972. DMI_MATCH(DMI_PRODUCT_NAME, "XPS 13 9343")
  973. }
  974. },
  975. { }
  976. };
  977. static int rt286_i2c_probe(struct i2c_client *i2c,
  978. const struct i2c_device_id *id)
  979. {
  980. struct rt286_platform_data *pdata = dev_get_platdata(&i2c->dev);
  981. struct rt286_priv *rt286;
  982. int i, ret, val;
  983. rt286 = devm_kzalloc(&i2c->dev, sizeof(*rt286),
  984. GFP_KERNEL);
  985. if (NULL == rt286)
  986. return -ENOMEM;
  987. rt286->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt286_regmap);
  988. if (IS_ERR(rt286->regmap)) {
  989. ret = PTR_ERR(rt286->regmap);
  990. dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
  991. ret);
  992. return ret;
  993. }
  994. ret = regmap_read(rt286->regmap,
  995. RT286_GET_PARAM(AC_NODE_ROOT, AC_PAR_VENDOR_ID), &val);
  996. if (ret != 0) {
  997. dev_err(&i2c->dev, "I2C error %d\n", ret);
  998. return ret;
  999. }
  1000. if (val != RT286_VENDOR_ID && val != RT288_VENDOR_ID) {
  1001. dev_err(&i2c->dev,
  1002. "Device with ID register %#x is not rt286\n", val);
  1003. return -ENODEV;
  1004. }
  1005. rt286->index_cache = devm_kmemdup(&i2c->dev, rt286_index_def,
  1006. sizeof(rt286_index_def), GFP_KERNEL);
  1007. if (!rt286->index_cache)
  1008. return -ENOMEM;
  1009. rt286->index_cache_size = INDEX_CACHE_SIZE;
  1010. rt286->i2c = i2c;
  1011. i2c_set_clientdata(i2c, rt286);
  1012. /* restore codec default */
  1013. for (i = 0; i < INDEX_CACHE_SIZE; i++)
  1014. regmap_write(rt286->regmap, rt286->index_cache[i].reg,
  1015. rt286->index_cache[i].def);
  1016. for (i = 0; i < ARRAY_SIZE(rt286_reg); i++)
  1017. regmap_write(rt286->regmap, rt286_reg[i].reg,
  1018. rt286_reg[i].def);
  1019. if (pdata)
  1020. rt286->pdata = *pdata;
  1021. if (dmi_check_system(force_combo_jack_table) ||
  1022. dmi_check_system(dmi_dell_dino))
  1023. rt286->pdata.cbj_en = true;
  1024. regmap_write(rt286->regmap, RT286_SET_AUDIO_POWER, AC_PWRST_D3);
  1025. for (i = 0; i < RT286_POWER_REG_LEN; i++)
  1026. regmap_write(rt286->regmap,
  1027. RT286_SET_POWER(rt286_support_power_controls[i]),
  1028. AC_PWRST_D1);
  1029. if (!rt286->pdata.cbj_en) {
  1030. regmap_write(rt286->regmap, RT286_CBJ_CTRL2, 0x0000);
  1031. regmap_write(rt286->regmap, RT286_MIC1_DET_CTRL, 0x0816);
  1032. regmap_update_bits(rt286->regmap,
  1033. RT286_CBJ_CTRL1, 0xf000, 0xb000);
  1034. } else {
  1035. regmap_update_bits(rt286->regmap,
  1036. RT286_CBJ_CTRL1, 0xf000, 0x5000);
  1037. }
  1038. mdelay(10);
  1039. if (!rt286->pdata.gpio2_en)
  1040. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0x4000);
  1041. else
  1042. regmap_write(rt286->regmap, RT286_SET_DMIC2_DEFAULT, 0);
  1043. mdelay(10);
  1044. regmap_write(rt286->regmap, RT286_MISC_CTRL1, 0x0000);
  1045. /* Power down LDO, VREF */
  1046. regmap_update_bits(rt286->regmap, RT286_POWER_CTRL2, 0xc, 0x0);
  1047. regmap_update_bits(rt286->regmap, RT286_POWER_CTRL1, 0x1001, 0x1001);
  1048. /* Set depop parameter */
  1049. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL2, 0x403a, 0x401a);
  1050. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL3, 0xf777, 0x4737);
  1051. regmap_update_bits(rt286->regmap, RT286_DEPOP_CTRL4, 0x00ff, 0x003f);
  1052. if (dmi_check_system(dmi_dell_dino)) {
  1053. regmap_update_bits(rt286->regmap,
  1054. RT286_SET_GPIO_MASK, 0x40, 0x40);
  1055. regmap_update_bits(rt286->regmap,
  1056. RT286_SET_GPIO_DIRECTION, 0x40, 0x40);
  1057. regmap_update_bits(rt286->regmap,
  1058. RT286_SET_GPIO_DATA, 0x40, 0x40);
  1059. regmap_update_bits(rt286->regmap,
  1060. RT286_GPIO_CTRL, 0xc, 0x8);
  1061. }
  1062. if (rt286->i2c->irq) {
  1063. ret = request_threaded_irq(rt286->i2c->irq, NULL, rt286_irq,
  1064. IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "rt286", rt286);
  1065. if (ret != 0) {
  1066. dev_err(&i2c->dev,
  1067. "Failed to reguest IRQ: %d\n", ret);
  1068. return ret;
  1069. }
  1070. }
  1071. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt286,
  1072. rt286_dai, ARRAY_SIZE(rt286_dai));
  1073. return ret;
  1074. }
  1075. static int rt286_i2c_remove(struct i2c_client *i2c)
  1076. {
  1077. struct rt286_priv *rt286 = i2c_get_clientdata(i2c);
  1078. if (i2c->irq)
  1079. free_irq(i2c->irq, rt286);
  1080. snd_soc_unregister_codec(&i2c->dev);
  1081. return 0;
  1082. }
  1083. static struct i2c_driver rt286_i2c_driver = {
  1084. .driver = {
  1085. .name = "rt286",
  1086. .acpi_match_table = ACPI_PTR(rt286_acpi_match),
  1087. },
  1088. .probe = rt286_i2c_probe,
  1089. .remove = rt286_i2c_remove,
  1090. .id_table = rt286_i2c_id,
  1091. };
  1092. module_i2c_driver(rt286_i2c_driver);
  1093. MODULE_DESCRIPTION("ASoC RT286 driver");
  1094. MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
  1095. MODULE_LICENSE("GPL");