max98925.c 18 KB

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  1. /*
  2. * max98925.c -- ALSA SoC Stereo MAX98925 driver
  3. * Copyright 2013-15 Maxim Integrated Products
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/delay.h>
  9. #include <linux/i2c.h>
  10. #include <linux/module.h>
  11. #include <linux/regmap.h>
  12. #include <linux/slab.h>
  13. #include <linux/cdev.h>
  14. #include <sound/pcm.h>
  15. #include <sound/pcm_params.h>
  16. #include <sound/soc.h>
  17. #include <sound/tlv.h>
  18. #include "max98925.h"
  19. static const char *const dai_text[] = {
  20. "Left", "Right", "LeftRight", "LeftRightDiv2",
  21. };
  22. static const char * const max98925_boost_voltage_text[] = {
  23. "8.5V", "8.25V", "8.0V", "7.75V", "7.5V", "7.25V", "7.0V", "6.75V",
  24. "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V", "6.5V"
  25. };
  26. static SOC_ENUM_SINGLE_DECL(max98925_boost_voltage,
  27. MAX98925_CONFIGURATION, M98925_BST_VOUT_SHIFT,
  28. max98925_boost_voltage_text);
  29. static const char *const hpf_text[] = {
  30. "Disable", "DC Block", "100Hz", "200Hz", "400Hz", "800Hz",
  31. };
  32. static const struct reg_default max98925_reg[] = {
  33. { 0x0B, 0x00 }, /* IRQ Enable0 */
  34. { 0x0C, 0x00 }, /* IRQ Enable1 */
  35. { 0x0D, 0x00 }, /* IRQ Enable2 */
  36. { 0x0E, 0x00 }, /* IRQ Clear0 */
  37. { 0x0F, 0x00 }, /* IRQ Clear1 */
  38. { 0x10, 0x00 }, /* IRQ Clear2 */
  39. { 0x11, 0xC0 }, /* Map0 */
  40. { 0x12, 0x00 }, /* Map1 */
  41. { 0x13, 0x00 }, /* Map2 */
  42. { 0x14, 0xF0 }, /* Map3 */
  43. { 0x15, 0x00 }, /* Map4 */
  44. { 0x16, 0xAB }, /* Map5 */
  45. { 0x17, 0x89 }, /* Map6 */
  46. { 0x18, 0x00 }, /* Map7 */
  47. { 0x19, 0x00 }, /* Map8 */
  48. { 0x1A, 0x06 }, /* DAI Clock Mode 1 */
  49. { 0x1B, 0xC0 }, /* DAI Clock Mode 2 */
  50. { 0x1C, 0x00 }, /* DAI Clock Divider Denominator MSBs */
  51. { 0x1D, 0x00 }, /* DAI Clock Divider Denominator LSBs */
  52. { 0x1E, 0xF0 }, /* DAI Clock Divider Numerator MSBs */
  53. { 0x1F, 0x00 }, /* DAI Clock Divider Numerator LSBs */
  54. { 0x20, 0x50 }, /* Format */
  55. { 0x21, 0x00 }, /* TDM Slot Select */
  56. { 0x22, 0x00 }, /* DOUT Configuration VMON */
  57. { 0x23, 0x00 }, /* DOUT Configuration IMON */
  58. { 0x24, 0x00 }, /* DOUT Configuration VBAT */
  59. { 0x25, 0x00 }, /* DOUT Configuration VBST */
  60. { 0x26, 0x00 }, /* DOUT Configuration FLAG */
  61. { 0x27, 0xFF }, /* DOUT HiZ Configuration 1 */
  62. { 0x28, 0xFF }, /* DOUT HiZ Configuration 2 */
  63. { 0x29, 0xFF }, /* DOUT HiZ Configuration 3 */
  64. { 0x2A, 0xFF }, /* DOUT HiZ Configuration 4 */
  65. { 0x2B, 0x02 }, /* DOUT Drive Strength */
  66. { 0x2C, 0x90 }, /* Filters */
  67. { 0x2D, 0x00 }, /* Gain */
  68. { 0x2E, 0x02 }, /* Gain Ramping */
  69. { 0x2F, 0x00 }, /* Speaker Amplifier */
  70. { 0x30, 0x0A }, /* Threshold */
  71. { 0x31, 0x00 }, /* ALC Attack */
  72. { 0x32, 0x80 }, /* ALC Atten and Release */
  73. { 0x33, 0x00 }, /* ALC Infinite Hold Release */
  74. { 0x34, 0x92 }, /* ALC Configuration */
  75. { 0x35, 0x01 }, /* Boost Converter */
  76. { 0x36, 0x00 }, /* Block Enable */
  77. { 0x37, 0x00 }, /* Configuration */
  78. { 0x38, 0x00 }, /* Global Enable */
  79. { 0x3A, 0x00 }, /* Boost Limiter */
  80. };
  81. static const struct soc_enum max98925_dai_enum =
  82. SOC_ENUM_SINGLE(MAX98925_GAIN, 5, ARRAY_SIZE(dai_text), dai_text);
  83. static const struct soc_enum max98925_hpf_enum =
  84. SOC_ENUM_SINGLE(MAX98925_FILTERS, 0, ARRAY_SIZE(hpf_text), hpf_text);
  85. static const struct snd_kcontrol_new max98925_hpf_sel_mux =
  86. SOC_DAPM_ENUM("Rc Filter MUX Mux", max98925_hpf_enum);
  87. static const struct snd_kcontrol_new max98925_dai_sel_mux =
  88. SOC_DAPM_ENUM("DAI IN MUX Mux", max98925_dai_enum);
  89. static int max98925_dac_event(struct snd_soc_dapm_widget *w,
  90. struct snd_kcontrol *kcontrol, int event)
  91. {
  92. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  93. struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
  94. switch (event) {
  95. case SND_SOC_DAPM_PRE_PMU:
  96. regmap_update_bits(max98925->regmap,
  97. MAX98925_BLOCK_ENABLE,
  98. M98925_BST_EN_MASK |
  99. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK,
  100. M98925_BST_EN_MASK |
  101. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK);
  102. break;
  103. case SND_SOC_DAPM_POST_PMD:
  104. regmap_update_bits(max98925->regmap,
  105. MAX98925_BLOCK_ENABLE, M98925_BST_EN_MASK |
  106. M98925_ADC_IMON_EN_MASK | M98925_ADC_VMON_EN_MASK, 0);
  107. break;
  108. default:
  109. return 0;
  110. }
  111. return 0;
  112. }
  113. static const struct snd_soc_dapm_widget max98925_dapm_widgets[] = {
  114. SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
  115. SND_SOC_DAPM_MUX("DAI IN MUX", SND_SOC_NOPM, 0, 0,
  116. &max98925_dai_sel_mux),
  117. SND_SOC_DAPM_MUX("Rc Filter MUX", SND_SOC_NOPM, 0, 0,
  118. &max98925_hpf_sel_mux),
  119. SND_SOC_DAPM_DAC_E("Amp Enable", NULL, MAX98925_BLOCK_ENABLE,
  120. M98925_SPK_EN_SHIFT, 0, max98925_dac_event,
  121. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
  122. SND_SOC_DAPM_SUPPLY("Global Enable", MAX98925_GLOBAL_ENABLE,
  123. M98925_EN_SHIFT, 0, NULL, 0),
  124. SND_SOC_DAPM_OUTPUT("BE_OUT"),
  125. };
  126. static const struct snd_soc_dapm_route max98925_audio_map[] = {
  127. {"DAI IN MUX", "Left", "DAI_OUT"},
  128. {"DAI IN MUX", "Right", "DAI_OUT"},
  129. {"DAI IN MUX", "LeftRight", "DAI_OUT"},
  130. {"DAI IN MUX", "LeftRightDiv2", "DAI_OUT"},
  131. {"Rc Filter MUX", "Disable", "DAI IN MUX"},
  132. {"Rc Filter MUX", "DC Block", "DAI IN MUX"},
  133. {"Rc Filter MUX", "100Hz", "DAI IN MUX"},
  134. {"Rc Filter MUX", "200Hz", "DAI IN MUX"},
  135. {"Rc Filter MUX", "400Hz", "DAI IN MUX"},
  136. {"Rc Filter MUX", "800Hz", "DAI IN MUX"},
  137. {"Amp Enable", NULL, "Rc Filter MUX"},
  138. {"BE_OUT", NULL, "Amp Enable"},
  139. {"BE_OUT", NULL, "Global Enable"},
  140. };
  141. static bool max98925_volatile_register(struct device *dev, unsigned int reg)
  142. {
  143. switch (reg) {
  144. case MAX98925_VBAT_DATA:
  145. case MAX98925_VBST_DATA:
  146. case MAX98925_LIVE_STATUS0:
  147. case MAX98925_LIVE_STATUS1:
  148. case MAX98925_LIVE_STATUS2:
  149. case MAX98925_STATE0:
  150. case MAX98925_STATE1:
  151. case MAX98925_STATE2:
  152. case MAX98925_FLAG0:
  153. case MAX98925_FLAG1:
  154. case MAX98925_FLAG2:
  155. case MAX98925_REV_VERSION:
  156. return true;
  157. default:
  158. return false;
  159. }
  160. }
  161. static bool max98925_readable_register(struct device *dev, unsigned int reg)
  162. {
  163. switch (reg) {
  164. case MAX98925_IRQ_CLEAR0:
  165. case MAX98925_IRQ_CLEAR1:
  166. case MAX98925_IRQ_CLEAR2:
  167. case MAX98925_ALC_HOLD_RLS:
  168. return false;
  169. default:
  170. return true;
  171. }
  172. }
  173. static DECLARE_TLV_DB_SCALE(max98925_spk_tlv, -600, 100, 0);
  174. static const struct snd_kcontrol_new max98925_snd_controls[] = {
  175. SOC_SINGLE_TLV("Speaker Volume", MAX98925_GAIN,
  176. M98925_SPK_GAIN_SHIFT, (1<<M98925_SPK_GAIN_WIDTH)-1, 0,
  177. max98925_spk_tlv),
  178. SOC_SINGLE("Ramp Switch", MAX98925_GAIN_RAMPING,
  179. M98925_SPK_RMP_EN_SHIFT, 1, 0),
  180. SOC_SINGLE("ZCD Switch", MAX98925_GAIN_RAMPING,
  181. M98925_SPK_ZCD_EN_SHIFT, 1, 0),
  182. SOC_SINGLE("ALC Switch", MAX98925_THRESHOLD,
  183. M98925_ALC_EN_SHIFT, 1, 0),
  184. SOC_SINGLE("ALC Threshold", MAX98925_THRESHOLD, M98925_ALC_TH_SHIFT,
  185. (1<<M98925_ALC_TH_WIDTH)-1, 0),
  186. SOC_ENUM("Boost Output Voltage", max98925_boost_voltage),
  187. };
  188. /* codec sample rate and n/m dividers parameter table */
  189. static const struct {
  190. int rate;
  191. int sr;
  192. int divisors[3][2];
  193. } rate_table[] = {
  194. {
  195. .rate = 8000,
  196. .sr = 0,
  197. .divisors = { {1, 375}, {5, 1764}, {1, 384} }
  198. },
  199. {
  200. .rate = 11025,
  201. .sr = 1,
  202. .divisors = { {147, 40000}, {1, 256}, {147, 40960} }
  203. },
  204. {
  205. .rate = 12000,
  206. .sr = 2,
  207. .divisors = { {1, 250}, {5, 1176}, {1, 256} }
  208. },
  209. {
  210. .rate = 16000,
  211. .sr = 3,
  212. .divisors = { {2, 375}, {5, 882}, {1, 192} }
  213. },
  214. {
  215. .rate = 22050,
  216. .sr = 4,
  217. .divisors = { {147, 20000}, {1, 128}, {147, 20480} }
  218. },
  219. {
  220. .rate = 24000,
  221. .sr = 5,
  222. .divisors = { {1, 125}, {5, 588}, {1, 128} }
  223. },
  224. {
  225. .rate = 32000,
  226. .sr = 6,
  227. .divisors = { {4, 375}, {5, 441}, {1, 96} }
  228. },
  229. {
  230. .rate = 44100,
  231. .sr = 7,
  232. .divisors = { {147, 10000}, {1, 64}, {147, 10240} }
  233. },
  234. {
  235. .rate = 48000,
  236. .sr = 8,
  237. .divisors = { {2, 125}, {5, 294}, {1, 64} }
  238. },
  239. };
  240. static inline int max98925_rate_value(struct snd_soc_codec *codec,
  241. int rate, int clock, int *value, int *n, int *m)
  242. {
  243. int ret = -EINVAL;
  244. int i;
  245. for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
  246. if (rate_table[i].rate >= rate) {
  247. *value = rate_table[i].sr;
  248. *n = rate_table[i].divisors[clock][0];
  249. *m = rate_table[i].divisors[clock][1];
  250. ret = 0;
  251. break;
  252. }
  253. }
  254. return ret;
  255. }
  256. static void max98925_set_sense_data(struct max98925_priv *max98925)
  257. {
  258. /* set VMON slots */
  259. regmap_update_bits(max98925->regmap,
  260. MAX98925_DOUT_CFG_VMON,
  261. M98925_DAI_VMON_EN_MASK, M98925_DAI_VMON_EN_MASK);
  262. regmap_update_bits(max98925->regmap,
  263. MAX98925_DOUT_CFG_VMON,
  264. M98925_DAI_VMON_SLOT_MASK,
  265. max98925->v_slot << M98925_DAI_VMON_SLOT_SHIFT);
  266. /* set IMON slots */
  267. regmap_update_bits(max98925->regmap,
  268. MAX98925_DOUT_CFG_IMON,
  269. M98925_DAI_IMON_EN_MASK, M98925_DAI_IMON_EN_MASK);
  270. regmap_update_bits(max98925->regmap,
  271. MAX98925_DOUT_CFG_IMON,
  272. M98925_DAI_IMON_SLOT_MASK,
  273. max98925->i_slot << M98925_DAI_IMON_SLOT_SHIFT);
  274. }
  275. static int max98925_dai_set_fmt(struct snd_soc_dai *codec_dai,
  276. unsigned int fmt)
  277. {
  278. struct snd_soc_codec *codec = codec_dai->codec;
  279. struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
  280. unsigned int invert = 0;
  281. dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
  282. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  283. case SND_SOC_DAIFMT_CBS_CFS:
  284. /* set DAI to slave mode */
  285. regmap_update_bits(max98925->regmap,
  286. MAX98925_DAI_CLK_MODE2,
  287. M98925_DAI_MAS_MASK, 0);
  288. max98925_set_sense_data(max98925);
  289. break;
  290. case SND_SOC_DAIFMT_CBM_CFM:
  291. /*
  292. * set left channel DAI to master mode,
  293. * right channel always slave
  294. */
  295. regmap_update_bits(max98925->regmap,
  296. MAX98925_DAI_CLK_MODE2,
  297. M98925_DAI_MAS_MASK, M98925_DAI_MAS_MASK);
  298. break;
  299. case SND_SOC_DAIFMT_CBS_CFM:
  300. case SND_SOC_DAIFMT_CBM_CFS:
  301. default:
  302. dev_err(codec->dev, "DAI clock mode unsupported");
  303. return -EINVAL;
  304. }
  305. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  306. case SND_SOC_DAIFMT_NB_NF:
  307. break;
  308. case SND_SOC_DAIFMT_NB_IF:
  309. invert = M98925_DAI_WCI_MASK;
  310. break;
  311. case SND_SOC_DAIFMT_IB_NF:
  312. invert = M98925_DAI_BCI_MASK;
  313. break;
  314. case SND_SOC_DAIFMT_IB_IF:
  315. invert = M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK;
  316. break;
  317. default:
  318. dev_err(codec->dev, "DAI invert mode unsupported");
  319. return -EINVAL;
  320. }
  321. regmap_update_bits(max98925->regmap, MAX98925_FORMAT,
  322. M98925_DAI_BCI_MASK | M98925_DAI_WCI_MASK, invert);
  323. return 0;
  324. }
  325. static int max98925_set_clock(struct max98925_priv *max98925,
  326. struct snd_pcm_hw_params *params)
  327. {
  328. unsigned int dai_sr = 0, clock, mdll, n, m;
  329. struct snd_soc_codec *codec = max98925->codec;
  330. int rate = params_rate(params);
  331. /* BCLK/LRCLK ratio calculation */
  332. int blr_clk_ratio = params_channels(params) * max98925->ch_size;
  333. switch (blr_clk_ratio) {
  334. case 32:
  335. regmap_update_bits(max98925->regmap,
  336. MAX98925_DAI_CLK_MODE2,
  337. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_32);
  338. break;
  339. case 48:
  340. regmap_update_bits(max98925->regmap,
  341. MAX98925_DAI_CLK_MODE2,
  342. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_48);
  343. break;
  344. case 64:
  345. regmap_update_bits(max98925->regmap,
  346. MAX98925_DAI_CLK_MODE2,
  347. M98925_DAI_BSEL_MASK, M98925_DAI_BSEL_64);
  348. break;
  349. default:
  350. return -EINVAL;
  351. }
  352. switch (max98925->sysclk) {
  353. case 6000000:
  354. clock = 0;
  355. mdll = M98925_MDLL_MULT_MCLKx16;
  356. break;
  357. case 11289600:
  358. clock = 1;
  359. mdll = M98925_MDLL_MULT_MCLKx8;
  360. break;
  361. case 12000000:
  362. clock = 0;
  363. mdll = M98925_MDLL_MULT_MCLKx8;
  364. break;
  365. case 12288000:
  366. clock = 2;
  367. mdll = M98925_MDLL_MULT_MCLKx8;
  368. break;
  369. default:
  370. dev_info(max98925->codec->dev, "unsupported sysclk %d\n",
  371. max98925->sysclk);
  372. return -EINVAL;
  373. }
  374. if (max98925_rate_value(codec, rate, clock, &dai_sr, &n, &m))
  375. return -EINVAL;
  376. /* set DAI_SR to correct LRCLK frequency */
  377. regmap_update_bits(max98925->regmap,
  378. MAX98925_DAI_CLK_MODE2,
  379. M98925_DAI_SR_MASK, dai_sr << M98925_DAI_SR_SHIFT);
  380. /* set DAI m divider */
  381. regmap_write(max98925->regmap,
  382. MAX98925_DAI_CLK_DIV_M_MSBS, m >> 8);
  383. regmap_write(max98925->regmap,
  384. MAX98925_DAI_CLK_DIV_M_LSBS, m & 0xFF);
  385. /* set DAI n divider */
  386. regmap_write(max98925->regmap,
  387. MAX98925_DAI_CLK_DIV_N_MSBS, n >> 8);
  388. regmap_write(max98925->regmap,
  389. MAX98925_DAI_CLK_DIV_N_LSBS, n & 0xFF);
  390. /* set MDLL */
  391. regmap_update_bits(max98925->regmap, MAX98925_DAI_CLK_MODE1,
  392. M98925_MDLL_MULT_MASK, mdll << M98925_MDLL_MULT_SHIFT);
  393. return 0;
  394. }
  395. static int max98925_dai_hw_params(struct snd_pcm_substream *substream,
  396. struct snd_pcm_hw_params *params,
  397. struct snd_soc_dai *dai)
  398. {
  399. struct snd_soc_codec *codec = dai->codec;
  400. struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
  401. switch (params_width(params)) {
  402. case 16:
  403. regmap_update_bits(max98925->regmap,
  404. MAX98925_FORMAT,
  405. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_16);
  406. max98925->ch_size = 16;
  407. break;
  408. case 24:
  409. regmap_update_bits(max98925->regmap,
  410. MAX98925_FORMAT,
  411. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_24);
  412. max98925->ch_size = 24;
  413. break;
  414. case 32:
  415. regmap_update_bits(max98925->regmap,
  416. MAX98925_FORMAT,
  417. M98925_DAI_CHANSZ_MASK, M98925_DAI_CHANSZ_32);
  418. max98925->ch_size = 32;
  419. break;
  420. default:
  421. pr_err("%s: format unsupported %d",
  422. __func__, params_format(params));
  423. return -EINVAL;
  424. }
  425. dev_dbg(codec->dev, "%s: format supported %d",
  426. __func__, params_format(params));
  427. return max98925_set_clock(max98925, params);
  428. }
  429. static int max98925_dai_set_sysclk(struct snd_soc_dai *dai,
  430. int clk_id, unsigned int freq, int dir)
  431. {
  432. struct snd_soc_codec *codec = dai->codec;
  433. struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
  434. switch (clk_id) {
  435. case 0:
  436. /* use MCLK for Left channel, right channel always BCLK */
  437. regmap_update_bits(max98925->regmap,
  438. MAX98925_DAI_CLK_MODE1,
  439. M98925_DAI_CLK_SOURCE_MASK, 0);
  440. break;
  441. case 1:
  442. /* configure dai clock source to BCLK instead of MCLK */
  443. regmap_update_bits(max98925->regmap,
  444. MAX98925_DAI_CLK_MODE1,
  445. M98925_DAI_CLK_SOURCE_MASK,
  446. M98925_DAI_CLK_SOURCE_MASK);
  447. break;
  448. default:
  449. return -EINVAL;
  450. }
  451. max98925->sysclk = freq;
  452. return 0;
  453. }
  454. #define MAX98925_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
  455. SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
  456. static const struct snd_soc_dai_ops max98925_dai_ops = {
  457. .set_sysclk = max98925_dai_set_sysclk,
  458. .set_fmt = max98925_dai_set_fmt,
  459. .hw_params = max98925_dai_hw_params,
  460. };
  461. static struct snd_soc_dai_driver max98925_dai[] = {
  462. {
  463. .name = "max98925-aif1",
  464. .playback = {
  465. .stream_name = "HiFi Playback",
  466. .channels_min = 1,
  467. .channels_max = 2,
  468. .rates = SNDRV_PCM_RATE_8000_48000,
  469. .formats = MAX98925_FORMATS,
  470. },
  471. .capture = {
  472. .stream_name = "HiFi Capture",
  473. .channels_min = 1,
  474. .channels_max = 2,
  475. .rates = SNDRV_PCM_RATE_8000_48000,
  476. .formats = MAX98925_FORMATS,
  477. },
  478. .ops = &max98925_dai_ops,
  479. }
  480. };
  481. static int max98925_probe(struct snd_soc_codec *codec)
  482. {
  483. struct max98925_priv *max98925 = snd_soc_codec_get_drvdata(codec);
  484. max98925->codec = codec;
  485. regmap_write(max98925->regmap, MAX98925_GLOBAL_ENABLE, 0x00);
  486. /* It's not the default but we need to set DAI_DLY */
  487. regmap_write(max98925->regmap,
  488. MAX98925_FORMAT, M98925_DAI_DLY_MASK);
  489. regmap_write(max98925->regmap, MAX98925_TDM_SLOT_SELECT, 0xC8);
  490. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG1, 0xFF);
  491. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG2, 0xFF);
  492. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG3, 0xFF);
  493. regmap_write(max98925->regmap, MAX98925_DOUT_HIZ_CFG4, 0xF0);
  494. regmap_write(max98925->regmap, MAX98925_FILTERS, 0xD8);
  495. regmap_write(max98925->regmap, MAX98925_ALC_CONFIGURATION, 0xF8);
  496. regmap_write(max98925->regmap, MAX98925_CONFIGURATION, 0xF0);
  497. /* Disable ALC muting */
  498. regmap_write(max98925->regmap, MAX98925_BOOST_LIMITER, 0xF8);
  499. return 0;
  500. }
  501. static const struct snd_soc_codec_driver soc_codec_dev_max98925 = {
  502. .probe = max98925_probe,
  503. .component_driver = {
  504. .controls = max98925_snd_controls,
  505. .num_controls = ARRAY_SIZE(max98925_snd_controls),
  506. .dapm_routes = max98925_audio_map,
  507. .num_dapm_routes = ARRAY_SIZE(max98925_audio_map),
  508. .dapm_widgets = max98925_dapm_widgets,
  509. .num_dapm_widgets = ARRAY_SIZE(max98925_dapm_widgets),
  510. },
  511. };
  512. static const struct regmap_config max98925_regmap = {
  513. .reg_bits = 8,
  514. .val_bits = 8,
  515. .max_register = MAX98925_REV_VERSION,
  516. .reg_defaults = max98925_reg,
  517. .num_reg_defaults = ARRAY_SIZE(max98925_reg),
  518. .volatile_reg = max98925_volatile_register,
  519. .readable_reg = max98925_readable_register,
  520. .cache_type = REGCACHE_RBTREE,
  521. };
  522. static int max98925_i2c_probe(struct i2c_client *i2c,
  523. const struct i2c_device_id *id)
  524. {
  525. int ret, reg;
  526. u32 value;
  527. struct max98925_priv *max98925;
  528. max98925 = devm_kzalloc(&i2c->dev,
  529. sizeof(*max98925), GFP_KERNEL);
  530. if (!max98925)
  531. return -ENOMEM;
  532. i2c_set_clientdata(i2c, max98925);
  533. max98925->regmap = devm_regmap_init_i2c(i2c, &max98925_regmap);
  534. if (IS_ERR(max98925->regmap)) {
  535. ret = PTR_ERR(max98925->regmap);
  536. dev_err(&i2c->dev,
  537. "Failed to allocate regmap: %d\n", ret);
  538. goto err_out;
  539. }
  540. if (!of_property_read_u32(i2c->dev.of_node, "vmon-slot-no", &value)) {
  541. if (value > M98925_DAI_VMON_SLOT_1E_1F) {
  542. dev_err(&i2c->dev, "vmon slot number is wrong:\n");
  543. return -EINVAL;
  544. }
  545. max98925->v_slot = value;
  546. }
  547. if (!of_property_read_u32(i2c->dev.of_node, "imon-slot-no", &value)) {
  548. if (value > M98925_DAI_IMON_SLOT_1E_1F) {
  549. dev_err(&i2c->dev, "imon slot number is wrong:\n");
  550. return -EINVAL;
  551. }
  552. max98925->i_slot = value;
  553. }
  554. ret = regmap_read(max98925->regmap,
  555. MAX98925_REV_VERSION, &reg);
  556. if ((ret < 0) ||
  557. ((reg != MAX98925_VERSION) &&
  558. (reg != MAX98925_VERSION1))) {
  559. dev_err(&i2c->dev,
  560. "device initialization error (%d 0x%02X)\n",
  561. ret, reg);
  562. goto err_out;
  563. }
  564. dev_info(&i2c->dev, "device version 0x%02X\n", reg);
  565. ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98925,
  566. max98925_dai, ARRAY_SIZE(max98925_dai));
  567. if (ret < 0)
  568. dev_err(&i2c->dev,
  569. "Failed to register codec: %d\n", ret);
  570. err_out:
  571. return ret;
  572. }
  573. static int max98925_i2c_remove(struct i2c_client *client)
  574. {
  575. snd_soc_unregister_codec(&client->dev);
  576. return 0;
  577. }
  578. static const struct i2c_device_id max98925_i2c_id[] = {
  579. { "max98925", 0 },
  580. { }
  581. };
  582. MODULE_DEVICE_TABLE(i2c, max98925_i2c_id);
  583. static const struct of_device_id max98925_of_match[] = {
  584. { .compatible = "maxim,max98925", },
  585. { }
  586. };
  587. MODULE_DEVICE_TABLE(of, max98925_of_match);
  588. static struct i2c_driver max98925_i2c_driver = {
  589. .driver = {
  590. .name = "max98925",
  591. .of_match_table = of_match_ptr(max98925_of_match),
  592. .pm = NULL,
  593. },
  594. .probe = max98925_i2c_probe,
  595. .remove = max98925_i2c_remove,
  596. .id_table = max98925_i2c_id,
  597. };
  598. module_i2c_driver(max98925_i2c_driver)
  599. MODULE_DESCRIPTION("ALSA SoC MAX98925 driver");
  600. MODULE_AUTHOR("Ralph Birt <rdbirt@gmail.com>, Anish kumar <anish.kumar@maximintegrated.com>");
  601. MODULE_LICENSE("GPL");