dice-stream.c 12 KB

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  1. /*
  2. * dice_stream.c - a part of driver for DICE based devices
  3. *
  4. * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
  5. * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp>
  6. *
  7. * Licensed under the terms of the GNU General Public License, version 2.
  8. */
  9. #include "dice.h"
  10. #define CALLBACK_TIMEOUT 200
  11. #define NOTIFICATION_TIMEOUT_MS (2 * MSEC_PER_SEC)
  12. struct reg_params {
  13. unsigned int count;
  14. unsigned int size;
  15. };
  16. const unsigned int snd_dice_rates[SND_DICE_RATES_COUNT] = {
  17. /* mode 0 */
  18. [0] = 32000,
  19. [1] = 44100,
  20. [2] = 48000,
  21. /* mode 1 */
  22. [3] = 88200,
  23. [4] = 96000,
  24. /* mode 2 */
  25. [5] = 176400,
  26. [6] = 192000,
  27. };
  28. /*
  29. * This operation has an effect to synchronize GLOBAL_STATUS/GLOBAL_SAMPLE_RATE
  30. * to GLOBAL_STATUS. Especially, just after powering on, these are different.
  31. */
  32. static int ensure_phase_lock(struct snd_dice *dice)
  33. {
  34. __be32 reg, nominal;
  35. int err;
  36. err = snd_dice_transaction_read_global(dice, GLOBAL_CLOCK_SELECT,
  37. &reg, sizeof(reg));
  38. if (err < 0)
  39. return err;
  40. if (completion_done(&dice->clock_accepted))
  41. reinit_completion(&dice->clock_accepted);
  42. err = snd_dice_transaction_write_global(dice, GLOBAL_CLOCK_SELECT,
  43. &reg, sizeof(reg));
  44. if (err < 0)
  45. return err;
  46. if (wait_for_completion_timeout(&dice->clock_accepted,
  47. msecs_to_jiffies(NOTIFICATION_TIMEOUT_MS)) == 0) {
  48. /*
  49. * Old versions of Dice firmware transfer no notification when
  50. * the same clock status as current one is set. In this case,
  51. * just check current clock status.
  52. */
  53. err = snd_dice_transaction_read_global(dice, GLOBAL_STATUS,
  54. &nominal, sizeof(nominal));
  55. if (err < 0)
  56. return err;
  57. if (!(be32_to_cpu(nominal) & STATUS_SOURCE_LOCKED))
  58. return -ETIMEDOUT;
  59. }
  60. return 0;
  61. }
  62. static int get_register_params(struct snd_dice *dice,
  63. struct reg_params *tx_params,
  64. struct reg_params *rx_params)
  65. {
  66. __be32 reg[2];
  67. int err;
  68. err = snd_dice_transaction_read_tx(dice, TX_NUMBER, reg, sizeof(reg));
  69. if (err < 0)
  70. return err;
  71. tx_params->count =
  72. min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
  73. tx_params->size = be32_to_cpu(reg[1]) * 4;
  74. err = snd_dice_transaction_read_rx(dice, RX_NUMBER, reg, sizeof(reg));
  75. if (err < 0)
  76. return err;
  77. rx_params->count =
  78. min_t(unsigned int, be32_to_cpu(reg[0]), MAX_STREAMS);
  79. rx_params->size = be32_to_cpu(reg[1]) * 4;
  80. return 0;
  81. }
  82. static void release_resources(struct snd_dice *dice)
  83. {
  84. unsigned int i;
  85. for (i = 0; i < MAX_STREAMS; i++) {
  86. if (amdtp_stream_running(&dice->tx_stream[i])) {
  87. amdtp_stream_pcm_abort(&dice->tx_stream[i]);
  88. amdtp_stream_stop(&dice->tx_stream[i]);
  89. }
  90. if (amdtp_stream_running(&dice->rx_stream[i])) {
  91. amdtp_stream_pcm_abort(&dice->rx_stream[i]);
  92. amdtp_stream_stop(&dice->rx_stream[i]);
  93. }
  94. fw_iso_resources_free(&dice->tx_resources[i]);
  95. fw_iso_resources_free(&dice->rx_resources[i]);
  96. }
  97. }
  98. static void stop_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
  99. struct reg_params *params)
  100. {
  101. __be32 reg;
  102. unsigned int i;
  103. for (i = 0; i < params->count; i++) {
  104. reg = cpu_to_be32((u32)-1);
  105. if (dir == AMDTP_IN_STREAM) {
  106. snd_dice_transaction_write_tx(dice,
  107. params->size * i + TX_ISOCHRONOUS,
  108. &reg, sizeof(reg));
  109. } else {
  110. snd_dice_transaction_write_rx(dice,
  111. params->size * i + RX_ISOCHRONOUS,
  112. &reg, sizeof(reg));
  113. }
  114. }
  115. }
  116. static int keep_resources(struct snd_dice *dice,
  117. enum amdtp_stream_direction dir, unsigned int index,
  118. unsigned int rate, unsigned int pcm_chs,
  119. unsigned int midi_ports)
  120. {
  121. struct amdtp_stream *stream;
  122. struct fw_iso_resources *resources;
  123. bool double_pcm_frames;
  124. unsigned int i;
  125. int err;
  126. if (dir == AMDTP_IN_STREAM) {
  127. stream = &dice->tx_stream[index];
  128. resources = &dice->tx_resources[index];
  129. } else {
  130. stream = &dice->rx_stream[index];
  131. resources = &dice->rx_resources[index];
  132. }
  133. /*
  134. * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in
  135. * one data block of AMDTP packet. Thus sampling transfer frequency is
  136. * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are
  137. * transferred on AMDTP packets at 96 kHz. Two successive samples of a
  138. * channel are stored consecutively in the packet. This quirk is called
  139. * as 'Dual Wire'.
  140. * For this quirk, blocking mode is required and PCM buffer size should
  141. * be aligned to SYT_INTERVAL.
  142. */
  143. double_pcm_frames = rate > 96000;
  144. if (double_pcm_frames) {
  145. rate /= 2;
  146. pcm_chs *= 2;
  147. }
  148. err = amdtp_am824_set_parameters(stream, rate, pcm_chs, midi_ports,
  149. double_pcm_frames);
  150. if (err < 0)
  151. return err;
  152. if (double_pcm_frames) {
  153. pcm_chs /= 2;
  154. for (i = 0; i < pcm_chs; i++) {
  155. amdtp_am824_set_pcm_position(stream, i, i * 2);
  156. amdtp_am824_set_pcm_position(stream, i + pcm_chs,
  157. i * 2 + 1);
  158. }
  159. }
  160. return fw_iso_resources_allocate(resources,
  161. amdtp_stream_get_max_payload(stream),
  162. fw_parent_device(dice->unit)->max_speed);
  163. }
  164. static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir,
  165. unsigned int rate, struct reg_params *params)
  166. {
  167. __be32 reg[2];
  168. unsigned int i, pcm_chs, midi_ports;
  169. struct amdtp_stream *streams;
  170. struct fw_iso_resources *resources;
  171. int err = 0;
  172. if (dir == AMDTP_IN_STREAM) {
  173. streams = dice->tx_stream;
  174. resources = dice->tx_resources;
  175. } else {
  176. streams = dice->rx_stream;
  177. resources = dice->rx_resources;
  178. }
  179. for (i = 0; i < params->count; i++) {
  180. if (dir == AMDTP_IN_STREAM) {
  181. err = snd_dice_transaction_read_tx(dice,
  182. params->size * i + TX_NUMBER_AUDIO,
  183. reg, sizeof(reg));
  184. } else {
  185. err = snd_dice_transaction_read_rx(dice,
  186. params->size * i + RX_NUMBER_AUDIO,
  187. reg, sizeof(reg));
  188. }
  189. if (err < 0)
  190. return err;
  191. pcm_chs = be32_to_cpu(reg[0]);
  192. midi_ports = be32_to_cpu(reg[1]);
  193. err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports);
  194. if (err < 0)
  195. return err;
  196. reg[0] = cpu_to_be32(resources[i].channel);
  197. if (dir == AMDTP_IN_STREAM) {
  198. err = snd_dice_transaction_write_tx(dice,
  199. params->size * i + TX_ISOCHRONOUS,
  200. reg, sizeof(reg[0]));
  201. } else {
  202. err = snd_dice_transaction_write_rx(dice,
  203. params->size * i + RX_ISOCHRONOUS,
  204. reg, sizeof(reg[0]));
  205. }
  206. if (err < 0)
  207. return err;
  208. err = amdtp_stream_start(&streams[i], resources[i].channel,
  209. fw_parent_device(dice->unit)->max_speed);
  210. if (err < 0)
  211. return err;
  212. }
  213. return err;
  214. }
  215. /*
  216. * MEMO: After this function, there're two states of streams:
  217. * - None streams are running.
  218. * - All streams are running.
  219. */
  220. int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate)
  221. {
  222. unsigned int curr_rate;
  223. unsigned int i;
  224. struct reg_params tx_params, rx_params;
  225. bool need_to_start;
  226. int err;
  227. if (dice->substreams_counter == 0)
  228. return -EIO;
  229. err = get_register_params(dice, &tx_params, &rx_params);
  230. if (err < 0)
  231. return err;
  232. err = snd_dice_transaction_get_rate(dice, &curr_rate);
  233. if (err < 0) {
  234. dev_err(&dice->unit->device,
  235. "fail to get sampling rate\n");
  236. return err;
  237. }
  238. if (rate == 0)
  239. rate = curr_rate;
  240. if (rate != curr_rate)
  241. return -EINVAL;
  242. /* Judge to need to restart streams. */
  243. for (i = 0; i < MAX_STREAMS; i++) {
  244. if (i < tx_params.count) {
  245. if (amdtp_streaming_error(&dice->tx_stream[i]) ||
  246. !amdtp_stream_running(&dice->tx_stream[i]))
  247. break;
  248. }
  249. if (i < rx_params.count) {
  250. if (amdtp_streaming_error(&dice->rx_stream[i]) ||
  251. !amdtp_stream_running(&dice->rx_stream[i]))
  252. break;
  253. }
  254. }
  255. need_to_start = (i < MAX_STREAMS);
  256. if (need_to_start) {
  257. /* Stop transmission. */
  258. snd_dice_transaction_clear_enable(dice);
  259. stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
  260. stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
  261. release_resources(dice);
  262. err = ensure_phase_lock(dice);
  263. if (err < 0) {
  264. dev_err(&dice->unit->device,
  265. "fail to ensure phase lock\n");
  266. return err;
  267. }
  268. /* Start both streams. */
  269. err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params);
  270. if (err < 0)
  271. goto error;
  272. err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params);
  273. if (err < 0)
  274. goto error;
  275. err = snd_dice_transaction_set_enable(dice);
  276. if (err < 0) {
  277. dev_err(&dice->unit->device,
  278. "fail to enable interface\n");
  279. goto error;
  280. }
  281. for (i = 0; i < MAX_STREAMS; i++) {
  282. if ((i < tx_params.count &&
  283. !amdtp_stream_wait_callback(&dice->tx_stream[i],
  284. CALLBACK_TIMEOUT)) ||
  285. (i < rx_params.count &&
  286. !amdtp_stream_wait_callback(&dice->rx_stream[i],
  287. CALLBACK_TIMEOUT))) {
  288. err = -ETIMEDOUT;
  289. goto error;
  290. }
  291. }
  292. }
  293. return err;
  294. error:
  295. snd_dice_transaction_clear_enable(dice);
  296. stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
  297. stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
  298. release_resources(dice);
  299. return err;
  300. }
  301. /*
  302. * MEMO: After this function, there're two states of streams:
  303. * - None streams are running.
  304. * - All streams are running.
  305. */
  306. void snd_dice_stream_stop_duplex(struct snd_dice *dice)
  307. {
  308. struct reg_params tx_params, rx_params;
  309. if (dice->substreams_counter > 0)
  310. return;
  311. snd_dice_transaction_clear_enable(dice);
  312. if (get_register_params(dice, &tx_params, &rx_params) == 0) {
  313. stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
  314. stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
  315. }
  316. release_resources(dice);
  317. }
  318. static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir,
  319. unsigned int index)
  320. {
  321. struct amdtp_stream *stream;
  322. struct fw_iso_resources *resources;
  323. int err;
  324. if (dir == AMDTP_IN_STREAM) {
  325. stream = &dice->tx_stream[index];
  326. resources = &dice->tx_resources[index];
  327. } else {
  328. stream = &dice->rx_stream[index];
  329. resources = &dice->rx_resources[index];
  330. }
  331. err = fw_iso_resources_init(resources, dice->unit);
  332. if (err < 0)
  333. goto end;
  334. resources->channels_mask = 0x00000000ffffffffuLL;
  335. err = amdtp_am824_init(stream, dice->unit, dir, CIP_BLOCKING);
  336. if (err < 0) {
  337. amdtp_stream_destroy(stream);
  338. fw_iso_resources_destroy(resources);
  339. }
  340. end:
  341. return err;
  342. }
  343. /*
  344. * This function should be called before starting streams or after stopping
  345. * streams.
  346. */
  347. static void destroy_stream(struct snd_dice *dice,
  348. enum amdtp_stream_direction dir,
  349. unsigned int index)
  350. {
  351. struct amdtp_stream *stream;
  352. struct fw_iso_resources *resources;
  353. if (dir == AMDTP_IN_STREAM) {
  354. stream = &dice->tx_stream[index];
  355. resources = &dice->tx_resources[index];
  356. } else {
  357. stream = &dice->rx_stream[index];
  358. resources = &dice->rx_resources[index];
  359. }
  360. amdtp_stream_destroy(stream);
  361. fw_iso_resources_destroy(resources);
  362. }
  363. int snd_dice_stream_init_duplex(struct snd_dice *dice)
  364. {
  365. int i, err;
  366. for (i = 0; i < MAX_STREAMS; i++) {
  367. err = init_stream(dice, AMDTP_IN_STREAM, i);
  368. if (err < 0) {
  369. for (; i >= 0; i--)
  370. destroy_stream(dice, AMDTP_IN_STREAM, i);
  371. goto end;
  372. }
  373. }
  374. for (i = 0; i < MAX_STREAMS; i++) {
  375. err = init_stream(dice, AMDTP_OUT_STREAM, i);
  376. if (err < 0) {
  377. for (; i >= 0; i--)
  378. destroy_stream(dice, AMDTP_OUT_STREAM, i);
  379. for (i = 0; i < MAX_STREAMS; i++)
  380. destroy_stream(dice, AMDTP_IN_STREAM, i);
  381. break;
  382. }
  383. }
  384. end:
  385. return err;
  386. }
  387. void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
  388. {
  389. unsigned int i;
  390. for (i = 0; i < MAX_STREAMS; i++) {
  391. destroy_stream(dice, AMDTP_IN_STREAM, i);
  392. destroy_stream(dice, AMDTP_OUT_STREAM, i);
  393. }
  394. }
  395. void snd_dice_stream_update_duplex(struct snd_dice *dice)
  396. {
  397. struct reg_params tx_params, rx_params;
  398. /*
  399. * On a bus reset, the DICE firmware disables streaming and then goes
  400. * off contemplating its own navel for hundreds of milliseconds before
  401. * it can react to any of our attempts to reenable streaming. This
  402. * means that we lose synchronization anyway, so we force our streams
  403. * to stop so that the application can restart them in an orderly
  404. * manner.
  405. */
  406. dice->global_enabled = false;
  407. if (get_register_params(dice, &tx_params, &rx_params) == 0) {
  408. stop_streams(dice, AMDTP_IN_STREAM, &tx_params);
  409. stop_streams(dice, AMDTP_OUT_STREAM, &rx_params);
  410. }
  411. }
  412. static void dice_lock_changed(struct snd_dice *dice)
  413. {
  414. dice->dev_lock_changed = true;
  415. wake_up(&dice->hwdep_wait);
  416. }
  417. int snd_dice_stream_lock_try(struct snd_dice *dice)
  418. {
  419. int err;
  420. spin_lock_irq(&dice->lock);
  421. if (dice->dev_lock_count < 0) {
  422. err = -EBUSY;
  423. goto out;
  424. }
  425. if (dice->dev_lock_count++ == 0)
  426. dice_lock_changed(dice);
  427. err = 0;
  428. out:
  429. spin_unlock_irq(&dice->lock);
  430. return err;
  431. }
  432. void snd_dice_stream_lock_release(struct snd_dice *dice)
  433. {
  434. spin_lock_irq(&dice->lock);
  435. if (WARN_ON(dice->dev_lock_count <= 0))
  436. goto out;
  437. if (--dice->dev_lock_count == 0)
  438. dice_lock_changed(dice);
  439. out:
  440. spin_unlock_irq(&dice->lock);
  441. }