dwc3-pci.c 8.1 KB

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  1. /**
  2. * dwc3-pci.c - PCI Specific glue layer
  3. *
  4. * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
  5. *
  6. * Authors: Felipe Balbi <balbi@ti.com>,
  7. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  8. *
  9. * This program is free software: you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 of
  11. * the License as published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/slab.h>
  21. #include <linux/pci.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/gpio/consumer.h>
  25. #include <linux/acpi.h>
  26. #include <linux/delay.h>
  27. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 0xabcd
  28. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI 0xabce
  29. #define PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31 0xabcf
  30. #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
  31. #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
  32. #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
  33. #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
  34. #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
  35. #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
  36. #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
  37. #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
  38. #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
  39. #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
  40. static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
  41. static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
  42. static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
  43. { "reset-gpios", &reset_gpios, 1 },
  44. { "cs-gpios", &cs_gpios, 1 },
  45. { },
  46. };
  47. static int dwc3_pci_quirks(struct pci_dev *pdev, struct platform_device *dwc3)
  48. {
  49. if (pdev->vendor == PCI_VENDOR_ID_AMD &&
  50. pdev->device == PCI_DEVICE_ID_AMD_NL_USB) {
  51. struct property_entry properties[] = {
  52. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  53. PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
  54. PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
  55. PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
  56. PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
  57. PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
  58. PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
  59. PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
  60. PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
  61. PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
  62. PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
  63. /*
  64. * FIXME these quirks should be removed when AMD NL
  65. * tapes out
  66. */
  67. PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
  68. PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
  69. PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
  70. { },
  71. };
  72. return platform_device_add_properties(dwc3, properties);
  73. }
  74. if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
  75. int ret;
  76. struct property_entry properties[] = {
  77. PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
  78. { }
  79. };
  80. ret = platform_device_add_properties(dwc3, properties);
  81. if (ret < 0)
  82. return ret;
  83. if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
  84. struct gpio_desc *gpio;
  85. acpi_dev_add_driver_gpios(ACPI_COMPANION(&pdev->dev),
  86. acpi_dwc3_byt_gpios);
  87. /*
  88. * These GPIOs will turn on the USB2 PHY. Note that we have to
  89. * put the gpio descriptors again here because the phy driver
  90. * might want to grab them, too.
  91. */
  92. gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
  93. if (IS_ERR(gpio))
  94. return PTR_ERR(gpio);
  95. gpiod_set_value_cansleep(gpio, 1);
  96. gpiod_put(gpio);
  97. gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
  98. if (IS_ERR(gpio))
  99. return PTR_ERR(gpio);
  100. if (gpio) {
  101. gpiod_set_value_cansleep(gpio, 1);
  102. gpiod_put(gpio);
  103. usleep_range(10000, 11000);
  104. }
  105. }
  106. }
  107. if (pdev->vendor == PCI_VENDOR_ID_SYNOPSYS &&
  108. (pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 ||
  109. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI ||
  110. pdev->device == PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31)) {
  111. struct property_entry properties[] = {
  112. PROPERTY_ENTRY_BOOL("snps,usb3_lpm_capable"),
  113. PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
  114. PROPERTY_ENTRY_BOOL("snps,dis_enblslpm_quirk"),
  115. { },
  116. };
  117. return platform_device_add_properties(dwc3, properties);
  118. }
  119. return 0;
  120. }
  121. static int dwc3_pci_probe(struct pci_dev *pci,
  122. const struct pci_device_id *id)
  123. {
  124. struct resource res[2];
  125. struct platform_device *dwc3;
  126. int ret;
  127. struct device *dev = &pci->dev;
  128. ret = pcim_enable_device(pci);
  129. if (ret) {
  130. dev_err(dev, "failed to enable pci device\n");
  131. return -ENODEV;
  132. }
  133. pci_set_master(pci);
  134. dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
  135. if (!dwc3) {
  136. dev_err(dev, "couldn't allocate dwc3 device\n");
  137. return -ENOMEM;
  138. }
  139. memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
  140. res[0].start = pci_resource_start(pci, 0);
  141. res[0].end = pci_resource_end(pci, 0);
  142. res[0].name = "dwc_usb3";
  143. res[0].flags = IORESOURCE_MEM;
  144. res[1].start = pci->irq;
  145. res[1].name = "dwc_usb3";
  146. res[1].flags = IORESOURCE_IRQ;
  147. ret = platform_device_add_resources(dwc3, res, ARRAY_SIZE(res));
  148. if (ret) {
  149. dev_err(dev, "couldn't add resources to dwc3 device\n");
  150. goto err;
  151. }
  152. dwc3->dev.parent = dev;
  153. ACPI_COMPANION_SET(&dwc3->dev, ACPI_COMPANION(dev));
  154. ret = dwc3_pci_quirks(pci, dwc3);
  155. if (ret)
  156. goto err;
  157. ret = platform_device_add(dwc3);
  158. if (ret) {
  159. dev_err(dev, "failed to register dwc3 device\n");
  160. goto err;
  161. }
  162. device_init_wakeup(dev, true);
  163. device_set_run_wake(dev, true);
  164. pci_set_drvdata(pci, dwc3);
  165. pm_runtime_put(dev);
  166. return 0;
  167. err:
  168. platform_device_put(dwc3);
  169. return ret;
  170. }
  171. static void dwc3_pci_remove(struct pci_dev *pci)
  172. {
  173. device_init_wakeup(&pci->dev, false);
  174. pm_runtime_get(&pci->dev);
  175. acpi_dev_remove_driver_gpios(ACPI_COMPANION(&pci->dev));
  176. platform_device_unregister(pci_get_drvdata(pci));
  177. }
  178. static const struct pci_device_id dwc3_pci_id_table[] = {
  179. {
  180. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  181. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3),
  182. },
  183. {
  184. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  185. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI),
  186. },
  187. {
  188. PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS,
  189. PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31),
  190. },
  191. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW), },
  192. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT), },
  193. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MRFLD), },
  194. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTLP), },
  195. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SPTH), },
  196. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT), },
  197. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BXT_M), },
  198. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_APL), },
  199. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KBP), },
  200. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GLK), },
  201. { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB), },
  202. { } /* Terminating Entry */
  203. };
  204. MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
  205. #ifdef CONFIG_PM
  206. static int dwc3_pci_runtime_suspend(struct device *dev)
  207. {
  208. if (device_run_wake(dev))
  209. return 0;
  210. return -EBUSY;
  211. }
  212. static int dwc3_pci_runtime_resume(struct device *dev)
  213. {
  214. struct platform_device *dwc3 = dev_get_drvdata(dev);
  215. return pm_runtime_get(&dwc3->dev);
  216. }
  217. #endif /* CONFIG_PM */
  218. #ifdef CONFIG_PM_SLEEP
  219. static int dwc3_pci_pm_dummy(struct device *dev)
  220. {
  221. /*
  222. * There's nothing to do here. No, seriously. Everything is either taken
  223. * care either by PCI subsystem or dwc3/core.c, so we have nothing
  224. * missing here.
  225. *
  226. * So you'd think we didn't need this at all, but PCI subsystem will
  227. * bail out if we don't have a valid callback :-s
  228. */
  229. return 0;
  230. }
  231. #endif /* CONFIG_PM_SLEEP */
  232. static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
  233. SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_pm_dummy, dwc3_pci_pm_dummy)
  234. SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
  235. NULL)
  236. };
  237. static struct pci_driver dwc3_pci_driver = {
  238. .name = "dwc3-pci",
  239. .id_table = dwc3_pci_id_table,
  240. .probe = dwc3_pci_probe,
  241. .remove = dwc3_pci_remove,
  242. .driver = {
  243. .pm = &dwc3_pci_dev_pm_ops,
  244. }
  245. };
  246. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  247. MODULE_LICENSE("GPL v2");
  248. MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
  249. module_pci_driver(dwc3_pci_driver);