pci.c 21 KB

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  1. /*
  2. * Copyright IBM Corp. 2012
  3. *
  4. * Author(s):
  5. * Jan Glauber <jang@linux.vnet.ibm.com>
  6. *
  7. * The System z PCI code is a rewrite from a prototype by
  8. * the following people (Kudoz!):
  9. * Alexander Schmidt
  10. * Christoph Raisch
  11. * Hannes Hering
  12. * Hoang-Nam Nguyen
  13. * Jan-Bernd Themann
  14. * Stefan Roscher
  15. * Thomas Klein
  16. */
  17. #define KMSG_COMPONENT "zpci"
  18. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  19. #include <linux/kernel.h>
  20. #include <linux/slab.h>
  21. #include <linux/err.h>
  22. #include <linux/export.h>
  23. #include <linux/delay.h>
  24. #include <linux/irq.h>
  25. #include <linux/kernel_stat.h>
  26. #include <linux/seq_file.h>
  27. #include <linux/pci.h>
  28. #include <linux/msi.h>
  29. #include <asm/isc.h>
  30. #include <asm/airq.h>
  31. #include <asm/facility.h>
  32. #include <asm/pci_insn.h>
  33. #include <asm/pci_clp.h>
  34. #include <asm/pci_dma.h>
  35. #define DEBUG /* enable pr_debug */
  36. #define SIC_IRQ_MODE_ALL 0
  37. #define SIC_IRQ_MODE_SINGLE 1
  38. #define ZPCI_NR_DMA_SPACES 1
  39. #define ZPCI_NR_DEVICES CONFIG_PCI_NR_FUNCTIONS
  40. /* list of all detected zpci devices */
  41. static LIST_HEAD(zpci_list);
  42. static DEFINE_SPINLOCK(zpci_list_lock);
  43. static struct irq_chip zpci_irq_chip = {
  44. .name = "zPCI",
  45. .irq_unmask = pci_msi_unmask_irq,
  46. .irq_mask = pci_msi_mask_irq,
  47. };
  48. static DECLARE_BITMAP(zpci_domain, ZPCI_NR_DEVICES);
  49. static DEFINE_SPINLOCK(zpci_domain_lock);
  50. static struct airq_iv *zpci_aisb_iv;
  51. static struct airq_iv *zpci_aibv[ZPCI_NR_DEVICES];
  52. /* Adapter interrupt definitions */
  53. static void zpci_irq_handler(struct airq_struct *airq);
  54. static struct airq_struct zpci_airq = {
  55. .handler = zpci_irq_handler,
  56. .isc = PCI_ISC,
  57. };
  58. #define ZPCI_IOMAP_ENTRIES \
  59. min(((unsigned long) CONFIG_PCI_NR_FUNCTIONS * PCI_BAR_COUNT), \
  60. ZPCI_IOMAP_MAX_ENTRIES)
  61. static DEFINE_SPINLOCK(zpci_iomap_lock);
  62. static unsigned long *zpci_iomap_bitmap;
  63. struct zpci_iomap_entry *zpci_iomap_start;
  64. EXPORT_SYMBOL_GPL(zpci_iomap_start);
  65. static struct kmem_cache *zdev_fmb_cache;
  66. struct zpci_dev *get_zdev_by_fid(u32 fid)
  67. {
  68. struct zpci_dev *tmp, *zdev = NULL;
  69. spin_lock(&zpci_list_lock);
  70. list_for_each_entry(tmp, &zpci_list, entry) {
  71. if (tmp->fid == fid) {
  72. zdev = tmp;
  73. break;
  74. }
  75. }
  76. spin_unlock(&zpci_list_lock);
  77. return zdev;
  78. }
  79. static struct zpci_dev *get_zdev_by_bus(struct pci_bus *bus)
  80. {
  81. return (bus && bus->sysdata) ? (struct zpci_dev *) bus->sysdata : NULL;
  82. }
  83. int pci_domain_nr(struct pci_bus *bus)
  84. {
  85. return ((struct zpci_dev *) bus->sysdata)->domain;
  86. }
  87. EXPORT_SYMBOL_GPL(pci_domain_nr);
  88. int pci_proc_domain(struct pci_bus *bus)
  89. {
  90. return pci_domain_nr(bus);
  91. }
  92. EXPORT_SYMBOL_GPL(pci_proc_domain);
  93. /* Modify PCI: Register adapter interruptions */
  94. static int zpci_set_airq(struct zpci_dev *zdev)
  95. {
  96. u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
  97. struct zpci_fib fib = {0};
  98. fib.isc = PCI_ISC;
  99. fib.sum = 1; /* enable summary notifications */
  100. fib.noi = airq_iv_end(zdev->aibv);
  101. fib.aibv = (unsigned long) zdev->aibv->vector;
  102. fib.aibvo = 0; /* each zdev has its own interrupt vector */
  103. fib.aisb = (unsigned long) zpci_aisb_iv->vector + (zdev->aisb/64)*8;
  104. fib.aisbo = zdev->aisb & 63;
  105. return zpci_mod_fc(req, &fib);
  106. }
  107. struct mod_pci_args {
  108. u64 base;
  109. u64 limit;
  110. u64 iota;
  111. u64 fmb_addr;
  112. };
  113. static int mod_pci(struct zpci_dev *zdev, int fn, u8 dmaas, struct mod_pci_args *args)
  114. {
  115. u64 req = ZPCI_CREATE_REQ(zdev->fh, dmaas, fn);
  116. struct zpci_fib fib = {0};
  117. fib.pba = args->base;
  118. fib.pal = args->limit;
  119. fib.iota = args->iota;
  120. fib.fmb_addr = args->fmb_addr;
  121. return zpci_mod_fc(req, &fib);
  122. }
  123. /* Modify PCI: Register I/O address translation parameters */
  124. int zpci_register_ioat(struct zpci_dev *zdev, u8 dmaas,
  125. u64 base, u64 limit, u64 iota)
  126. {
  127. struct mod_pci_args args = { base, limit, iota, 0 };
  128. WARN_ON_ONCE(iota & 0x3fff);
  129. args.iota |= ZPCI_IOTA_RTTO_FLAG;
  130. return mod_pci(zdev, ZPCI_MOD_FC_REG_IOAT, dmaas, &args);
  131. }
  132. /* Modify PCI: Unregister I/O address translation parameters */
  133. int zpci_unregister_ioat(struct zpci_dev *zdev, u8 dmaas)
  134. {
  135. struct mod_pci_args args = { 0, 0, 0, 0 };
  136. return mod_pci(zdev, ZPCI_MOD_FC_DEREG_IOAT, dmaas, &args);
  137. }
  138. /* Modify PCI: Unregister adapter interruptions */
  139. static int zpci_clear_airq(struct zpci_dev *zdev)
  140. {
  141. struct mod_pci_args args = { 0, 0, 0, 0 };
  142. return mod_pci(zdev, ZPCI_MOD_FC_DEREG_INT, 0, &args);
  143. }
  144. /* Modify PCI: Set PCI function measurement parameters */
  145. int zpci_fmb_enable_device(struct zpci_dev *zdev)
  146. {
  147. struct mod_pci_args args = { 0, 0, 0, 0 };
  148. if (zdev->fmb)
  149. return -EINVAL;
  150. zdev->fmb = kmem_cache_zalloc(zdev_fmb_cache, GFP_KERNEL);
  151. if (!zdev->fmb)
  152. return -ENOMEM;
  153. WARN_ON((u64) zdev->fmb & 0xf);
  154. /* reset software counters */
  155. atomic64_set(&zdev->allocated_pages, 0);
  156. atomic64_set(&zdev->mapped_pages, 0);
  157. atomic64_set(&zdev->unmapped_pages, 0);
  158. args.fmb_addr = virt_to_phys(zdev->fmb);
  159. return mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args);
  160. }
  161. /* Modify PCI: Disable PCI function measurement */
  162. int zpci_fmb_disable_device(struct zpci_dev *zdev)
  163. {
  164. struct mod_pci_args args = { 0, 0, 0, 0 };
  165. int rc;
  166. if (!zdev->fmb)
  167. return -EINVAL;
  168. /* Function measurement is disabled if fmb address is zero */
  169. rc = mod_pci(zdev, ZPCI_MOD_FC_SET_MEASURE, 0, &args);
  170. kmem_cache_free(zdev_fmb_cache, zdev->fmb);
  171. zdev->fmb = NULL;
  172. return rc;
  173. }
  174. #define ZPCI_PCIAS_CFGSPC 15
  175. static int zpci_cfg_load(struct zpci_dev *zdev, int offset, u32 *val, u8 len)
  176. {
  177. u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
  178. u64 data;
  179. int rc;
  180. rc = zpci_load(&data, req, offset);
  181. if (!rc) {
  182. data = data << ((8 - len) * 8);
  183. data = le64_to_cpu(data);
  184. *val = (u32) data;
  185. } else
  186. *val = 0xffffffff;
  187. return rc;
  188. }
  189. static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
  190. {
  191. u64 req = ZPCI_CREATE_REQ(zdev->fh, ZPCI_PCIAS_CFGSPC, len);
  192. u64 data = val;
  193. int rc;
  194. data = cpu_to_le64(data);
  195. data = data >> ((8 - len) * 8);
  196. rc = zpci_store(data, req, offset);
  197. return rc;
  198. }
  199. void pcibios_fixup_bus(struct pci_bus *bus)
  200. {
  201. }
  202. resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  203. resource_size_t size,
  204. resource_size_t align)
  205. {
  206. return 0;
  207. }
  208. /* combine single writes by using store-block insn */
  209. void __iowrite64_copy(void __iomem *to, const void *from, size_t count)
  210. {
  211. zpci_memcpy_toio(to, from, count);
  212. }
  213. /* Create a virtual mapping cookie for a PCI BAR */
  214. void __iomem *pci_iomap_range(struct pci_dev *pdev,
  215. int bar,
  216. unsigned long offset,
  217. unsigned long max)
  218. {
  219. struct zpci_dev *zdev = to_zpci(pdev);
  220. int idx;
  221. if (!pci_resource_len(pdev, bar))
  222. return NULL;
  223. idx = zdev->bars[bar].map_idx;
  224. spin_lock(&zpci_iomap_lock);
  225. /* Detect overrun */
  226. WARN_ON(!++zpci_iomap_start[idx].count);
  227. zpci_iomap_start[idx].fh = zdev->fh;
  228. zpci_iomap_start[idx].bar = bar;
  229. spin_unlock(&zpci_iomap_lock);
  230. return (void __iomem *) ZPCI_ADDR(idx) + offset;
  231. }
  232. EXPORT_SYMBOL(pci_iomap_range);
  233. void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
  234. {
  235. return pci_iomap_range(dev, bar, 0, maxlen);
  236. }
  237. EXPORT_SYMBOL(pci_iomap);
  238. void pci_iounmap(struct pci_dev *pdev, void __iomem *addr)
  239. {
  240. unsigned int idx = ZPCI_IDX(addr);
  241. spin_lock(&zpci_iomap_lock);
  242. /* Detect underrun */
  243. WARN_ON(!zpci_iomap_start[idx].count);
  244. if (!--zpci_iomap_start[idx].count) {
  245. zpci_iomap_start[idx].fh = 0;
  246. zpci_iomap_start[idx].bar = 0;
  247. }
  248. spin_unlock(&zpci_iomap_lock);
  249. }
  250. EXPORT_SYMBOL(pci_iounmap);
  251. static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  252. int size, u32 *val)
  253. {
  254. struct zpci_dev *zdev = get_zdev_by_bus(bus);
  255. int ret;
  256. if (!zdev || devfn != ZPCI_DEVFN)
  257. ret = -ENODEV;
  258. else
  259. ret = zpci_cfg_load(zdev, where, val, size);
  260. return ret;
  261. }
  262. static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
  263. int size, u32 val)
  264. {
  265. struct zpci_dev *zdev = get_zdev_by_bus(bus);
  266. int ret;
  267. if (!zdev || devfn != ZPCI_DEVFN)
  268. ret = -ENODEV;
  269. else
  270. ret = zpci_cfg_store(zdev, where, val, size);
  271. return ret;
  272. }
  273. static struct pci_ops pci_root_ops = {
  274. .read = pci_read,
  275. .write = pci_write,
  276. };
  277. static void zpci_irq_handler(struct airq_struct *airq)
  278. {
  279. unsigned long si, ai;
  280. struct airq_iv *aibv;
  281. int irqs_on = 0;
  282. inc_irq_stat(IRQIO_PCI);
  283. for (si = 0;;) {
  284. /* Scan adapter summary indicator bit vector */
  285. si = airq_iv_scan(zpci_aisb_iv, si, airq_iv_end(zpci_aisb_iv));
  286. if (si == -1UL) {
  287. if (irqs_on++)
  288. /* End of second scan with interrupts on. */
  289. break;
  290. /* First scan complete, reenable interrupts. */
  291. if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC))
  292. break;
  293. si = 0;
  294. continue;
  295. }
  296. /* Scan the adapter interrupt vector for this device. */
  297. aibv = zpci_aibv[si];
  298. for (ai = 0;;) {
  299. ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
  300. if (ai == -1UL)
  301. break;
  302. inc_irq_stat(IRQIO_MSI);
  303. airq_iv_lock(aibv, ai);
  304. generic_handle_irq(airq_iv_get_data(aibv, ai));
  305. airq_iv_unlock(aibv, ai);
  306. }
  307. }
  308. }
  309. int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  310. {
  311. struct zpci_dev *zdev = to_zpci(pdev);
  312. unsigned int hwirq, msi_vecs;
  313. unsigned long aisb;
  314. struct msi_desc *msi;
  315. struct msi_msg msg;
  316. int rc, irq;
  317. if (type == PCI_CAP_ID_MSI && nvec > 1)
  318. return 1;
  319. msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
  320. /* Allocate adapter summary indicator bit */
  321. rc = -EIO;
  322. aisb = airq_iv_alloc_bit(zpci_aisb_iv);
  323. if (aisb == -1UL)
  324. goto out;
  325. zdev->aisb = aisb;
  326. /* Create adapter interrupt vector */
  327. rc = -ENOMEM;
  328. zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
  329. if (!zdev->aibv)
  330. goto out_si;
  331. /* Wire up shortcut pointer */
  332. zpci_aibv[aisb] = zdev->aibv;
  333. /* Request MSI interrupts */
  334. hwirq = 0;
  335. for_each_pci_msi_entry(msi, pdev) {
  336. rc = -EIO;
  337. irq = irq_alloc_desc(0); /* Alloc irq on node 0 */
  338. if (irq < 0)
  339. goto out_msi;
  340. rc = irq_set_msi_desc(irq, msi);
  341. if (rc)
  342. goto out_msi;
  343. irq_set_chip_and_handler(irq, &zpci_irq_chip,
  344. handle_simple_irq);
  345. msg.data = hwirq;
  346. msg.address_lo = zdev->msi_addr & 0xffffffff;
  347. msg.address_hi = zdev->msi_addr >> 32;
  348. pci_write_msi_msg(irq, &msg);
  349. airq_iv_set_data(zdev->aibv, hwirq, irq);
  350. hwirq++;
  351. }
  352. /* Enable adapter interrupts */
  353. rc = zpci_set_airq(zdev);
  354. if (rc)
  355. goto out_msi;
  356. return (msi_vecs == nvec) ? 0 : msi_vecs;
  357. out_msi:
  358. for_each_pci_msi_entry(msi, pdev) {
  359. if (hwirq-- == 0)
  360. break;
  361. irq_set_msi_desc(msi->irq, NULL);
  362. irq_free_desc(msi->irq);
  363. msi->msg.address_lo = 0;
  364. msi->msg.address_hi = 0;
  365. msi->msg.data = 0;
  366. msi->irq = 0;
  367. }
  368. zpci_aibv[aisb] = NULL;
  369. airq_iv_release(zdev->aibv);
  370. out_si:
  371. airq_iv_free_bit(zpci_aisb_iv, aisb);
  372. out:
  373. return rc;
  374. }
  375. void arch_teardown_msi_irqs(struct pci_dev *pdev)
  376. {
  377. struct zpci_dev *zdev = to_zpci(pdev);
  378. struct msi_desc *msi;
  379. int rc;
  380. /* Disable adapter interrupts */
  381. rc = zpci_clear_airq(zdev);
  382. if (rc)
  383. return;
  384. /* Release MSI interrupts */
  385. for_each_pci_msi_entry(msi, pdev) {
  386. if (msi->msi_attrib.is_msix)
  387. __pci_msix_desc_mask_irq(msi, 1);
  388. else
  389. __pci_msi_desc_mask_irq(msi, 1, 1);
  390. irq_set_msi_desc(msi->irq, NULL);
  391. irq_free_desc(msi->irq);
  392. msi->msg.address_lo = 0;
  393. msi->msg.address_hi = 0;
  394. msi->msg.data = 0;
  395. msi->irq = 0;
  396. }
  397. zpci_aibv[zdev->aisb] = NULL;
  398. airq_iv_release(zdev->aibv);
  399. airq_iv_free_bit(zpci_aisb_iv, zdev->aisb);
  400. }
  401. static void zpci_map_resources(struct pci_dev *pdev)
  402. {
  403. resource_size_t len;
  404. int i;
  405. for (i = 0; i < PCI_BAR_COUNT; i++) {
  406. len = pci_resource_len(pdev, i);
  407. if (!len)
  408. continue;
  409. pdev->resource[i].start =
  410. (resource_size_t __force) pci_iomap(pdev, i, 0);
  411. pdev->resource[i].end = pdev->resource[i].start + len - 1;
  412. }
  413. }
  414. static void zpci_unmap_resources(struct pci_dev *pdev)
  415. {
  416. resource_size_t len;
  417. int i;
  418. for (i = 0; i < PCI_BAR_COUNT; i++) {
  419. len = pci_resource_len(pdev, i);
  420. if (!len)
  421. continue;
  422. pci_iounmap(pdev, (void __iomem __force *)
  423. pdev->resource[i].start);
  424. }
  425. }
  426. static int __init zpci_irq_init(void)
  427. {
  428. int rc;
  429. rc = register_adapter_interrupt(&zpci_airq);
  430. if (rc)
  431. goto out;
  432. /* Set summary to 1 to be called every time for the ISC. */
  433. *zpci_airq.lsi_ptr = 1;
  434. rc = -ENOMEM;
  435. zpci_aisb_iv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
  436. if (!zpci_aisb_iv)
  437. goto out_airq;
  438. zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, NULL, PCI_ISC);
  439. return 0;
  440. out_airq:
  441. unregister_adapter_interrupt(&zpci_airq);
  442. out:
  443. return rc;
  444. }
  445. static void zpci_irq_exit(void)
  446. {
  447. airq_iv_release(zpci_aisb_iv);
  448. unregister_adapter_interrupt(&zpci_airq);
  449. }
  450. static int zpci_alloc_iomap(struct zpci_dev *zdev)
  451. {
  452. unsigned long entry;
  453. spin_lock(&zpci_iomap_lock);
  454. entry = find_first_zero_bit(zpci_iomap_bitmap, ZPCI_IOMAP_ENTRIES);
  455. if (entry == ZPCI_IOMAP_ENTRIES) {
  456. spin_unlock(&zpci_iomap_lock);
  457. return -ENOSPC;
  458. }
  459. set_bit(entry, zpci_iomap_bitmap);
  460. spin_unlock(&zpci_iomap_lock);
  461. return entry;
  462. }
  463. static void zpci_free_iomap(struct zpci_dev *zdev, int entry)
  464. {
  465. spin_lock(&zpci_iomap_lock);
  466. memset(&zpci_iomap_start[entry], 0, sizeof(struct zpci_iomap_entry));
  467. clear_bit(entry, zpci_iomap_bitmap);
  468. spin_unlock(&zpci_iomap_lock);
  469. }
  470. static struct resource *__alloc_res(struct zpci_dev *zdev, unsigned long start,
  471. unsigned long size, unsigned long flags)
  472. {
  473. struct resource *r;
  474. r = kzalloc(sizeof(*r), GFP_KERNEL);
  475. if (!r)
  476. return NULL;
  477. r->start = start;
  478. r->end = r->start + size - 1;
  479. r->flags = flags;
  480. r->name = zdev->res_name;
  481. if (request_resource(&iomem_resource, r)) {
  482. kfree(r);
  483. return NULL;
  484. }
  485. return r;
  486. }
  487. static int zpci_setup_bus_resources(struct zpci_dev *zdev,
  488. struct list_head *resources)
  489. {
  490. unsigned long addr, size, flags;
  491. struct resource *res;
  492. int i, entry;
  493. snprintf(zdev->res_name, sizeof(zdev->res_name),
  494. "PCI Bus %04x:%02x", zdev->domain, ZPCI_BUS_NR);
  495. for (i = 0; i < PCI_BAR_COUNT; i++) {
  496. if (!zdev->bars[i].size)
  497. continue;
  498. entry = zpci_alloc_iomap(zdev);
  499. if (entry < 0)
  500. return entry;
  501. zdev->bars[i].map_idx = entry;
  502. /* only MMIO is supported */
  503. flags = IORESOURCE_MEM;
  504. if (zdev->bars[i].val & 8)
  505. flags |= IORESOURCE_PREFETCH;
  506. if (zdev->bars[i].val & 4)
  507. flags |= IORESOURCE_MEM_64;
  508. addr = ZPCI_ADDR(entry);
  509. size = 1UL << zdev->bars[i].size;
  510. res = __alloc_res(zdev, addr, size, flags);
  511. if (!res) {
  512. zpci_free_iomap(zdev, entry);
  513. return -ENOMEM;
  514. }
  515. zdev->bars[i].res = res;
  516. pci_add_resource(resources, res);
  517. }
  518. return 0;
  519. }
  520. static void zpci_cleanup_bus_resources(struct zpci_dev *zdev)
  521. {
  522. int i;
  523. for (i = 0; i < PCI_BAR_COUNT; i++) {
  524. if (!zdev->bars[i].size || !zdev->bars[i].res)
  525. continue;
  526. zpci_free_iomap(zdev, zdev->bars[i].map_idx);
  527. release_resource(zdev->bars[i].res);
  528. kfree(zdev->bars[i].res);
  529. }
  530. }
  531. int pcibios_add_device(struct pci_dev *pdev)
  532. {
  533. struct resource *res;
  534. int i;
  535. pdev->dev.groups = zpci_attr_groups;
  536. pdev->dev.archdata.dma_ops = &s390_pci_dma_ops;
  537. zpci_map_resources(pdev);
  538. for (i = 0; i < PCI_BAR_COUNT; i++) {
  539. res = &pdev->resource[i];
  540. if (res->parent || !res->flags)
  541. continue;
  542. pci_claim_resource(pdev, i);
  543. }
  544. return 0;
  545. }
  546. void pcibios_release_device(struct pci_dev *pdev)
  547. {
  548. zpci_unmap_resources(pdev);
  549. }
  550. int pcibios_enable_device(struct pci_dev *pdev, int mask)
  551. {
  552. struct zpci_dev *zdev = to_zpci(pdev);
  553. zpci_debug_init_device(zdev, dev_name(&pdev->dev));
  554. zpci_fmb_enable_device(zdev);
  555. return pci_enable_resources(pdev, mask);
  556. }
  557. void pcibios_disable_device(struct pci_dev *pdev)
  558. {
  559. struct zpci_dev *zdev = to_zpci(pdev);
  560. zpci_fmb_disable_device(zdev);
  561. zpci_debug_exit_device(zdev);
  562. }
  563. #ifdef CONFIG_HIBERNATE_CALLBACKS
  564. static int zpci_restore(struct device *dev)
  565. {
  566. struct pci_dev *pdev = to_pci_dev(dev);
  567. struct zpci_dev *zdev = to_zpci(pdev);
  568. int ret = 0;
  569. if (zdev->state != ZPCI_FN_STATE_ONLINE)
  570. goto out;
  571. ret = clp_enable_fh(zdev, ZPCI_NR_DMA_SPACES);
  572. if (ret)
  573. goto out;
  574. zpci_map_resources(pdev);
  575. zpci_register_ioat(zdev, 0, zdev->start_dma, zdev->end_dma,
  576. (u64) zdev->dma_table);
  577. out:
  578. return ret;
  579. }
  580. static int zpci_freeze(struct device *dev)
  581. {
  582. struct pci_dev *pdev = to_pci_dev(dev);
  583. struct zpci_dev *zdev = to_zpci(pdev);
  584. if (zdev->state != ZPCI_FN_STATE_ONLINE)
  585. return 0;
  586. zpci_unregister_ioat(zdev, 0);
  587. zpci_unmap_resources(pdev);
  588. return clp_disable_fh(zdev);
  589. }
  590. struct dev_pm_ops pcibios_pm_ops = {
  591. .thaw_noirq = zpci_restore,
  592. .freeze_noirq = zpci_freeze,
  593. .restore_noirq = zpci_restore,
  594. .poweroff_noirq = zpci_freeze,
  595. };
  596. #endif /* CONFIG_HIBERNATE_CALLBACKS */
  597. static int zpci_alloc_domain(struct zpci_dev *zdev)
  598. {
  599. spin_lock(&zpci_domain_lock);
  600. zdev->domain = find_first_zero_bit(zpci_domain, ZPCI_NR_DEVICES);
  601. if (zdev->domain == ZPCI_NR_DEVICES) {
  602. spin_unlock(&zpci_domain_lock);
  603. return -ENOSPC;
  604. }
  605. set_bit(zdev->domain, zpci_domain);
  606. spin_unlock(&zpci_domain_lock);
  607. return 0;
  608. }
  609. static void zpci_free_domain(struct zpci_dev *zdev)
  610. {
  611. spin_lock(&zpci_domain_lock);
  612. clear_bit(zdev->domain, zpci_domain);
  613. spin_unlock(&zpci_domain_lock);
  614. }
  615. void pcibios_remove_bus(struct pci_bus *bus)
  616. {
  617. struct zpci_dev *zdev = get_zdev_by_bus(bus);
  618. zpci_exit_slot(zdev);
  619. zpci_cleanup_bus_resources(zdev);
  620. zpci_free_domain(zdev);
  621. spin_lock(&zpci_list_lock);
  622. list_del(&zdev->entry);
  623. spin_unlock(&zpci_list_lock);
  624. kfree(zdev);
  625. }
  626. static int zpci_scan_bus(struct zpci_dev *zdev)
  627. {
  628. LIST_HEAD(resources);
  629. int ret;
  630. ret = zpci_setup_bus_resources(zdev, &resources);
  631. if (ret)
  632. goto error;
  633. zdev->bus = pci_scan_root_bus(NULL, ZPCI_BUS_NR, &pci_root_ops,
  634. zdev, &resources);
  635. if (!zdev->bus) {
  636. ret = -EIO;
  637. goto error;
  638. }
  639. zdev->bus->max_bus_speed = zdev->max_bus_speed;
  640. pci_bus_add_devices(zdev->bus);
  641. return 0;
  642. error:
  643. zpci_cleanup_bus_resources(zdev);
  644. pci_free_resource_list(&resources);
  645. return ret;
  646. }
  647. int zpci_enable_device(struct zpci_dev *zdev)
  648. {
  649. int rc;
  650. rc = clp_enable_fh(zdev, ZPCI_NR_DMA_SPACES);
  651. if (rc)
  652. goto out;
  653. rc = zpci_dma_init_device(zdev);
  654. if (rc)
  655. goto out_dma;
  656. zdev->state = ZPCI_FN_STATE_ONLINE;
  657. return 0;
  658. out_dma:
  659. clp_disable_fh(zdev);
  660. out:
  661. return rc;
  662. }
  663. EXPORT_SYMBOL_GPL(zpci_enable_device);
  664. int zpci_disable_device(struct zpci_dev *zdev)
  665. {
  666. zpci_dma_exit_device(zdev);
  667. return clp_disable_fh(zdev);
  668. }
  669. EXPORT_SYMBOL_GPL(zpci_disable_device);
  670. int zpci_create_device(struct zpci_dev *zdev)
  671. {
  672. int rc;
  673. rc = zpci_alloc_domain(zdev);
  674. if (rc)
  675. goto out;
  676. mutex_init(&zdev->lock);
  677. if (zdev->state == ZPCI_FN_STATE_CONFIGURED) {
  678. rc = zpci_enable_device(zdev);
  679. if (rc)
  680. goto out_free;
  681. }
  682. rc = zpci_scan_bus(zdev);
  683. if (rc)
  684. goto out_disable;
  685. spin_lock(&zpci_list_lock);
  686. list_add_tail(&zdev->entry, &zpci_list);
  687. spin_unlock(&zpci_list_lock);
  688. zpci_init_slot(zdev);
  689. return 0;
  690. out_disable:
  691. if (zdev->state == ZPCI_FN_STATE_ONLINE)
  692. zpci_disable_device(zdev);
  693. out_free:
  694. zpci_free_domain(zdev);
  695. out:
  696. return rc;
  697. }
  698. void zpci_stop_device(struct zpci_dev *zdev)
  699. {
  700. zpci_dma_exit_device(zdev);
  701. /*
  702. * Note: SCLP disables fh via set-pci-fn so don't
  703. * do that here.
  704. */
  705. }
  706. EXPORT_SYMBOL_GPL(zpci_stop_device);
  707. int zpci_report_error(struct pci_dev *pdev,
  708. struct zpci_report_error_header *report)
  709. {
  710. struct zpci_dev *zdev = to_zpci(pdev);
  711. return sclp_pci_report(report, zdev->fh, zdev->fid);
  712. }
  713. EXPORT_SYMBOL(zpci_report_error);
  714. static inline int barsize(u8 size)
  715. {
  716. return (size) ? (1 << size) >> 10 : 0;
  717. }
  718. static int zpci_mem_init(void)
  719. {
  720. BUILD_BUG_ON(!is_power_of_2(__alignof__(struct zpci_fmb)) ||
  721. __alignof__(struct zpci_fmb) < sizeof(struct zpci_fmb));
  722. zdev_fmb_cache = kmem_cache_create("PCI_FMB_cache", sizeof(struct zpci_fmb),
  723. __alignof__(struct zpci_fmb), 0, NULL);
  724. if (!zdev_fmb_cache)
  725. goto error_fmb;
  726. zpci_iomap_start = kcalloc(ZPCI_IOMAP_ENTRIES,
  727. sizeof(*zpci_iomap_start), GFP_KERNEL);
  728. if (!zpci_iomap_start)
  729. goto error_iomap;
  730. zpci_iomap_bitmap = kcalloc(BITS_TO_LONGS(ZPCI_IOMAP_ENTRIES),
  731. sizeof(*zpci_iomap_bitmap), GFP_KERNEL);
  732. if (!zpci_iomap_bitmap)
  733. goto error_iomap_bitmap;
  734. return 0;
  735. error_iomap_bitmap:
  736. kfree(zpci_iomap_start);
  737. error_iomap:
  738. kmem_cache_destroy(zdev_fmb_cache);
  739. error_fmb:
  740. return -ENOMEM;
  741. }
  742. static void zpci_mem_exit(void)
  743. {
  744. kfree(zpci_iomap_bitmap);
  745. kfree(zpci_iomap_start);
  746. kmem_cache_destroy(zdev_fmb_cache);
  747. }
  748. static unsigned int s390_pci_probe = 1;
  749. static unsigned int s390_pci_initialized;
  750. char * __init pcibios_setup(char *str)
  751. {
  752. if (!strcmp(str, "off")) {
  753. s390_pci_probe = 0;
  754. return NULL;
  755. }
  756. return str;
  757. }
  758. bool zpci_is_enabled(void)
  759. {
  760. return s390_pci_initialized;
  761. }
  762. static int __init pci_base_init(void)
  763. {
  764. int rc;
  765. if (!s390_pci_probe)
  766. return 0;
  767. if (!test_facility(69) || !test_facility(71))
  768. return 0;
  769. rc = zpci_debug_init();
  770. if (rc)
  771. goto out;
  772. rc = zpci_mem_init();
  773. if (rc)
  774. goto out_mem;
  775. rc = zpci_irq_init();
  776. if (rc)
  777. goto out_irq;
  778. rc = zpci_dma_init();
  779. if (rc)
  780. goto out_dma;
  781. rc = clp_scan_pci_devices();
  782. if (rc)
  783. goto out_find;
  784. s390_pci_initialized = 1;
  785. return 0;
  786. out_find:
  787. zpci_dma_exit();
  788. out_dma:
  789. zpci_irq_exit();
  790. out_irq:
  791. zpci_mem_exit();
  792. out_mem:
  793. zpci_debug_exit();
  794. out:
  795. return rc;
  796. }
  797. subsys_initcall_sync(pci_base_init);
  798. void zpci_rescan(void)
  799. {
  800. if (zpci_is_enabled())
  801. clp_rescan_pci_devices_simple();
  802. }