dma.c 5.3 KB

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  1. /* Wrapper for DMA channel allocator that starts clocks etc */
  2. #include <linux/kernel.h>
  3. #include <linux/spinlock.h>
  4. #include <asm/dma.h>
  5. #include <hwregs/reg_map.h>
  6. #include <hwregs/reg_rdwr.h>
  7. #include <hwregs/marb_defs.h>
  8. #include <hwregs/config_defs.h>
  9. #include <hwregs/strmux_defs.h>
  10. #include <linux/errno.h>
  11. #include <mach/arbiter.h>
  12. static char used_dma_channels[MAX_DMA_CHANNELS];
  13. static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
  14. static DEFINE_SPINLOCK(dma_lock);
  15. int crisv32_request_dma(unsigned int dmanr, const char *device_id,
  16. unsigned options, unsigned int bandwidth,
  17. enum dma_owner owner)
  18. {
  19. unsigned long flags;
  20. reg_config_rw_clk_ctrl clk_ctrl;
  21. reg_strmux_rw_cfg strmux_cfg;
  22. if (crisv32_arbiter_allocate_bandwidth(dmanr,
  23. options & DMA_INT_MEM ?
  24. INT_REGION : EXT_REGION,
  25. bandwidth))
  26. return -ENOMEM;
  27. spin_lock_irqsave(&dma_lock, flags);
  28. if (used_dma_channels[dmanr]) {
  29. spin_unlock_irqrestore(&dma_lock, flags);
  30. if (options & DMA_VERBOSE_ON_ERROR) {
  31. printk(KERN_ERR "Failed to request DMA %i for %s, "
  32. "already allocated by %s\n",
  33. dmanr,
  34. device_id,
  35. used_dma_channels_users[dmanr]);
  36. }
  37. if (options & DMA_PANIC_ON_ERROR)
  38. panic("request_dma error!");
  39. return -EBUSY;
  40. }
  41. clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
  42. strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
  43. switch (dmanr) {
  44. case 0:
  45. case 1:
  46. clk_ctrl.dma01_eth0 = 1;
  47. break;
  48. case 2:
  49. case 3:
  50. clk_ctrl.dma23 = 1;
  51. break;
  52. case 4:
  53. case 5:
  54. clk_ctrl.dma45 = 1;
  55. break;
  56. case 6:
  57. case 7:
  58. clk_ctrl.dma67 = 1;
  59. break;
  60. case 8:
  61. case 9:
  62. clk_ctrl.dma89_strcop = 1;
  63. break;
  64. #if MAX_DMA_CHANNELS-1 != 9
  65. #error Check dma.c
  66. #endif
  67. default:
  68. spin_unlock_irqrestore(&dma_lock, flags);
  69. if (options & DMA_VERBOSE_ON_ERROR) {
  70. printk(KERN_ERR "Failed to request DMA %i for %s, "
  71. "only 0-%i valid)\n",
  72. dmanr, device_id, MAX_DMA_CHANNELS - 1);
  73. }
  74. if (options & DMA_PANIC_ON_ERROR)
  75. panic("request_dma error!");
  76. return -EINVAL;
  77. }
  78. switch (owner) {
  79. case dma_eth0:
  80. if (dmanr == 0)
  81. strmux_cfg.dma0 = regk_strmux_eth0;
  82. else if (dmanr == 1)
  83. strmux_cfg.dma1 = regk_strmux_eth0;
  84. else
  85. panic("Invalid DMA channel for eth0\n");
  86. break;
  87. case dma_eth1:
  88. if (dmanr == 6)
  89. strmux_cfg.dma6 = regk_strmux_eth1;
  90. else if (dmanr == 7)
  91. strmux_cfg.dma7 = regk_strmux_eth1;
  92. else
  93. panic("Invalid DMA channel for eth1\n");
  94. break;
  95. case dma_iop0:
  96. if (dmanr == 2)
  97. strmux_cfg.dma2 = regk_strmux_iop0;
  98. else if (dmanr == 3)
  99. strmux_cfg.dma3 = regk_strmux_iop0;
  100. else
  101. panic("Invalid DMA channel for iop0\n");
  102. break;
  103. case dma_iop1:
  104. if (dmanr == 4)
  105. strmux_cfg.dma4 = regk_strmux_iop1;
  106. else if (dmanr == 5)
  107. strmux_cfg.dma5 = regk_strmux_iop1;
  108. else
  109. panic("Invalid DMA channel for iop1\n");
  110. break;
  111. case dma_ser0:
  112. if (dmanr == 6)
  113. strmux_cfg.dma6 = regk_strmux_ser0;
  114. else if (dmanr == 7)
  115. strmux_cfg.dma7 = regk_strmux_ser0;
  116. else
  117. panic("Invalid DMA channel for ser0\n");
  118. break;
  119. case dma_ser1:
  120. if (dmanr == 4)
  121. strmux_cfg.dma4 = regk_strmux_ser1;
  122. else if (dmanr == 5)
  123. strmux_cfg.dma5 = regk_strmux_ser1;
  124. else
  125. panic("Invalid DMA channel for ser1\n");
  126. break;
  127. case dma_ser2:
  128. if (dmanr == 2)
  129. strmux_cfg.dma2 = regk_strmux_ser2;
  130. else if (dmanr == 3)
  131. strmux_cfg.dma3 = regk_strmux_ser2;
  132. else
  133. panic("Invalid DMA channel for ser2\n");
  134. break;
  135. case dma_ser3:
  136. if (dmanr == 8)
  137. strmux_cfg.dma8 = regk_strmux_ser3;
  138. else if (dmanr == 9)
  139. strmux_cfg.dma9 = regk_strmux_ser3;
  140. else
  141. panic("Invalid DMA channel for ser3\n");
  142. break;
  143. case dma_sser0:
  144. if (dmanr == 4)
  145. strmux_cfg.dma4 = regk_strmux_sser0;
  146. else if (dmanr == 5)
  147. strmux_cfg.dma5 = regk_strmux_sser0;
  148. else
  149. panic("Invalid DMA channel for sser0\n");
  150. break;
  151. case dma_sser1:
  152. if (dmanr == 6)
  153. strmux_cfg.dma6 = regk_strmux_sser1;
  154. else if (dmanr == 7)
  155. strmux_cfg.dma7 = regk_strmux_sser1;
  156. else
  157. panic("Invalid DMA channel for sser1\n");
  158. break;
  159. case dma_ata:
  160. if (dmanr == 2)
  161. strmux_cfg.dma2 = regk_strmux_ata;
  162. else if (dmanr == 3)
  163. strmux_cfg.dma3 = regk_strmux_ata;
  164. else
  165. panic("Invalid DMA channel for ata\n");
  166. break;
  167. case dma_strp:
  168. if (dmanr == 8)
  169. strmux_cfg.dma8 = regk_strmux_strcop;
  170. else if (dmanr == 9)
  171. strmux_cfg.dma9 = regk_strmux_strcop;
  172. else
  173. panic("Invalid DMA channel for strp\n");
  174. break;
  175. case dma_ext0:
  176. if (dmanr == 6)
  177. strmux_cfg.dma6 = regk_strmux_ext0;
  178. else
  179. panic("Invalid DMA channel for ext0\n");
  180. break;
  181. case dma_ext1:
  182. if (dmanr == 7)
  183. strmux_cfg.dma7 = regk_strmux_ext1;
  184. else
  185. panic("Invalid DMA channel for ext1\n");
  186. break;
  187. case dma_ext2:
  188. if (dmanr == 2)
  189. strmux_cfg.dma2 = regk_strmux_ext2;
  190. else if (dmanr == 8)
  191. strmux_cfg.dma8 = regk_strmux_ext2;
  192. else
  193. panic("Invalid DMA channel for ext2\n");
  194. break;
  195. case dma_ext3:
  196. if (dmanr == 3)
  197. strmux_cfg.dma3 = regk_strmux_ext3;
  198. else if (dmanr == 9)
  199. strmux_cfg.dma9 = regk_strmux_ext2;
  200. else
  201. panic("Invalid DMA channel for ext2\n");
  202. break;
  203. }
  204. used_dma_channels[dmanr] = 1;
  205. used_dma_channels_users[dmanr] = device_id;
  206. REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
  207. REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
  208. spin_unlock_irqrestore(&dma_lock, flags);
  209. return 0;
  210. }
  211. void crisv32_free_dma(unsigned int dmanr)
  212. {
  213. spin_lock(&dma_lock);
  214. used_dma_channels[dmanr] = 0;
  215. spin_unlock(&dma_lock);
  216. }