txx9aclc.c 12 KB

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  1. /*
  2. * Generic TXx9 ACLC platform driver
  3. *
  4. * Copyright (C) 2009 Atsushi Nemoto
  5. *
  6. * Based on RBTX49xx patch from CELF patch archive.
  7. * (C) Copyright TOSHIBA CORPORATION 2004-2006
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/init.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/scatterlist.h>
  17. #include <linux/slab.h>
  18. #include <linux/dmaengine.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/soc.h>
  23. #include "txx9aclc.h"
  24. static struct txx9aclc_soc_device {
  25. struct txx9aclc_dmadata dmadata[2];
  26. } txx9aclc_soc_device;
  27. /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
  28. static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
  29. static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
  30. struct txx9aclc_dmadata *dmadata);
  31. static const struct snd_pcm_hardware txx9aclc_pcm_hardware = {
  32. /*
  33. * REVISIT: SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID
  34. * needs more works for noncoherent MIPS.
  35. */
  36. .info = SNDRV_PCM_INFO_INTERLEAVED |
  37. SNDRV_PCM_INFO_BATCH |
  38. SNDRV_PCM_INFO_PAUSE,
  39. .period_bytes_min = 1024,
  40. .period_bytes_max = 8 * 1024,
  41. .periods_min = 2,
  42. .periods_max = 4096,
  43. .buffer_bytes_max = 32 * 1024,
  44. };
  45. static int txx9aclc_pcm_hw_params(struct snd_pcm_substream *substream,
  46. struct snd_pcm_hw_params *params)
  47. {
  48. struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
  49. struct snd_pcm_runtime *runtime = substream->runtime;
  50. struct txx9aclc_dmadata *dmadata = runtime->private_data;
  51. int ret;
  52. ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  53. if (ret < 0)
  54. return ret;
  55. dev_dbg(rtd->platform->dev,
  56. "runtime->dma_area = %#lx dma_addr = %#lx dma_bytes = %zd "
  57. "runtime->min_align %ld\n",
  58. (unsigned long)runtime->dma_area,
  59. (unsigned long)runtime->dma_addr, runtime->dma_bytes,
  60. runtime->min_align);
  61. dev_dbg(rtd->platform->dev,
  62. "periods %d period_bytes %d stream %d\n",
  63. params_periods(params), params_period_bytes(params),
  64. substream->stream);
  65. dmadata->substream = substream;
  66. dmadata->pos = 0;
  67. return 0;
  68. }
  69. static int txx9aclc_pcm_hw_free(struct snd_pcm_substream *substream)
  70. {
  71. return snd_pcm_lib_free_pages(substream);
  72. }
  73. static int txx9aclc_pcm_prepare(struct snd_pcm_substream *substream)
  74. {
  75. struct snd_pcm_runtime *runtime = substream->runtime;
  76. struct txx9aclc_dmadata *dmadata = runtime->private_data;
  77. dmadata->dma_addr = runtime->dma_addr;
  78. dmadata->buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
  79. dmadata->period_bytes = snd_pcm_lib_period_bytes(substream);
  80. if (dmadata->buffer_bytes == dmadata->period_bytes) {
  81. dmadata->frag_bytes = dmadata->period_bytes >> 1;
  82. dmadata->frags = 2;
  83. } else {
  84. dmadata->frag_bytes = dmadata->period_bytes;
  85. dmadata->frags = dmadata->buffer_bytes / dmadata->period_bytes;
  86. }
  87. dmadata->frag_count = 0;
  88. dmadata->pos = 0;
  89. return 0;
  90. }
  91. static void txx9aclc_dma_complete(void *arg)
  92. {
  93. struct txx9aclc_dmadata *dmadata = arg;
  94. unsigned long flags;
  95. /* dma completion handler cannot submit new operations */
  96. spin_lock_irqsave(&dmadata->dma_lock, flags);
  97. if (dmadata->frag_count >= 0) {
  98. dmadata->dmacount--;
  99. if (!WARN_ON(dmadata->dmacount < 0))
  100. tasklet_schedule(&dmadata->tasklet);
  101. }
  102. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  103. }
  104. static struct dma_async_tx_descriptor *
  105. txx9aclc_dma_submit(struct txx9aclc_dmadata *dmadata, dma_addr_t buf_dma_addr)
  106. {
  107. struct dma_chan *chan = dmadata->dma_chan;
  108. struct dma_async_tx_descriptor *desc;
  109. struct scatterlist sg;
  110. sg_init_table(&sg, 1);
  111. sg_set_page(&sg, pfn_to_page(PFN_DOWN(buf_dma_addr)),
  112. dmadata->frag_bytes, buf_dma_addr & (PAGE_SIZE - 1));
  113. sg_dma_address(&sg) = buf_dma_addr;
  114. desc = dmaengine_prep_slave_sg(chan, &sg, 1,
  115. dmadata->substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
  116. DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
  117. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  118. if (!desc) {
  119. dev_err(&chan->dev->device, "cannot prepare slave dma\n");
  120. return NULL;
  121. }
  122. desc->callback = txx9aclc_dma_complete;
  123. desc->callback_param = dmadata;
  124. dmaengine_submit(desc);
  125. return desc;
  126. }
  127. #define NR_DMA_CHAIN 2
  128. static void txx9aclc_dma_tasklet(unsigned long data)
  129. {
  130. struct txx9aclc_dmadata *dmadata = (struct txx9aclc_dmadata *)data;
  131. struct dma_chan *chan = dmadata->dma_chan;
  132. struct dma_async_tx_descriptor *desc;
  133. struct snd_pcm_substream *substream = dmadata->substream;
  134. u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
  135. ACCTL_AUDODMA : ACCTL_AUDIDMA;
  136. int i;
  137. unsigned long flags;
  138. spin_lock_irqsave(&dmadata->dma_lock, flags);
  139. if (dmadata->frag_count < 0) {
  140. struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
  141. void __iomem *base = drvdata->base;
  142. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  143. dmaengine_terminate_all(chan);
  144. /* first time */
  145. for (i = 0; i < NR_DMA_CHAIN; i++) {
  146. desc = txx9aclc_dma_submit(dmadata,
  147. dmadata->dma_addr + i * dmadata->frag_bytes);
  148. if (!desc)
  149. return;
  150. }
  151. dmadata->dmacount = NR_DMA_CHAIN;
  152. dma_async_issue_pending(chan);
  153. spin_lock_irqsave(&dmadata->dma_lock, flags);
  154. __raw_writel(ctlbit, base + ACCTLEN);
  155. dmadata->frag_count = NR_DMA_CHAIN % dmadata->frags;
  156. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  157. return;
  158. }
  159. if (WARN_ON(dmadata->dmacount >= NR_DMA_CHAIN)) {
  160. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  161. return;
  162. }
  163. while (dmadata->dmacount < NR_DMA_CHAIN) {
  164. dmadata->dmacount++;
  165. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  166. desc = txx9aclc_dma_submit(dmadata,
  167. dmadata->dma_addr +
  168. dmadata->frag_count * dmadata->frag_bytes);
  169. if (!desc)
  170. return;
  171. dma_async_issue_pending(chan);
  172. spin_lock_irqsave(&dmadata->dma_lock, flags);
  173. dmadata->frag_count++;
  174. dmadata->frag_count %= dmadata->frags;
  175. dmadata->pos += dmadata->frag_bytes;
  176. dmadata->pos %= dmadata->buffer_bytes;
  177. if ((dmadata->frag_count * dmadata->frag_bytes) %
  178. dmadata->period_bytes == 0)
  179. snd_pcm_period_elapsed(substream);
  180. }
  181. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  182. }
  183. static int txx9aclc_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  184. {
  185. struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
  186. struct txx9aclc_plat_drvdata *drvdata =txx9aclc_drvdata;
  187. void __iomem *base = drvdata->base;
  188. unsigned long flags;
  189. int ret = 0;
  190. u32 ctlbit = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
  191. ACCTL_AUDODMA : ACCTL_AUDIDMA;
  192. spin_lock_irqsave(&dmadata->dma_lock, flags);
  193. switch (cmd) {
  194. case SNDRV_PCM_TRIGGER_START:
  195. dmadata->frag_count = -1;
  196. tasklet_schedule(&dmadata->tasklet);
  197. break;
  198. case SNDRV_PCM_TRIGGER_STOP:
  199. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  200. case SNDRV_PCM_TRIGGER_SUSPEND:
  201. __raw_writel(ctlbit, base + ACCTLDIS);
  202. break;
  203. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  204. case SNDRV_PCM_TRIGGER_RESUME:
  205. __raw_writel(ctlbit, base + ACCTLEN);
  206. break;
  207. default:
  208. ret = -EINVAL;
  209. }
  210. spin_unlock_irqrestore(&dmadata->dma_lock, flags);
  211. return ret;
  212. }
  213. static snd_pcm_uframes_t
  214. txx9aclc_pcm_pointer(struct snd_pcm_substream *substream)
  215. {
  216. struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
  217. return bytes_to_frames(substream->runtime, dmadata->pos);
  218. }
  219. static int txx9aclc_pcm_open(struct snd_pcm_substream *substream)
  220. {
  221. struct txx9aclc_soc_device *dev = &txx9aclc_soc_device;
  222. struct txx9aclc_dmadata *dmadata = &dev->dmadata[substream->stream];
  223. int ret;
  224. ret = snd_soc_set_runtime_hwparams(substream, &txx9aclc_pcm_hardware);
  225. if (ret)
  226. return ret;
  227. /* ensure that buffer size is a multiple of period size */
  228. ret = snd_pcm_hw_constraint_integer(substream->runtime,
  229. SNDRV_PCM_HW_PARAM_PERIODS);
  230. if (ret < 0)
  231. return ret;
  232. substream->runtime->private_data = dmadata;
  233. return 0;
  234. }
  235. static int txx9aclc_pcm_close(struct snd_pcm_substream *substream)
  236. {
  237. struct txx9aclc_dmadata *dmadata = substream->runtime->private_data;
  238. struct dma_chan *chan = dmadata->dma_chan;
  239. dmadata->frag_count = -1;
  240. dmaengine_terminate_all(chan);
  241. return 0;
  242. }
  243. static struct snd_pcm_ops txx9aclc_pcm_ops = {
  244. .open = txx9aclc_pcm_open,
  245. .close = txx9aclc_pcm_close,
  246. .ioctl = snd_pcm_lib_ioctl,
  247. .hw_params = txx9aclc_pcm_hw_params,
  248. .hw_free = txx9aclc_pcm_hw_free,
  249. .prepare = txx9aclc_pcm_prepare,
  250. .trigger = txx9aclc_pcm_trigger,
  251. .pointer = txx9aclc_pcm_pointer,
  252. };
  253. static int txx9aclc_pcm_new(struct snd_soc_pcm_runtime *rtd)
  254. {
  255. struct snd_card *card = rtd->card->snd_card;
  256. struct snd_soc_dai *dai = rtd->cpu_dai;
  257. struct snd_pcm *pcm = rtd->pcm;
  258. struct platform_device *pdev = to_platform_device(rtd->platform->dev);
  259. struct txx9aclc_soc_device *dev;
  260. struct resource *r;
  261. int i;
  262. int ret;
  263. /* at this point onwards the AC97 component has probed and this will be valid */
  264. dev = snd_soc_dai_get_drvdata(dai);
  265. dev->dmadata[0].stream = SNDRV_PCM_STREAM_PLAYBACK;
  266. dev->dmadata[1].stream = SNDRV_PCM_STREAM_CAPTURE;
  267. for (i = 0; i < 2; i++) {
  268. r = platform_get_resource(pdev, IORESOURCE_DMA, i);
  269. if (!r) {
  270. ret = -EBUSY;
  271. goto exit;
  272. }
  273. dev->dmadata[i].dma_res = r;
  274. ret = txx9aclc_dma_init(dev, &dev->dmadata[i]);
  275. if (ret)
  276. goto exit;
  277. }
  278. return snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  279. card->dev, 64 * 1024, 4 * 1024 * 1024);
  280. exit:
  281. for (i = 0; i < 2; i++) {
  282. if (dev->dmadata[i].dma_chan)
  283. dma_release_channel(dev->dmadata[i].dma_chan);
  284. dev->dmadata[i].dma_chan = NULL;
  285. }
  286. return ret;
  287. }
  288. static bool filter(struct dma_chan *chan, void *param)
  289. {
  290. struct txx9aclc_dmadata *dmadata = param;
  291. char *devname;
  292. bool found = false;
  293. devname = kasprintf(GFP_KERNEL, "%s.%d", dmadata->dma_res->name,
  294. (int)dmadata->dma_res->start);
  295. if (strcmp(dev_name(chan->device->dev), devname) == 0) {
  296. chan->private = &dmadata->dma_slave;
  297. found = true;
  298. }
  299. kfree(devname);
  300. return found;
  301. }
  302. static int txx9aclc_dma_init(struct txx9aclc_soc_device *dev,
  303. struct txx9aclc_dmadata *dmadata)
  304. {
  305. struct txx9aclc_plat_drvdata *drvdata =txx9aclc_drvdata;
  306. struct txx9dmac_slave *ds = &dmadata->dma_slave;
  307. dma_cap_mask_t mask;
  308. spin_lock_init(&dmadata->dma_lock);
  309. ds->reg_width = sizeof(u32);
  310. if (dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  311. ds->tx_reg = drvdata->physbase + ACAUDODAT;
  312. ds->rx_reg = 0;
  313. } else {
  314. ds->tx_reg = 0;
  315. ds->rx_reg = drvdata->physbase + ACAUDIDAT;
  316. }
  317. /* Try to grab a DMA channel */
  318. dma_cap_zero(mask);
  319. dma_cap_set(DMA_SLAVE, mask);
  320. dmadata->dma_chan = dma_request_channel(mask, filter, dmadata);
  321. if (!dmadata->dma_chan) {
  322. printk(KERN_ERR
  323. "DMA channel for %s is not available\n",
  324. dmadata->stream == SNDRV_PCM_STREAM_PLAYBACK ?
  325. "playback" : "capture");
  326. return -EBUSY;
  327. }
  328. tasklet_init(&dmadata->tasklet, txx9aclc_dma_tasklet,
  329. (unsigned long)dmadata);
  330. return 0;
  331. }
  332. static int txx9aclc_pcm_probe(struct snd_soc_platform *platform)
  333. {
  334. snd_soc_platform_set_drvdata(platform, &txx9aclc_soc_device);
  335. return 0;
  336. }
  337. static int txx9aclc_pcm_remove(struct snd_soc_platform *platform)
  338. {
  339. struct txx9aclc_soc_device *dev = snd_soc_platform_get_drvdata(platform);
  340. struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
  341. void __iomem *base = drvdata->base;
  342. int i;
  343. /* disable all FIFO DMAs */
  344. __raw_writel(ACCTL_AUDODMA | ACCTL_AUDIDMA, base + ACCTLDIS);
  345. /* dummy R/W to clear pending DMAREQ if any */
  346. __raw_writel(__raw_readl(base + ACAUDIDAT), base + ACAUDODAT);
  347. for (i = 0; i < 2; i++) {
  348. struct txx9aclc_dmadata *dmadata = &dev->dmadata[i];
  349. struct dma_chan *chan = dmadata->dma_chan;
  350. if (chan) {
  351. dmadata->frag_count = -1;
  352. dmaengine_terminate_all(chan);
  353. dma_release_channel(chan);
  354. }
  355. dev->dmadata[i].dma_chan = NULL;
  356. }
  357. return 0;
  358. }
  359. static struct snd_soc_platform_driver txx9aclc_soc_platform = {
  360. .probe = txx9aclc_pcm_probe,
  361. .remove = txx9aclc_pcm_remove,
  362. .ops = &txx9aclc_pcm_ops,
  363. .pcm_new = txx9aclc_pcm_new,
  364. };
  365. static int txx9aclc_soc_platform_probe(struct platform_device *pdev)
  366. {
  367. return devm_snd_soc_register_platform(&pdev->dev,
  368. &txx9aclc_soc_platform);
  369. }
  370. static struct platform_driver txx9aclc_pcm_driver = {
  371. .driver = {
  372. .name = "txx9aclc-pcm-audio",
  373. },
  374. .probe = txx9aclc_soc_platform_probe,
  375. };
  376. module_platform_driver(txx9aclc_pcm_driver);
  377. MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
  378. MODULE_DESCRIPTION("TXx9 ACLC Audio DMA driver");
  379. MODULE_LICENSE("GPL");