txx9aclc-ac97.c 6.2 KB

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  1. /*
  2. * TXx9 ACLC AC97 driver
  3. *
  4. * Copyright (C) 2009 Atsushi Nemoto
  5. *
  6. * Based on RBTX49xx patch from CELF patch archive.
  7. * (C) Copyright TOSHIBA CORPORATION 2004-2006
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/delay.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/gfp.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/soc.h>
  22. #include "txx9aclc.h"
  23. #define AC97_DIR \
  24. (SND_SOC_DAIDIR_PLAYBACK | SND_SOC_DAIDIR_CAPTURE)
  25. #define AC97_RATES \
  26. SNDRV_PCM_RATE_8000_48000
  27. #ifdef __BIG_ENDIAN
  28. #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_BE
  29. #else
  30. #define AC97_FMTS SNDRV_PCM_FMTBIT_S16_LE
  31. #endif
  32. static DECLARE_WAIT_QUEUE_HEAD(ac97_waitq);
  33. /* REVISIT: How to find txx9aclc_drvdata from snd_ac97? */
  34. static struct txx9aclc_plat_drvdata *txx9aclc_drvdata;
  35. static int txx9aclc_regready(struct txx9aclc_plat_drvdata *drvdata)
  36. {
  37. return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY;
  38. }
  39. /* AC97 controller reads codec register */
  40. static unsigned short txx9aclc_ac97_read(struct snd_ac97 *ac97,
  41. unsigned short reg)
  42. {
  43. struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
  44. void __iomem *base = drvdata->base;
  45. u32 dat;
  46. if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num)))
  47. return 0xffff;
  48. reg |= ac97->num << 7;
  49. dat = (reg << ACREGACC_REG_SHIFT) | ACREGACC_READ;
  50. __raw_writel(dat, base + ACREGACC);
  51. __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
  52. if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
  53. __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
  54. printk(KERN_ERR "ac97 read timeout (reg %#x)\n", reg);
  55. dat = 0xffff;
  56. goto done;
  57. }
  58. dat = __raw_readl(base + ACREGACC);
  59. if (((dat >> ACREGACC_REG_SHIFT) & 0xff) != reg) {
  60. printk(KERN_ERR "reg mismatch %x with %x\n",
  61. dat, reg);
  62. dat = 0xffff;
  63. goto done;
  64. }
  65. dat = (dat >> ACREGACC_DAT_SHIFT) & 0xffff;
  66. done:
  67. __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
  68. return dat;
  69. }
  70. /* AC97 controller writes to codec register */
  71. static void txx9aclc_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  72. unsigned short val)
  73. {
  74. struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
  75. void __iomem *base = drvdata->base;
  76. __raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) |
  77. (val << ACREGACC_DAT_SHIFT),
  78. base + ACREGACC);
  79. __raw_writel(ACINT_REGACCRDY, base + ACINTEN);
  80. if (!wait_event_timeout(ac97_waitq, txx9aclc_regready(txx9aclc_drvdata), HZ)) {
  81. printk(KERN_ERR
  82. "ac97 write timeout (reg %#x)\n", reg);
  83. }
  84. __raw_writel(ACINT_REGACCRDY, base + ACINTDIS);
  85. }
  86. static void txx9aclc_ac97_cold_reset(struct snd_ac97 *ac97)
  87. {
  88. struct txx9aclc_plat_drvdata *drvdata = txx9aclc_drvdata;
  89. void __iomem *base = drvdata->base;
  90. u32 ready = ACINT_CODECRDY(ac97->num) | ACINT_REGACCRDY;
  91. __raw_writel(ACCTL_ENLINK, base + ACCTLDIS);
  92. mmiowb();
  93. udelay(1);
  94. __raw_writel(ACCTL_ENLINK, base + ACCTLEN);
  95. /* wait for primary codec ready status */
  96. __raw_writel(ready, base + ACINTEN);
  97. if (!wait_event_timeout(ac97_waitq,
  98. (__raw_readl(base + ACINTSTS) & ready) == ready,
  99. HZ)) {
  100. dev_err(&ac97->dev, "primary codec is not ready "
  101. "(status %#x)\n",
  102. __raw_readl(base + ACINTSTS));
  103. }
  104. __raw_writel(ACINT_REGACCRDY, base + ACINTSTS);
  105. __raw_writel(ready, base + ACINTDIS);
  106. }
  107. /* AC97 controller operations */
  108. static struct snd_ac97_bus_ops txx9aclc_ac97_ops = {
  109. .read = txx9aclc_ac97_read,
  110. .write = txx9aclc_ac97_write,
  111. .reset = txx9aclc_ac97_cold_reset,
  112. };
  113. static irqreturn_t txx9aclc_ac97_irq(int irq, void *dev_id)
  114. {
  115. struct txx9aclc_plat_drvdata *drvdata = dev_id;
  116. void __iomem *base = drvdata->base;
  117. __raw_writel(__raw_readl(base + ACINTMSTS), base + ACINTDIS);
  118. wake_up(&ac97_waitq);
  119. return IRQ_HANDLED;
  120. }
  121. static int txx9aclc_ac97_probe(struct snd_soc_dai *dai)
  122. {
  123. txx9aclc_drvdata = snd_soc_dai_get_drvdata(dai);
  124. return 0;
  125. }
  126. static int txx9aclc_ac97_remove(struct snd_soc_dai *dai)
  127. {
  128. struct txx9aclc_plat_drvdata *drvdata = snd_soc_dai_get_drvdata(dai);
  129. /* disable AC-link */
  130. __raw_writel(ACCTL_ENLINK, drvdata->base + ACCTLDIS);
  131. txx9aclc_drvdata = NULL;
  132. return 0;
  133. }
  134. static struct snd_soc_dai_driver txx9aclc_ac97_dai = {
  135. .bus_control = true,
  136. .probe = txx9aclc_ac97_probe,
  137. .remove = txx9aclc_ac97_remove,
  138. .playback = {
  139. .rates = AC97_RATES,
  140. .formats = AC97_FMTS,
  141. .channels_min = 2,
  142. .channels_max = 2,
  143. },
  144. .capture = {
  145. .rates = AC97_RATES,
  146. .formats = AC97_FMTS,
  147. .channels_min = 2,
  148. .channels_max = 2,
  149. },
  150. };
  151. static const struct snd_soc_component_driver txx9aclc_ac97_component = {
  152. .name = "txx9aclc-ac97",
  153. };
  154. static int txx9aclc_ac97_dev_probe(struct platform_device *pdev)
  155. {
  156. struct txx9aclc_plat_drvdata *drvdata;
  157. struct resource *r;
  158. int err;
  159. int irq;
  160. irq = platform_get_irq(pdev, 0);
  161. if (irq < 0)
  162. return irq;
  163. drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
  164. if (!drvdata)
  165. return -ENOMEM;
  166. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  167. drvdata->base = devm_ioremap_resource(&pdev->dev, r);
  168. if (IS_ERR(drvdata->base))
  169. return PTR_ERR(drvdata->base);
  170. platform_set_drvdata(pdev, drvdata);
  171. drvdata->physbase = r->start;
  172. if (sizeof(drvdata->physbase) > sizeof(r->start) &&
  173. r->start >= TXX9_DIRECTMAP_BASE &&
  174. r->start < TXX9_DIRECTMAP_BASE + 0x400000)
  175. drvdata->physbase |= 0xf00000000ull;
  176. err = devm_request_irq(&pdev->dev, irq, txx9aclc_ac97_irq,
  177. 0, dev_name(&pdev->dev), drvdata);
  178. if (err < 0)
  179. return err;
  180. err = snd_soc_set_ac97_ops(&txx9aclc_ac97_ops);
  181. if (err < 0)
  182. return err;
  183. return snd_soc_register_component(&pdev->dev, &txx9aclc_ac97_component,
  184. &txx9aclc_ac97_dai, 1);
  185. }
  186. static int txx9aclc_ac97_dev_remove(struct platform_device *pdev)
  187. {
  188. snd_soc_unregister_component(&pdev->dev);
  189. snd_soc_set_ac97_ops(NULL);
  190. return 0;
  191. }
  192. static struct platform_driver txx9aclc_ac97_driver = {
  193. .probe = txx9aclc_ac97_dev_probe,
  194. .remove = txx9aclc_ac97_dev_remove,
  195. .driver = {
  196. .name = "txx9aclc-ac97",
  197. },
  198. };
  199. module_platform_driver(txx9aclc_ac97_driver);
  200. MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
  201. MODULE_DESCRIPTION("TXx9 ACLC AC97 driver");
  202. MODULE_LICENSE("GPL");
  203. MODULE_ALIAS("platform:txx9aclc-ac97");