pxa2xx-i2s.c 9.9 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * lrg@slimlogic.co.uk
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/io.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/initval.h>
  23. #include <sound/soc.h>
  24. #include <sound/pxa2xx-lib.h>
  25. #include <sound/dmaengine_pcm.h>
  26. #include <mach/hardware.h>
  27. #include <mach/audio.h>
  28. #include "pxa2xx-i2s.h"
  29. /*
  30. * I2S Controller Register and Bit Definitions
  31. */
  32. #define SACR0 __REG(0x40400000) /* Global Control Register */
  33. #define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */
  34. #define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
  35. #define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */
  36. #define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */
  37. #define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */
  38. #define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */
  39. #define SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */
  40. #define SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */
  41. #define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
  42. #define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
  43. #define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
  44. #define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
  45. #define SACR0_ENB (1 << 0) /* Enable I2S Link */
  46. #define SACR1_ENLBF (1 << 5) /* Enable Loopback */
  47. #define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
  48. #define SACR1_DREC (1 << 3) /* Disable Recording Function */
  49. #define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
  50. #define SASR0_I2SOFF (1 << 7) /* Controller Status */
  51. #define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */
  52. #define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */
  53. #define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */
  54. #define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
  55. #define SASR0_BSY (1 << 2) /* I2S Busy */
  56. #define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
  57. #define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
  58. #define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
  59. #define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
  60. #define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */
  61. #define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */
  62. #define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */
  63. #define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */
  64. struct pxa_i2s_port {
  65. u32 sadiv;
  66. u32 sacr0;
  67. u32 sacr1;
  68. u32 saimr;
  69. int master;
  70. u32 fmt;
  71. };
  72. static struct pxa_i2s_port pxa_i2s;
  73. static struct clk *clk_i2s;
  74. static int clk_ena = 0;
  75. static unsigned long pxa2xx_i2s_pcm_stereo_out_req = 3;
  76. static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_out = {
  77. .addr = __PREG(SADR),
  78. .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  79. .maxburst = 32,
  80. .filter_data = &pxa2xx_i2s_pcm_stereo_out_req,
  81. };
  82. static unsigned long pxa2xx_i2s_pcm_stereo_in_req = 2;
  83. static struct snd_dmaengine_dai_dma_data pxa2xx_i2s_pcm_stereo_in = {
  84. .addr = __PREG(SADR),
  85. .addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
  86. .maxburst = 32,
  87. .filter_data = &pxa2xx_i2s_pcm_stereo_in_req,
  88. };
  89. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream,
  90. struct snd_soc_dai *dai)
  91. {
  92. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  93. struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  94. if (IS_ERR(clk_i2s))
  95. return PTR_ERR(clk_i2s);
  96. if (!cpu_dai->active)
  97. SACR0 = 0;
  98. return 0;
  99. }
  100. /* wait for I2S controller to be ready */
  101. static int pxa_i2s_wait(void)
  102. {
  103. int i;
  104. /* flush the Rx FIFO */
  105. for(i = 0; i < 16; i++)
  106. SADR;
  107. return 0;
  108. }
  109. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  110. unsigned int fmt)
  111. {
  112. /* interface format */
  113. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  114. case SND_SOC_DAIFMT_I2S:
  115. pxa_i2s.fmt = 0;
  116. break;
  117. case SND_SOC_DAIFMT_LEFT_J:
  118. pxa_i2s.fmt = SACR1_AMSL;
  119. break;
  120. }
  121. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  122. case SND_SOC_DAIFMT_CBS_CFS:
  123. pxa_i2s.master = 1;
  124. break;
  125. case SND_SOC_DAIFMT_CBM_CFS:
  126. pxa_i2s.master = 0;
  127. break;
  128. default:
  129. break;
  130. }
  131. return 0;
  132. }
  133. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  134. int clk_id, unsigned int freq, int dir)
  135. {
  136. if (clk_id != PXA2XX_I2S_SYSCLK)
  137. return -ENODEV;
  138. return 0;
  139. }
  140. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  141. struct snd_pcm_hw_params *params,
  142. struct snd_soc_dai *dai)
  143. {
  144. struct snd_dmaengine_dai_dma_data *dma_data;
  145. if (WARN_ON(IS_ERR(clk_i2s)))
  146. return -EINVAL;
  147. clk_prepare_enable(clk_i2s);
  148. clk_ena = 1;
  149. pxa_i2s_wait();
  150. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  151. dma_data = &pxa2xx_i2s_pcm_stereo_out;
  152. else
  153. dma_data = &pxa2xx_i2s_pcm_stereo_in;
  154. snd_soc_dai_set_dma_data(dai, substream, dma_data);
  155. /* is port used by another stream */
  156. if (!(SACR0 & SACR0_ENB)) {
  157. SACR0 = 0;
  158. if (pxa_i2s.master)
  159. SACR0 |= SACR0_BCKD;
  160. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  161. SACR1 |= pxa_i2s.fmt;
  162. }
  163. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  164. SAIMR |= SAIMR_TFS;
  165. else
  166. SAIMR |= SAIMR_RFS;
  167. switch (params_rate(params)) {
  168. case 8000:
  169. SADIV = 0x48;
  170. break;
  171. case 11025:
  172. SADIV = 0x34;
  173. break;
  174. case 16000:
  175. SADIV = 0x24;
  176. break;
  177. case 22050:
  178. SADIV = 0x1a;
  179. break;
  180. case 44100:
  181. SADIV = 0xd;
  182. break;
  183. case 48000:
  184. SADIV = 0xc;
  185. break;
  186. case 96000: /* not in manual and possibly slightly inaccurate */
  187. SADIV = 0x6;
  188. break;
  189. }
  190. return 0;
  191. }
  192. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
  193. struct snd_soc_dai *dai)
  194. {
  195. int ret = 0;
  196. switch (cmd) {
  197. case SNDRV_PCM_TRIGGER_START:
  198. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  199. SACR1 &= ~SACR1_DRPL;
  200. else
  201. SACR1 &= ~SACR1_DREC;
  202. SACR0 |= SACR0_ENB;
  203. break;
  204. case SNDRV_PCM_TRIGGER_RESUME:
  205. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  206. case SNDRV_PCM_TRIGGER_STOP:
  207. case SNDRV_PCM_TRIGGER_SUSPEND:
  208. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  209. break;
  210. default:
  211. ret = -EINVAL;
  212. }
  213. return ret;
  214. }
  215. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream,
  216. struct snd_soc_dai *dai)
  217. {
  218. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  219. SACR1 |= SACR1_DRPL;
  220. SAIMR &= ~SAIMR_TFS;
  221. } else {
  222. SACR1 |= SACR1_DREC;
  223. SAIMR &= ~SAIMR_RFS;
  224. }
  225. if ((SACR1 & (SACR1_DREC | SACR1_DRPL)) == (SACR1_DREC | SACR1_DRPL)) {
  226. SACR0 &= ~SACR0_ENB;
  227. pxa_i2s_wait();
  228. if (clk_ena) {
  229. clk_disable_unprepare(clk_i2s);
  230. clk_ena = 0;
  231. }
  232. }
  233. }
  234. #ifdef CONFIG_PM
  235. static int pxa2xx_i2s_suspend(struct snd_soc_dai *dai)
  236. {
  237. /* store registers */
  238. pxa_i2s.sacr0 = SACR0;
  239. pxa_i2s.sacr1 = SACR1;
  240. pxa_i2s.saimr = SAIMR;
  241. pxa_i2s.sadiv = SADIV;
  242. /* deactivate link */
  243. SACR0 &= ~SACR0_ENB;
  244. pxa_i2s_wait();
  245. return 0;
  246. }
  247. static int pxa2xx_i2s_resume(struct snd_soc_dai *dai)
  248. {
  249. pxa_i2s_wait();
  250. SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
  251. SACR1 = pxa_i2s.sacr1;
  252. SAIMR = pxa_i2s.saimr;
  253. SADIV = pxa_i2s.sadiv;
  254. SACR0 = pxa_i2s.sacr0;
  255. return 0;
  256. }
  257. #else
  258. #define pxa2xx_i2s_suspend NULL
  259. #define pxa2xx_i2s_resume NULL
  260. #endif
  261. static int pxa2xx_i2s_probe(struct snd_soc_dai *dai)
  262. {
  263. clk_i2s = clk_get(dai->dev, "I2SCLK");
  264. if (IS_ERR(clk_i2s))
  265. return PTR_ERR(clk_i2s);
  266. /*
  267. * PXA Developer's Manual:
  268. * If SACR0[ENB] is toggled in the middle of a normal operation,
  269. * the SACR0[RST] bit must also be set and cleared to reset all
  270. * I2S controller registers.
  271. */
  272. SACR0 = SACR0_RST;
  273. SACR0 = 0;
  274. /* Make sure RPL and REC are disabled */
  275. SACR1 = SACR1_DRPL | SACR1_DREC;
  276. /* Along with FIFO servicing */
  277. SAIMR &= ~(SAIMR_RFS | SAIMR_TFS);
  278. snd_soc_dai_init_dma_data(dai, &pxa2xx_i2s_pcm_stereo_out,
  279. &pxa2xx_i2s_pcm_stereo_in);
  280. return 0;
  281. }
  282. static int pxa2xx_i2s_remove(struct snd_soc_dai *dai)
  283. {
  284. clk_put(clk_i2s);
  285. clk_i2s = ERR_PTR(-ENOENT);
  286. return 0;
  287. }
  288. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  289. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  290. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  291. static const struct snd_soc_dai_ops pxa_i2s_dai_ops = {
  292. .startup = pxa2xx_i2s_startup,
  293. .shutdown = pxa2xx_i2s_shutdown,
  294. .trigger = pxa2xx_i2s_trigger,
  295. .hw_params = pxa2xx_i2s_hw_params,
  296. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  297. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  298. };
  299. static struct snd_soc_dai_driver pxa_i2s_dai = {
  300. .probe = pxa2xx_i2s_probe,
  301. .remove = pxa2xx_i2s_remove,
  302. .suspend = pxa2xx_i2s_suspend,
  303. .resume = pxa2xx_i2s_resume,
  304. .playback = {
  305. .channels_min = 2,
  306. .channels_max = 2,
  307. .rates = PXA2XX_I2S_RATES,
  308. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  309. .capture = {
  310. .channels_min = 2,
  311. .channels_max = 2,
  312. .rates = PXA2XX_I2S_RATES,
  313. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  314. .ops = &pxa_i2s_dai_ops,
  315. .symmetric_rates = 1,
  316. };
  317. static const struct snd_soc_component_driver pxa_i2s_component = {
  318. .name = "pxa-i2s",
  319. };
  320. static int pxa2xx_i2s_drv_probe(struct platform_device *pdev)
  321. {
  322. return devm_snd_soc_register_component(&pdev->dev, &pxa_i2s_component,
  323. &pxa_i2s_dai, 1);
  324. }
  325. static struct platform_driver pxa2xx_i2s_driver = {
  326. .probe = pxa2xx_i2s_drv_probe,
  327. .driver = {
  328. .name = "pxa2xx-i2s",
  329. },
  330. };
  331. static int __init pxa2xx_i2s_init(void)
  332. {
  333. clk_i2s = ERR_PTR(-ENOENT);
  334. return platform_driver_register(&pxa2xx_i2s_driver);
  335. }
  336. static void __exit pxa2xx_i2s_exit(void)
  337. {
  338. platform_driver_unregister(&pxa2xx_i2s_driver);
  339. }
  340. module_init(pxa2xx_i2s_init);
  341. module_exit(pxa2xx_i2s_exit);
  342. /* Module information */
  343. MODULE_AUTHOR("Liam Girdwood, lrg@slimlogic.co.uk");
  344. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  345. MODULE_LICENSE("GPL");
  346. MODULE_ALIAS("platform:pxa2xx-i2s");