sst.c 14 KB

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  1. /*
  2. * sst.c - Intel SST Driver for audio engine
  3. *
  4. * Copyright (C) 2008-14 Intel Corp
  5. * Authors: Vinod Koul <vinod.koul@intel.com>
  6. * Harsha Priya <priya.harsha@intel.com>
  7. * Dharageswari R <dharageswari.r@intel.com>
  8. * KP Jeeja <jeeja.kp@intel.com>
  9. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; version 2 of the License.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  21. */
  22. #include <linux/module.h>
  23. #include <linux/fs.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/firmware.h>
  26. #include <linux/pm_runtime.h>
  27. #include <linux/pm_qos.h>
  28. #include <linux/async.h>
  29. #include <linux/acpi.h>
  30. #include <sound/core.h>
  31. #include <sound/soc.h>
  32. #include <asm/platform_sst_audio.h>
  33. #include "../sst-mfld-platform.h"
  34. #include "sst.h"
  35. #include "../../common/sst-dsp.h"
  36. MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
  37. MODULE_AUTHOR("Harsha Priya <priya.harsha@intel.com>");
  38. MODULE_DESCRIPTION("Intel (R) SST(R) Audio Engine Driver");
  39. MODULE_LICENSE("GPL v2");
  40. static inline bool sst_is_process_reply(u32 msg_id)
  41. {
  42. return ((msg_id & PROCESS_MSG) ? true : false);
  43. }
  44. static inline bool sst_validate_mailbox_size(unsigned int size)
  45. {
  46. return ((size <= SST_MAILBOX_SIZE) ? true : false);
  47. }
  48. static irqreturn_t intel_sst_interrupt_mrfld(int irq, void *context)
  49. {
  50. union interrupt_reg_mrfld isr;
  51. union ipc_header_mrfld header;
  52. union sst_imr_reg_mrfld imr;
  53. struct ipc_post *msg = NULL;
  54. unsigned int size = 0;
  55. struct intel_sst_drv *drv = (struct intel_sst_drv *) context;
  56. irqreturn_t retval = IRQ_HANDLED;
  57. /* Interrupt arrived, check src */
  58. isr.full = sst_shim_read64(drv->shim, SST_ISRX);
  59. if (isr.part.done_interrupt) {
  60. /* Clear done bit */
  61. spin_lock(&drv->ipc_spin_lock);
  62. header.full = sst_shim_read64(drv->shim,
  63. drv->ipc_reg.ipcx);
  64. header.p.header_high.part.done = 0;
  65. sst_shim_write64(drv->shim, drv->ipc_reg.ipcx, header.full);
  66. /* write 1 to clear status register */;
  67. isr.part.done_interrupt = 1;
  68. sst_shim_write64(drv->shim, SST_ISRX, isr.full);
  69. spin_unlock(&drv->ipc_spin_lock);
  70. /* we can send more messages to DSP so trigger work */
  71. queue_work(drv->post_msg_wq, &drv->ipc_post_msg_wq);
  72. retval = IRQ_HANDLED;
  73. }
  74. if (isr.part.busy_interrupt) {
  75. /* message from dsp so copy that */
  76. spin_lock(&drv->ipc_spin_lock);
  77. imr.full = sst_shim_read64(drv->shim, SST_IMRX);
  78. imr.part.busy_interrupt = 1;
  79. sst_shim_write64(drv->shim, SST_IMRX, imr.full);
  80. spin_unlock(&drv->ipc_spin_lock);
  81. header.full = sst_shim_read64(drv->shim, drv->ipc_reg.ipcd);
  82. if (sst_create_ipc_msg(&msg, header.p.header_high.part.large)) {
  83. drv->ops->clear_interrupt(drv);
  84. return IRQ_HANDLED;
  85. }
  86. if (header.p.header_high.part.large) {
  87. size = header.p.header_low_payload;
  88. if (sst_validate_mailbox_size(size)) {
  89. memcpy_fromio(msg->mailbox_data,
  90. drv->mailbox + drv->mailbox_recv_offset, size);
  91. } else {
  92. dev_err(drv->dev,
  93. "Mailbox not copied, payload size is: %u\n", size);
  94. header.p.header_low_payload = 0;
  95. }
  96. }
  97. msg->mrfld_header = header;
  98. msg->is_process_reply =
  99. sst_is_process_reply(header.p.header_high.part.msg_id);
  100. spin_lock(&drv->rx_msg_lock);
  101. list_add_tail(&msg->node, &drv->rx_list);
  102. spin_unlock(&drv->rx_msg_lock);
  103. drv->ops->clear_interrupt(drv);
  104. retval = IRQ_WAKE_THREAD;
  105. }
  106. return retval;
  107. }
  108. static irqreturn_t intel_sst_irq_thread_mrfld(int irq, void *context)
  109. {
  110. struct intel_sst_drv *drv = (struct intel_sst_drv *) context;
  111. struct ipc_post *__msg, *msg = NULL;
  112. unsigned long irq_flags;
  113. spin_lock_irqsave(&drv->rx_msg_lock, irq_flags);
  114. if (list_empty(&drv->rx_list)) {
  115. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  116. return IRQ_HANDLED;
  117. }
  118. list_for_each_entry_safe(msg, __msg, &drv->rx_list, node) {
  119. list_del(&msg->node);
  120. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  121. if (msg->is_process_reply)
  122. drv->ops->process_message(msg);
  123. else
  124. drv->ops->process_reply(drv, msg);
  125. if (msg->is_large)
  126. kfree(msg->mailbox_data);
  127. kfree(msg);
  128. spin_lock_irqsave(&drv->rx_msg_lock, irq_flags);
  129. }
  130. spin_unlock_irqrestore(&drv->rx_msg_lock, irq_flags);
  131. return IRQ_HANDLED;
  132. }
  133. static int sst_save_dsp_context_v2(struct intel_sst_drv *sst)
  134. {
  135. int ret = 0;
  136. ret = sst_prepare_and_post_msg(sst, SST_TASK_ID_MEDIA, IPC_CMD,
  137. IPC_PREP_D3, PIPE_RSVD, 0, NULL, NULL,
  138. true, true, false, true);
  139. if (ret < 0) {
  140. dev_err(sst->dev, "not suspending FW!!, Err: %d\n", ret);
  141. return -EIO;
  142. }
  143. return 0;
  144. }
  145. static struct intel_sst_ops mrfld_ops = {
  146. .interrupt = intel_sst_interrupt_mrfld,
  147. .irq_thread = intel_sst_irq_thread_mrfld,
  148. .clear_interrupt = intel_sst_clear_intr_mrfld,
  149. .start = sst_start_mrfld,
  150. .reset = intel_sst_reset_dsp_mrfld,
  151. .post_message = sst_post_message_mrfld,
  152. .process_reply = sst_process_reply_mrfld,
  153. .save_dsp_context = sst_save_dsp_context_v2,
  154. .alloc_stream = sst_alloc_stream_mrfld,
  155. .post_download = sst_post_download_mrfld,
  156. };
  157. int sst_driver_ops(struct intel_sst_drv *sst)
  158. {
  159. switch (sst->dev_id) {
  160. case SST_MRFLD_PCI_ID:
  161. case SST_BYT_ACPI_ID:
  162. case SST_CHV_ACPI_ID:
  163. sst->tstamp = SST_TIME_STAMP_MRFLD;
  164. sst->ops = &mrfld_ops;
  165. return 0;
  166. default:
  167. dev_err(sst->dev,
  168. "SST Driver capabilities missing for dev_id: %x",
  169. sst->dev_id);
  170. return -EINVAL;
  171. };
  172. }
  173. void sst_process_pending_msg(struct work_struct *work)
  174. {
  175. struct intel_sst_drv *ctx = container_of(work,
  176. struct intel_sst_drv, ipc_post_msg_wq);
  177. ctx->ops->post_message(ctx, NULL, false);
  178. }
  179. static int sst_workqueue_init(struct intel_sst_drv *ctx)
  180. {
  181. INIT_LIST_HEAD(&ctx->memcpy_list);
  182. INIT_LIST_HEAD(&ctx->rx_list);
  183. INIT_LIST_HEAD(&ctx->ipc_dispatch_list);
  184. INIT_LIST_HEAD(&ctx->block_list);
  185. INIT_WORK(&ctx->ipc_post_msg_wq, sst_process_pending_msg);
  186. init_waitqueue_head(&ctx->wait_queue);
  187. ctx->post_msg_wq =
  188. create_singlethread_workqueue("sst_post_msg_wq");
  189. if (!ctx->post_msg_wq)
  190. return -EBUSY;
  191. return 0;
  192. }
  193. static void sst_init_locks(struct intel_sst_drv *ctx)
  194. {
  195. mutex_init(&ctx->sst_lock);
  196. spin_lock_init(&ctx->rx_msg_lock);
  197. spin_lock_init(&ctx->ipc_spin_lock);
  198. spin_lock_init(&ctx->block_lock);
  199. }
  200. int sst_alloc_drv_context(struct intel_sst_drv **ctx,
  201. struct device *dev, unsigned int dev_id)
  202. {
  203. *ctx = devm_kzalloc(dev, sizeof(struct intel_sst_drv), GFP_KERNEL);
  204. if (!(*ctx))
  205. return -ENOMEM;
  206. (*ctx)->dev = dev;
  207. (*ctx)->dev_id = dev_id;
  208. return 0;
  209. }
  210. EXPORT_SYMBOL_GPL(sst_alloc_drv_context);
  211. int sst_context_init(struct intel_sst_drv *ctx)
  212. {
  213. int ret = 0, i;
  214. if (!ctx->pdata)
  215. return -EINVAL;
  216. if (!ctx->pdata->probe_data)
  217. return -EINVAL;
  218. memcpy(&ctx->info, ctx->pdata->probe_data, sizeof(ctx->info));
  219. ret = sst_driver_ops(ctx);
  220. if (ret != 0)
  221. return -EINVAL;
  222. sst_init_locks(ctx);
  223. sst_set_fw_state_locked(ctx, SST_RESET);
  224. /* pvt_id 0 reserved for async messages */
  225. ctx->pvt_id = 1;
  226. ctx->stream_cnt = 0;
  227. ctx->fw_in_mem = NULL;
  228. /* we use memcpy, so set to 0 */
  229. ctx->use_dma = 0;
  230. ctx->use_lli = 0;
  231. if (sst_workqueue_init(ctx))
  232. return -EINVAL;
  233. ctx->mailbox_recv_offset = ctx->pdata->ipc_info->mbox_recv_off;
  234. ctx->ipc_reg.ipcx = SST_IPCX + ctx->pdata->ipc_info->ipc_offset;
  235. ctx->ipc_reg.ipcd = SST_IPCD + ctx->pdata->ipc_info->ipc_offset;
  236. dev_info(ctx->dev, "Got drv data max stream %d\n",
  237. ctx->info.max_streams);
  238. for (i = 1; i <= ctx->info.max_streams; i++) {
  239. struct stream_info *stream = &ctx->streams[i];
  240. memset(stream, 0, sizeof(*stream));
  241. stream->pipe_id = PIPE_RSVD;
  242. mutex_init(&stream->lock);
  243. }
  244. /* Register the ISR */
  245. ret = devm_request_threaded_irq(ctx->dev, ctx->irq_num, ctx->ops->interrupt,
  246. ctx->ops->irq_thread, 0, SST_DRV_NAME,
  247. ctx);
  248. if (ret)
  249. goto do_free_mem;
  250. dev_dbg(ctx->dev, "Registered IRQ %#x\n", ctx->irq_num);
  251. /* default intr are unmasked so set this as masked */
  252. sst_shim_write64(ctx->shim, SST_IMRX, 0xFFFF0038);
  253. ctx->qos = devm_kzalloc(ctx->dev,
  254. sizeof(struct pm_qos_request), GFP_KERNEL);
  255. if (!ctx->qos) {
  256. ret = -ENOMEM;
  257. goto do_free_mem;
  258. }
  259. pm_qos_add_request(ctx->qos, PM_QOS_CPU_DMA_LATENCY,
  260. PM_QOS_DEFAULT_VALUE);
  261. dev_dbg(ctx->dev, "Requesting FW %s now...\n", ctx->firmware_name);
  262. ret = reject_firmware_nowait(THIS_MODULE, true, ctx->firmware_name,
  263. ctx->dev, GFP_KERNEL, ctx, sst_firmware_load_cb);
  264. if (ret) {
  265. dev_err(ctx->dev, "Firmware download failed:%d\n", ret);
  266. goto do_free_mem;
  267. }
  268. sst_register(ctx->dev);
  269. return 0;
  270. do_free_mem:
  271. destroy_workqueue(ctx->post_msg_wq);
  272. return ret;
  273. }
  274. EXPORT_SYMBOL_GPL(sst_context_init);
  275. void sst_context_cleanup(struct intel_sst_drv *ctx)
  276. {
  277. pm_runtime_get_noresume(ctx->dev);
  278. pm_runtime_disable(ctx->dev);
  279. sst_unregister(ctx->dev);
  280. sst_set_fw_state_locked(ctx, SST_SHUTDOWN);
  281. flush_scheduled_work();
  282. destroy_workqueue(ctx->post_msg_wq);
  283. pm_qos_remove_request(ctx->qos);
  284. kfree(ctx->fw_sg_list.src);
  285. kfree(ctx->fw_sg_list.dst);
  286. ctx->fw_sg_list.list_len = 0;
  287. kfree(ctx->fw_in_mem);
  288. ctx->fw_in_mem = NULL;
  289. sst_memcpy_free_resources(ctx);
  290. ctx = NULL;
  291. }
  292. EXPORT_SYMBOL_GPL(sst_context_cleanup);
  293. static inline void sst_save_shim64(struct intel_sst_drv *ctx,
  294. void __iomem *shim,
  295. struct sst_shim_regs64 *shim_regs)
  296. {
  297. unsigned long irq_flags;
  298. spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags);
  299. shim_regs->imrx = sst_shim_read64(shim, SST_IMRX);
  300. shim_regs->csr = sst_shim_read64(shim, SST_CSR);
  301. spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags);
  302. }
  303. static inline void sst_restore_shim64(struct intel_sst_drv *ctx,
  304. void __iomem *shim,
  305. struct sst_shim_regs64 *shim_regs)
  306. {
  307. unsigned long irq_flags;
  308. /*
  309. * we only need to restore IMRX for this case, rest will be
  310. * initialize by FW or driver when firmware is loaded
  311. */
  312. spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags);
  313. sst_shim_write64(shim, SST_IMRX, shim_regs->imrx);
  314. sst_shim_write64(shim, SST_CSR, shim_regs->csr);
  315. spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags);
  316. }
  317. void sst_configure_runtime_pm(struct intel_sst_drv *ctx)
  318. {
  319. pm_runtime_set_autosuspend_delay(ctx->dev, SST_SUSPEND_DELAY);
  320. pm_runtime_use_autosuspend(ctx->dev);
  321. /*
  322. * For acpi devices, the actual physical device state is
  323. * initially active. So change the state to active before
  324. * enabling the pm
  325. */
  326. if (!acpi_disabled)
  327. pm_runtime_set_active(ctx->dev);
  328. pm_runtime_enable(ctx->dev);
  329. if (acpi_disabled)
  330. pm_runtime_set_active(ctx->dev);
  331. else
  332. pm_runtime_put_noidle(ctx->dev);
  333. sst_save_shim64(ctx, ctx->shim, ctx->shim_regs64);
  334. }
  335. EXPORT_SYMBOL_GPL(sst_configure_runtime_pm);
  336. static int intel_sst_runtime_suspend(struct device *dev)
  337. {
  338. int ret = 0;
  339. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  340. if (ctx->sst_state == SST_RESET) {
  341. dev_dbg(dev, "LPE is already in RESET state, No action\n");
  342. return 0;
  343. }
  344. /* save fw context */
  345. if (ctx->ops->save_dsp_context(ctx))
  346. return -EBUSY;
  347. /* Move the SST state to Reset */
  348. sst_set_fw_state_locked(ctx, SST_RESET);
  349. synchronize_irq(ctx->irq_num);
  350. flush_workqueue(ctx->post_msg_wq);
  351. ctx->ops->reset(ctx);
  352. /* save the shim registers because PMC doesn't save state */
  353. sst_save_shim64(ctx, ctx->shim, ctx->shim_regs64);
  354. return ret;
  355. }
  356. static int intel_sst_suspend(struct device *dev)
  357. {
  358. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  359. struct sst_fw_save *fw_save;
  360. int i, ret = 0;
  361. /* check first if we are already in SW reset */
  362. if (ctx->sst_state == SST_RESET)
  363. return 0;
  364. /*
  365. * check if any stream is active and running
  366. * they should already by suspend by soc_suspend
  367. */
  368. for (i = 1; i <= ctx->info.max_streams; i++) {
  369. struct stream_info *stream = &ctx->streams[i];
  370. if (stream->status == STREAM_RUNNING) {
  371. dev_err(dev, "stream %d is running, can't suspend, abort\n", i);
  372. return -EBUSY;
  373. }
  374. }
  375. synchronize_irq(ctx->irq_num);
  376. flush_workqueue(ctx->post_msg_wq);
  377. /* Move the SST state to Reset */
  378. sst_set_fw_state_locked(ctx, SST_RESET);
  379. /* tell DSP we are suspending */
  380. if (ctx->ops->save_dsp_context(ctx))
  381. return -EBUSY;
  382. /* save the memories */
  383. fw_save = kzalloc(sizeof(*fw_save), GFP_KERNEL);
  384. if (!fw_save)
  385. return -ENOMEM;
  386. fw_save->iram = kzalloc(ctx->iram_end - ctx->iram_base, GFP_KERNEL);
  387. if (!fw_save->iram) {
  388. ret = -ENOMEM;
  389. goto iram;
  390. }
  391. fw_save->dram = kzalloc(ctx->dram_end - ctx->dram_base, GFP_KERNEL);
  392. if (!fw_save->dram) {
  393. ret = -ENOMEM;
  394. goto dram;
  395. }
  396. fw_save->sram = kzalloc(SST_MAILBOX_SIZE, GFP_KERNEL);
  397. if (!fw_save->sram) {
  398. ret = -ENOMEM;
  399. goto sram;
  400. }
  401. fw_save->ddr = kzalloc(ctx->ddr_end - ctx->ddr_base, GFP_KERNEL);
  402. if (!fw_save->ddr) {
  403. ret = -ENOMEM;
  404. goto ddr;
  405. }
  406. memcpy32_fromio(fw_save->iram, ctx->iram, ctx->iram_end - ctx->iram_base);
  407. memcpy32_fromio(fw_save->dram, ctx->dram, ctx->dram_end - ctx->dram_base);
  408. memcpy32_fromio(fw_save->sram, ctx->mailbox, SST_MAILBOX_SIZE);
  409. memcpy32_fromio(fw_save->ddr, ctx->ddr, ctx->ddr_end - ctx->ddr_base);
  410. ctx->fw_save = fw_save;
  411. ctx->ops->reset(ctx);
  412. return 0;
  413. ddr:
  414. kfree(fw_save->sram);
  415. sram:
  416. kfree(fw_save->dram);
  417. dram:
  418. kfree(fw_save->iram);
  419. iram:
  420. kfree(fw_save);
  421. return ret;
  422. }
  423. static int intel_sst_resume(struct device *dev)
  424. {
  425. struct intel_sst_drv *ctx = dev_get_drvdata(dev);
  426. struct sst_fw_save *fw_save = ctx->fw_save;
  427. int ret = 0;
  428. struct sst_block *block;
  429. if (!fw_save)
  430. return 0;
  431. sst_set_fw_state_locked(ctx, SST_FW_LOADING);
  432. /* we have to restore the memory saved */
  433. ctx->ops->reset(ctx);
  434. ctx->fw_save = NULL;
  435. memcpy32_toio(ctx->iram, fw_save->iram, ctx->iram_end - ctx->iram_base);
  436. memcpy32_toio(ctx->dram, fw_save->dram, ctx->dram_end - ctx->dram_base);
  437. memcpy32_toio(ctx->mailbox, fw_save->sram, SST_MAILBOX_SIZE);
  438. memcpy32_toio(ctx->ddr, fw_save->ddr, ctx->ddr_end - ctx->ddr_base);
  439. kfree(fw_save->sram);
  440. kfree(fw_save->dram);
  441. kfree(fw_save->iram);
  442. kfree(fw_save->ddr);
  443. kfree(fw_save);
  444. block = sst_create_block(ctx, 0, FW_DWNL_ID);
  445. if (block == NULL)
  446. return -ENOMEM;
  447. /* start and wait for ack */
  448. ctx->ops->start(ctx);
  449. ret = sst_wait_timeout(ctx, block);
  450. if (ret) {
  451. dev_err(ctx->dev, "fw download failed %d\n", ret);
  452. /* FW download failed due to timeout */
  453. ret = -EBUSY;
  454. } else {
  455. sst_set_fw_state_locked(ctx, SST_FW_RUNNING);
  456. }
  457. sst_free_block(ctx, block);
  458. return ret;
  459. }
  460. const struct dev_pm_ops intel_sst_pm = {
  461. .suspend = intel_sst_suspend,
  462. .resume = intel_sst_resume,
  463. .runtime_suspend = intel_sst_runtime_suspend,
  464. };
  465. EXPORT_SYMBOL_GPL(intel_sst_pm);