img-spdif-out.c 11 KB

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  1. /*
  2. * IMG SPDIF output controller driver
  3. *
  4. * Copyright (C) 2015 Imagination Technologies Ltd.
  5. *
  6. * Author: Damien Horsley <Damien.Horsley@imgtec.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms and conditions of the GNU General Public License,
  10. * version 2, as published by the Free Software Foundation.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/init.h>
  14. #include <linux/kernel.h>
  15. #include <linux/module.h>
  16. #include <linux/of.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/reset.h>
  20. #include <sound/core.h>
  21. #include <sound/dmaengine_pcm.h>
  22. #include <sound/initval.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #define IMG_SPDIF_OUT_TX_FIFO 0x0
  27. #define IMG_SPDIF_OUT_CTL 0x4
  28. #define IMG_SPDIF_OUT_CTL_FS_MASK BIT(4)
  29. #define IMG_SPDIF_OUT_CTL_CLK_MASK BIT(2)
  30. #define IMG_SPDIF_OUT_CTL_SRT_MASK BIT(0)
  31. #define IMG_SPDIF_OUT_CSL 0x14
  32. #define IMG_SPDIF_OUT_CSH_UV 0x18
  33. #define IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT 0
  34. #define IMG_SPDIF_OUT_CSH_UV_CSH_MASK 0xff
  35. struct img_spdif_out {
  36. spinlock_t lock;
  37. void __iomem *base;
  38. struct clk *clk_sys;
  39. struct clk *clk_ref;
  40. struct snd_dmaengine_dai_dma_data dma_data;
  41. struct device *dev;
  42. struct reset_control *rst;
  43. };
  44. static int img_spdif_out_suspend(struct device *dev)
  45. {
  46. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  47. clk_disable_unprepare(spdif->clk_ref);
  48. return 0;
  49. }
  50. static int img_spdif_out_resume(struct device *dev)
  51. {
  52. struct img_spdif_out *spdif = dev_get_drvdata(dev);
  53. int ret;
  54. ret = clk_prepare_enable(spdif->clk_ref);
  55. if (ret) {
  56. dev_err(dev, "clk_enable failed: %d\n", ret);
  57. return ret;
  58. }
  59. return 0;
  60. }
  61. static inline void img_spdif_out_writel(struct img_spdif_out *spdif, u32 val,
  62. u32 reg)
  63. {
  64. writel(val, spdif->base + reg);
  65. }
  66. static inline u32 img_spdif_out_readl(struct img_spdif_out *spdif, u32 reg)
  67. {
  68. return readl(spdif->base + reg);
  69. }
  70. static void img_spdif_out_reset(struct img_spdif_out *spdif)
  71. {
  72. u32 ctl, status_low, status_high;
  73. ctl = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL) &
  74. ~IMG_SPDIF_OUT_CTL_SRT_MASK;
  75. status_low = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  76. status_high = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  77. reset_control_assert(spdif->rst);
  78. reset_control_deassert(spdif->rst);
  79. img_spdif_out_writel(spdif, ctl, IMG_SPDIF_OUT_CTL);
  80. img_spdif_out_writel(spdif, status_low, IMG_SPDIF_OUT_CSL);
  81. img_spdif_out_writel(spdif, status_high, IMG_SPDIF_OUT_CSH_UV);
  82. }
  83. static int img_spdif_out_info(struct snd_kcontrol *kcontrol,
  84. struct snd_ctl_elem_info *uinfo)
  85. {
  86. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  87. uinfo->count = 1;
  88. return 0;
  89. }
  90. static int img_spdif_out_get_status_mask(struct snd_kcontrol *kcontrol,
  91. struct snd_ctl_elem_value *ucontrol)
  92. {
  93. ucontrol->value.iec958.status[0] = 0xff;
  94. ucontrol->value.iec958.status[1] = 0xff;
  95. ucontrol->value.iec958.status[2] = 0xff;
  96. ucontrol->value.iec958.status[3] = 0xff;
  97. ucontrol->value.iec958.status[4] = 0xff;
  98. return 0;
  99. }
  100. static int img_spdif_out_get_status(struct snd_kcontrol *kcontrol,
  101. struct snd_ctl_elem_value *ucontrol)
  102. {
  103. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  104. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  105. u32 reg;
  106. unsigned long flags;
  107. spin_lock_irqsave(&spdif->lock, flags);
  108. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSL);
  109. ucontrol->value.iec958.status[0] = reg & 0xff;
  110. ucontrol->value.iec958.status[1] = (reg >> 8) & 0xff;
  111. ucontrol->value.iec958.status[2] = (reg >> 16) & 0xff;
  112. ucontrol->value.iec958.status[3] = (reg >> 24) & 0xff;
  113. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  114. ucontrol->value.iec958.status[4] =
  115. (reg & IMG_SPDIF_OUT_CSH_UV_CSH_MASK) >>
  116. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  117. spin_unlock_irqrestore(&spdif->lock, flags);
  118. return 0;
  119. }
  120. static int img_spdif_out_set_status(struct snd_kcontrol *kcontrol,
  121. struct snd_ctl_elem_value *ucontrol)
  122. {
  123. struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
  124. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(cpu_dai);
  125. u32 reg;
  126. unsigned long flags;
  127. reg = ((u32)ucontrol->value.iec958.status[3] << 24);
  128. reg |= ((u32)ucontrol->value.iec958.status[2] << 16);
  129. reg |= ((u32)ucontrol->value.iec958.status[1] << 8);
  130. reg |= (u32)ucontrol->value.iec958.status[0];
  131. spin_lock_irqsave(&spdif->lock, flags);
  132. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSL);
  133. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CSH_UV);
  134. reg &= ~IMG_SPDIF_OUT_CSH_UV_CSH_MASK;
  135. reg |= (u32)ucontrol->value.iec958.status[4] <<
  136. IMG_SPDIF_OUT_CSH_UV_CSH_SHIFT;
  137. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CSH_UV);
  138. spin_unlock_irqrestore(&spdif->lock, flags);
  139. return 0;
  140. }
  141. static struct snd_kcontrol_new img_spdif_out_controls[] = {
  142. {
  143. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  144. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  145. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
  146. .info = img_spdif_out_info,
  147. .get = img_spdif_out_get_status_mask
  148. },
  149. {
  150. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  151. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  152. .info = img_spdif_out_info,
  153. .get = img_spdif_out_get_status,
  154. .put = img_spdif_out_set_status
  155. }
  156. };
  157. static int img_spdif_out_trigger(struct snd_pcm_substream *substream, int cmd,
  158. struct snd_soc_dai *dai)
  159. {
  160. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  161. u32 reg;
  162. unsigned long flags;
  163. switch (cmd) {
  164. case SNDRV_PCM_TRIGGER_START:
  165. case SNDRV_PCM_TRIGGER_RESUME:
  166. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  167. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  168. reg |= IMG_SPDIF_OUT_CTL_SRT_MASK;
  169. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  170. break;
  171. case SNDRV_PCM_TRIGGER_STOP:
  172. case SNDRV_PCM_TRIGGER_SUSPEND:
  173. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  174. spin_lock_irqsave(&spdif->lock, flags);
  175. img_spdif_out_reset(spdif);
  176. spin_unlock_irqrestore(&spdif->lock, flags);
  177. break;
  178. default:
  179. return -EINVAL;
  180. }
  181. return 0;
  182. }
  183. static int img_spdif_out_hw_params(struct snd_pcm_substream *substream,
  184. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  185. {
  186. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  187. unsigned int channels;
  188. long pre_div_a, pre_div_b, diff_a, diff_b, rate, clk_rate;
  189. u32 reg;
  190. snd_pcm_format_t format;
  191. rate = params_rate(params);
  192. format = params_format(params);
  193. channels = params_channels(params);
  194. dev_dbg(spdif->dev, "hw_params rate %ld channels %u format %u\n",
  195. rate, channels, format);
  196. if (format != SNDRV_PCM_FORMAT_S32_LE)
  197. return -EINVAL;
  198. if (channels != 2)
  199. return -EINVAL;
  200. pre_div_a = clk_round_rate(spdif->clk_ref, rate * 256);
  201. if (pre_div_a < 0)
  202. return pre_div_a;
  203. pre_div_b = clk_round_rate(spdif->clk_ref, rate * 384);
  204. if (pre_div_b < 0)
  205. return pre_div_b;
  206. diff_a = abs((pre_div_a / 256) - rate);
  207. diff_b = abs((pre_div_b / 384) - rate);
  208. /* If diffs are equal, use lower clock rate */
  209. if (diff_a > diff_b)
  210. clk_set_rate(spdif->clk_ref, pre_div_b);
  211. else
  212. clk_set_rate(spdif->clk_ref, pre_div_a);
  213. /*
  214. * Another driver (eg machine driver) may have rejected the above
  215. * change. Get the current rate and set the register bit according to
  216. * the new min diff
  217. */
  218. clk_rate = clk_get_rate(spdif->clk_ref);
  219. diff_a = abs((clk_rate / 256) - rate);
  220. diff_b = abs((clk_rate / 384) - rate);
  221. reg = img_spdif_out_readl(spdif, IMG_SPDIF_OUT_CTL);
  222. if (diff_a <= diff_b)
  223. reg &= ~IMG_SPDIF_OUT_CTL_CLK_MASK;
  224. else
  225. reg |= IMG_SPDIF_OUT_CTL_CLK_MASK;
  226. img_spdif_out_writel(spdif, reg, IMG_SPDIF_OUT_CTL);
  227. return 0;
  228. }
  229. static const struct snd_soc_dai_ops img_spdif_out_dai_ops = {
  230. .trigger = img_spdif_out_trigger,
  231. .hw_params = img_spdif_out_hw_params
  232. };
  233. static int img_spdif_out_dai_probe(struct snd_soc_dai *dai)
  234. {
  235. struct img_spdif_out *spdif = snd_soc_dai_get_drvdata(dai);
  236. snd_soc_dai_init_dma_data(dai, &spdif->dma_data, NULL);
  237. snd_soc_add_dai_controls(dai, img_spdif_out_controls,
  238. ARRAY_SIZE(img_spdif_out_controls));
  239. return 0;
  240. }
  241. static struct snd_soc_dai_driver img_spdif_out_dai = {
  242. .probe = img_spdif_out_dai_probe,
  243. .playback = {
  244. .channels_min = 2,
  245. .channels_max = 2,
  246. .rates = SNDRV_PCM_RATE_8000_192000,
  247. .formats = SNDRV_PCM_FMTBIT_S32_LE
  248. },
  249. .ops = &img_spdif_out_dai_ops
  250. };
  251. static const struct snd_soc_component_driver img_spdif_out_component = {
  252. .name = "img-spdif-out"
  253. };
  254. static int img_spdif_out_probe(struct platform_device *pdev)
  255. {
  256. struct img_spdif_out *spdif;
  257. struct resource *res;
  258. void __iomem *base;
  259. int ret;
  260. struct device *dev = &pdev->dev;
  261. spdif = devm_kzalloc(&pdev->dev, sizeof(*spdif), GFP_KERNEL);
  262. if (!spdif)
  263. return -ENOMEM;
  264. platform_set_drvdata(pdev, spdif);
  265. spdif->dev = &pdev->dev;
  266. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  267. base = devm_ioremap_resource(&pdev->dev, res);
  268. if (IS_ERR(base))
  269. return PTR_ERR(base);
  270. spdif->base = base;
  271. spdif->rst = devm_reset_control_get(&pdev->dev, "rst");
  272. if (IS_ERR(spdif->rst)) {
  273. if (PTR_ERR(spdif->rst) != -EPROBE_DEFER)
  274. dev_err(&pdev->dev, "No top level reset found\n");
  275. return PTR_ERR(spdif->rst);
  276. }
  277. spdif->clk_sys = devm_clk_get(&pdev->dev, "sys");
  278. if (IS_ERR(spdif->clk_sys)) {
  279. if (PTR_ERR(spdif->clk_sys) != -EPROBE_DEFER)
  280. dev_err(dev, "Failed to acquire clock 'sys'\n");
  281. return PTR_ERR(spdif->clk_sys);
  282. }
  283. spdif->clk_ref = devm_clk_get(&pdev->dev, "ref");
  284. if (IS_ERR(spdif->clk_ref)) {
  285. if (PTR_ERR(spdif->clk_ref) != -EPROBE_DEFER)
  286. dev_err(dev, "Failed to acquire clock 'ref'\n");
  287. return PTR_ERR(spdif->clk_ref);
  288. }
  289. ret = clk_prepare_enable(spdif->clk_sys);
  290. if (ret)
  291. return ret;
  292. img_spdif_out_writel(spdif, IMG_SPDIF_OUT_CTL_FS_MASK,
  293. IMG_SPDIF_OUT_CTL);
  294. img_spdif_out_reset(spdif);
  295. pm_runtime_enable(&pdev->dev);
  296. if (!pm_runtime_enabled(&pdev->dev)) {
  297. ret = img_spdif_out_resume(&pdev->dev);
  298. if (ret)
  299. goto err_pm_disable;
  300. }
  301. spin_lock_init(&spdif->lock);
  302. spdif->dma_data.addr = res->start + IMG_SPDIF_OUT_TX_FIFO;
  303. spdif->dma_data.addr_width = 4;
  304. spdif->dma_data.maxburst = 4;
  305. ret = devm_snd_soc_register_component(&pdev->dev,
  306. &img_spdif_out_component,
  307. &img_spdif_out_dai, 1);
  308. if (ret)
  309. goto err_suspend;
  310. ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
  311. if (ret)
  312. goto err_suspend;
  313. dev_dbg(&pdev->dev, "Probe successful\n");
  314. return 0;
  315. err_suspend:
  316. if (!pm_runtime_status_suspended(&pdev->dev))
  317. img_spdif_out_suspend(&pdev->dev);
  318. err_pm_disable:
  319. pm_runtime_disable(&pdev->dev);
  320. clk_disable_unprepare(spdif->clk_sys);
  321. return ret;
  322. }
  323. static int img_spdif_out_dev_remove(struct platform_device *pdev)
  324. {
  325. struct img_spdif_out *spdif = platform_get_drvdata(pdev);
  326. pm_runtime_disable(&pdev->dev);
  327. if (!pm_runtime_status_suspended(&pdev->dev))
  328. img_spdif_out_suspend(&pdev->dev);
  329. clk_disable_unprepare(spdif->clk_sys);
  330. return 0;
  331. }
  332. static const struct of_device_id img_spdif_out_of_match[] = {
  333. { .compatible = "img,spdif-out" },
  334. {}
  335. };
  336. MODULE_DEVICE_TABLE(of, img_spdif_out_of_match);
  337. static const struct dev_pm_ops img_spdif_out_pm_ops = {
  338. SET_RUNTIME_PM_OPS(img_spdif_out_suspend,
  339. img_spdif_out_resume, NULL)
  340. };
  341. static struct platform_driver img_spdif_out_driver = {
  342. .driver = {
  343. .name = "img-spdif-out",
  344. .of_match_table = img_spdif_out_of_match,
  345. .pm = &img_spdif_out_pm_ops
  346. },
  347. .probe = img_spdif_out_probe,
  348. .remove = img_spdif_out_dev_remove
  349. };
  350. module_platform_driver(img_spdif_out_driver);
  351. MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
  352. MODULE_DESCRIPTION("IMG SPDIF Output driver");
  353. MODULE_LICENSE("GPL v2");