wm_adsp.c 79 KB

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  1. /*
  2. * wm_adsp.c -- Wolfson ADSP support
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/firmware.h>
  17. #include <linux/list.h>
  18. #include <linux/pm.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/regmap.h>
  21. #include <linux/regulator/consumer.h>
  22. #include <linux/slab.h>
  23. #include <linux/vmalloc.h>
  24. #include <linux/workqueue.h>
  25. #include <linux/debugfs.h>
  26. #include <sound/core.h>
  27. #include <sound/pcm.h>
  28. #include <sound/pcm_params.h>
  29. #include <sound/soc.h>
  30. #include <sound/jack.h>
  31. #include <sound/initval.h>
  32. #include <sound/tlv.h>
  33. #include "wm_adsp.h"
  34. #define adsp_crit(_dsp, fmt, ...) \
  35. dev_crit(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  36. #define adsp_err(_dsp, fmt, ...) \
  37. dev_err(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  38. #define adsp_warn(_dsp, fmt, ...) \
  39. dev_warn(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  40. #define adsp_info(_dsp, fmt, ...) \
  41. dev_info(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  42. #define adsp_dbg(_dsp, fmt, ...) \
  43. dev_dbg(_dsp->dev, "DSP%d: " fmt, _dsp->num, ##__VA_ARGS__)
  44. #define ADSP1_CONTROL_1 0x00
  45. #define ADSP1_CONTROL_2 0x02
  46. #define ADSP1_CONTROL_3 0x03
  47. #define ADSP1_CONTROL_4 0x04
  48. #define ADSP1_CONTROL_5 0x06
  49. #define ADSP1_CONTROL_6 0x07
  50. #define ADSP1_CONTROL_7 0x08
  51. #define ADSP1_CONTROL_8 0x09
  52. #define ADSP1_CONTROL_9 0x0A
  53. #define ADSP1_CONTROL_10 0x0B
  54. #define ADSP1_CONTROL_11 0x0C
  55. #define ADSP1_CONTROL_12 0x0D
  56. #define ADSP1_CONTROL_13 0x0F
  57. #define ADSP1_CONTROL_14 0x10
  58. #define ADSP1_CONTROL_15 0x11
  59. #define ADSP1_CONTROL_16 0x12
  60. #define ADSP1_CONTROL_17 0x13
  61. #define ADSP1_CONTROL_18 0x14
  62. #define ADSP1_CONTROL_19 0x16
  63. #define ADSP1_CONTROL_20 0x17
  64. #define ADSP1_CONTROL_21 0x18
  65. #define ADSP1_CONTROL_22 0x1A
  66. #define ADSP1_CONTROL_23 0x1B
  67. #define ADSP1_CONTROL_24 0x1C
  68. #define ADSP1_CONTROL_25 0x1E
  69. #define ADSP1_CONTROL_26 0x20
  70. #define ADSP1_CONTROL_27 0x21
  71. #define ADSP1_CONTROL_28 0x22
  72. #define ADSP1_CONTROL_29 0x23
  73. #define ADSP1_CONTROL_30 0x24
  74. #define ADSP1_CONTROL_31 0x26
  75. /*
  76. * ADSP1 Control 19
  77. */
  78. #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  79. #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  80. #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
  81. /*
  82. * ADSP1 Control 30
  83. */
  84. #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
  85. #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
  86. #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
  87. #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
  88. #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  89. #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  90. #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  91. #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  92. #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  93. #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  94. #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  95. #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  96. #define ADSP1_START 0x0001 /* DSP1_START */
  97. #define ADSP1_START_MASK 0x0001 /* DSP1_START */
  98. #define ADSP1_START_SHIFT 0 /* DSP1_START */
  99. #define ADSP1_START_WIDTH 1 /* DSP1_START */
  100. /*
  101. * ADSP1 Control 31
  102. */
  103. #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
  104. #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
  105. #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
  106. #define ADSP2_CONTROL 0x0
  107. #define ADSP2_CLOCKING 0x1
  108. #define ADSP2_STATUS1 0x4
  109. #define ADSP2_WDMA_CONFIG_1 0x30
  110. #define ADSP2_WDMA_CONFIG_2 0x31
  111. #define ADSP2_RDMA_CONFIG_1 0x34
  112. #define ADSP2_SCRATCH0 0x40
  113. #define ADSP2_SCRATCH1 0x41
  114. #define ADSP2_SCRATCH2 0x42
  115. #define ADSP2_SCRATCH3 0x43
  116. /*
  117. * ADSP2 Control
  118. */
  119. #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
  120. #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
  121. #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
  122. #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
  123. #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  124. #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  125. #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  126. #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  127. #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  128. #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  129. #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  130. #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  131. #define ADSP2_START 0x0001 /* DSP1_START */
  132. #define ADSP2_START_MASK 0x0001 /* DSP1_START */
  133. #define ADSP2_START_SHIFT 0 /* DSP1_START */
  134. #define ADSP2_START_WIDTH 1 /* DSP1_START */
  135. /*
  136. * ADSP2 clocking
  137. */
  138. #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
  139. #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
  140. #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
  141. /*
  142. * ADSP2 Status 1
  143. */
  144. #define ADSP2_RAM_RDY 0x0001
  145. #define ADSP2_RAM_RDY_MASK 0x0001
  146. #define ADSP2_RAM_RDY_SHIFT 0
  147. #define ADSP2_RAM_RDY_WIDTH 1
  148. #define ADSP_MAX_STD_CTRL_SIZE 512
  149. struct wm_adsp_buf {
  150. struct list_head list;
  151. void *buf;
  152. };
  153. static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
  154. struct list_head *list)
  155. {
  156. struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  157. if (buf == NULL)
  158. return NULL;
  159. buf->buf = vmalloc(len);
  160. if (!buf->buf) {
  161. vfree(buf);
  162. return NULL;
  163. }
  164. memcpy(buf->buf, src, len);
  165. if (list)
  166. list_add_tail(&buf->list, list);
  167. return buf;
  168. }
  169. static void wm_adsp_buf_free(struct list_head *list)
  170. {
  171. while (!list_empty(list)) {
  172. struct wm_adsp_buf *buf = list_first_entry(list,
  173. struct wm_adsp_buf,
  174. list);
  175. list_del(&buf->list);
  176. vfree(buf->buf);
  177. kfree(buf);
  178. }
  179. }
  180. #define WM_ADSP_FW_MBC_VSS 0
  181. #define WM_ADSP_FW_HIFI 1
  182. #define WM_ADSP_FW_TX 2
  183. #define WM_ADSP_FW_TX_SPK 3
  184. #define WM_ADSP_FW_RX 4
  185. #define WM_ADSP_FW_RX_ANC 5
  186. #define WM_ADSP_FW_CTRL 6
  187. #define WM_ADSP_FW_ASR 7
  188. #define WM_ADSP_FW_TRACE 8
  189. #define WM_ADSP_FW_SPK_PROT 9
  190. #define WM_ADSP_FW_MISC 10
  191. #define WM_ADSP_NUM_FW 11
  192. static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
  193. [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
  194. [WM_ADSP_FW_HIFI] = "MasterHiFi",
  195. [WM_ADSP_FW_TX] = "Tx",
  196. [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
  197. [WM_ADSP_FW_RX] = "Rx",
  198. [WM_ADSP_FW_RX_ANC] = "Rx ANC",
  199. [WM_ADSP_FW_CTRL] = "Voice Ctrl",
  200. [WM_ADSP_FW_ASR] = "ASR Assist",
  201. [WM_ADSP_FW_TRACE] = "Dbg Trace",
  202. [WM_ADSP_FW_SPK_PROT] = "Protection",
  203. [WM_ADSP_FW_MISC] = "Misc",
  204. };
  205. struct wm_adsp_system_config_xm_hdr {
  206. __be32 sys_enable;
  207. __be32 fw_id;
  208. __be32 fw_rev;
  209. __be32 boot_status;
  210. __be32 watchdog;
  211. __be32 dma_buffer_size;
  212. __be32 rdma[6];
  213. __be32 wdma[8];
  214. __be32 build_job_name[3];
  215. __be32 build_job_number;
  216. };
  217. struct wm_adsp_alg_xm_struct {
  218. __be32 magic;
  219. __be32 smoothing;
  220. __be32 threshold;
  221. __be32 host_buf_ptr;
  222. __be32 start_seq;
  223. __be32 high_water_mark;
  224. __be32 low_water_mark;
  225. __be64 smoothed_power;
  226. };
  227. struct wm_adsp_buffer {
  228. __be32 X_buf_base; /* XM base addr of first X area */
  229. __be32 X_buf_size; /* Size of 1st X area in words */
  230. __be32 X_buf_base2; /* XM base addr of 2nd X area */
  231. __be32 X_buf_brk; /* Total X size in words */
  232. __be32 Y_buf_base; /* YM base addr of Y area */
  233. __be32 wrap; /* Total size X and Y in words */
  234. __be32 high_water_mark; /* Point at which IRQ is asserted */
  235. __be32 irq_count; /* bits 1-31 count IRQ assertions */
  236. __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
  237. __be32 next_write_index; /* word index of next write */
  238. __be32 next_read_index; /* word index of next read */
  239. __be32 error; /* error if any */
  240. __be32 oldest_block_index; /* word index of oldest surviving */
  241. __be32 requested_rewind; /* how many blocks rewind was done */
  242. __be32 reserved_space; /* internal */
  243. __be32 min_free; /* min free space since stream start */
  244. __be32 blocks_written[2]; /* total blocks written (64 bit) */
  245. __be32 words_written[2]; /* total words written (64 bit) */
  246. };
  247. struct wm_adsp_compr;
  248. struct wm_adsp_compr_buf {
  249. struct wm_adsp *dsp;
  250. struct wm_adsp_compr *compr;
  251. struct wm_adsp_buffer_region *regions;
  252. u32 host_buf_ptr;
  253. u32 error;
  254. u32 irq_count;
  255. int read_index;
  256. int avail;
  257. };
  258. struct wm_adsp_compr {
  259. struct wm_adsp *dsp;
  260. struct wm_adsp_compr_buf *buf;
  261. struct snd_compr_stream *stream;
  262. struct snd_compressed_buffer size;
  263. u32 *raw_buf;
  264. unsigned int copied_total;
  265. unsigned int sample_rate;
  266. };
  267. #define WM_ADSP_DATA_WORD_SIZE 3
  268. #define WM_ADSP_MIN_FRAGMENTS 1
  269. #define WM_ADSP_MAX_FRAGMENTS 256
  270. #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
  271. #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
  272. #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
  273. #define HOST_BUFFER_FIELD(field) \
  274. (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
  275. #define ALG_XM_FIELD(field) \
  276. (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
  277. static int wm_adsp_buffer_init(struct wm_adsp *dsp);
  278. static int wm_adsp_buffer_free(struct wm_adsp *dsp);
  279. struct wm_adsp_buffer_region {
  280. unsigned int offset;
  281. unsigned int cumulative_size;
  282. unsigned int mem_type;
  283. unsigned int base_addr;
  284. };
  285. struct wm_adsp_buffer_region_def {
  286. unsigned int mem_type;
  287. unsigned int base_offset;
  288. unsigned int size_offset;
  289. };
  290. static const struct wm_adsp_buffer_region_def default_regions[] = {
  291. {
  292. .mem_type = WMFW_ADSP2_XM,
  293. .base_offset = HOST_BUFFER_FIELD(X_buf_base),
  294. .size_offset = HOST_BUFFER_FIELD(X_buf_size),
  295. },
  296. {
  297. .mem_type = WMFW_ADSP2_XM,
  298. .base_offset = HOST_BUFFER_FIELD(X_buf_base2),
  299. .size_offset = HOST_BUFFER_FIELD(X_buf_brk),
  300. },
  301. {
  302. .mem_type = WMFW_ADSP2_YM,
  303. .base_offset = HOST_BUFFER_FIELD(Y_buf_base),
  304. .size_offset = HOST_BUFFER_FIELD(wrap),
  305. },
  306. };
  307. struct wm_adsp_fw_caps {
  308. u32 id;
  309. struct snd_codec_desc desc;
  310. int num_regions;
  311. const struct wm_adsp_buffer_region_def *region_defs;
  312. };
  313. static const struct wm_adsp_fw_caps ctrl_caps[] = {
  314. {
  315. .id = SND_AUDIOCODEC_BESPOKE,
  316. .desc = {
  317. .max_ch = 1,
  318. .sample_rates = { 16000 },
  319. .num_sample_rates = 1,
  320. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  321. },
  322. .num_regions = ARRAY_SIZE(default_regions),
  323. .region_defs = default_regions,
  324. },
  325. };
  326. static const struct wm_adsp_fw_caps trace_caps[] = {
  327. {
  328. .id = SND_AUDIOCODEC_BESPOKE,
  329. .desc = {
  330. .max_ch = 8,
  331. .sample_rates = {
  332. 4000, 8000, 11025, 12000, 16000, 22050,
  333. 24000, 32000, 44100, 48000, 64000, 88200,
  334. 96000, 176400, 192000
  335. },
  336. .num_sample_rates = 15,
  337. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  338. },
  339. .num_regions = ARRAY_SIZE(default_regions),
  340. .region_defs = default_regions,
  341. },
  342. };
  343. static const struct {
  344. const char *file;
  345. int compr_direction;
  346. int num_caps;
  347. const struct wm_adsp_fw_caps *caps;
  348. bool voice_trigger;
  349. } wm_adsp_fw[WM_ADSP_NUM_FW] = {
  350. [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
  351. [WM_ADSP_FW_HIFI] = { .file = "hifi" },
  352. [WM_ADSP_FW_TX] = { .file = "tx" },
  353. [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
  354. [WM_ADSP_FW_RX] = { .file = "rx" },
  355. [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
  356. [WM_ADSP_FW_CTRL] = {
  357. .file = "ctrl",
  358. .compr_direction = SND_COMPRESS_CAPTURE,
  359. .num_caps = ARRAY_SIZE(ctrl_caps),
  360. .caps = ctrl_caps,
  361. .voice_trigger = true,
  362. },
  363. [WM_ADSP_FW_ASR] = { .file = "asr" },
  364. [WM_ADSP_FW_TRACE] = {
  365. .file = "trace",
  366. .compr_direction = SND_COMPRESS_CAPTURE,
  367. .num_caps = ARRAY_SIZE(trace_caps),
  368. .caps = trace_caps,
  369. },
  370. [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
  371. [WM_ADSP_FW_MISC] = { .file = "misc" },
  372. };
  373. struct wm_coeff_ctl_ops {
  374. int (*xget)(struct snd_kcontrol *kcontrol,
  375. struct snd_ctl_elem_value *ucontrol);
  376. int (*xput)(struct snd_kcontrol *kcontrol,
  377. struct snd_ctl_elem_value *ucontrol);
  378. int (*xinfo)(struct snd_kcontrol *kcontrol,
  379. struct snd_ctl_elem_info *uinfo);
  380. };
  381. struct wm_coeff_ctl {
  382. const char *name;
  383. const char *fw_name;
  384. struct wm_adsp_alg_region alg_region;
  385. struct wm_coeff_ctl_ops ops;
  386. struct wm_adsp *dsp;
  387. unsigned int enabled:1;
  388. struct list_head list;
  389. void *cache;
  390. unsigned int offset;
  391. size_t len;
  392. unsigned int set:1;
  393. struct snd_kcontrol *kcontrol;
  394. struct soc_bytes_ext bytes_ext;
  395. unsigned int flags;
  396. };
  397. #ifdef CONFIG_DEBUG_FS
  398. static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
  399. {
  400. char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
  401. kfree(dsp->wmfw_file_name);
  402. dsp->wmfw_file_name = tmp;
  403. }
  404. static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
  405. {
  406. char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
  407. kfree(dsp->bin_file_name);
  408. dsp->bin_file_name = tmp;
  409. }
  410. static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
  411. {
  412. kfree(dsp->wmfw_file_name);
  413. kfree(dsp->bin_file_name);
  414. dsp->wmfw_file_name = NULL;
  415. dsp->bin_file_name = NULL;
  416. }
  417. static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
  418. char __user *user_buf,
  419. size_t count, loff_t *ppos)
  420. {
  421. struct wm_adsp *dsp = file->private_data;
  422. ssize_t ret;
  423. mutex_lock(&dsp->pwr_lock);
  424. if (!dsp->wmfw_file_name || !dsp->booted)
  425. ret = 0;
  426. else
  427. ret = simple_read_from_buffer(user_buf, count, ppos,
  428. dsp->wmfw_file_name,
  429. strlen(dsp->wmfw_file_name));
  430. mutex_unlock(&dsp->pwr_lock);
  431. return ret;
  432. }
  433. static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
  434. char __user *user_buf,
  435. size_t count, loff_t *ppos)
  436. {
  437. struct wm_adsp *dsp = file->private_data;
  438. ssize_t ret;
  439. mutex_lock(&dsp->pwr_lock);
  440. if (!dsp->bin_file_name || !dsp->booted)
  441. ret = 0;
  442. else
  443. ret = simple_read_from_buffer(user_buf, count, ppos,
  444. dsp->bin_file_name,
  445. strlen(dsp->bin_file_name));
  446. mutex_unlock(&dsp->pwr_lock);
  447. return ret;
  448. }
  449. static const struct {
  450. const char *name;
  451. const struct file_operations fops;
  452. } wm_adsp_debugfs_fops[] = {
  453. {
  454. .name = "wmfw_file_name",
  455. .fops = {
  456. .open = simple_open,
  457. .read = wm_adsp_debugfs_wmfw_read,
  458. },
  459. },
  460. {
  461. .name = "bin_file_name",
  462. .fops = {
  463. .open = simple_open,
  464. .read = wm_adsp_debugfs_bin_read,
  465. },
  466. },
  467. };
  468. static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
  469. struct snd_soc_codec *codec)
  470. {
  471. struct dentry *root = NULL;
  472. char *root_name;
  473. int i;
  474. if (!codec->component.debugfs_root) {
  475. adsp_err(dsp, "No codec debugfs root\n");
  476. goto err;
  477. }
  478. root_name = kmalloc(PAGE_SIZE, GFP_KERNEL);
  479. if (!root_name)
  480. goto err;
  481. snprintf(root_name, PAGE_SIZE, "dsp%d", dsp->num);
  482. root = debugfs_create_dir(root_name, codec->component.debugfs_root);
  483. kfree(root_name);
  484. if (!root)
  485. goto err;
  486. if (!debugfs_create_bool("booted", S_IRUGO, root, &dsp->booted))
  487. goto err;
  488. if (!debugfs_create_bool("running", S_IRUGO, root, &dsp->running))
  489. goto err;
  490. if (!debugfs_create_x32("fw_id", S_IRUGO, root, &dsp->fw_id))
  491. goto err;
  492. if (!debugfs_create_x32("fw_version", S_IRUGO, root,
  493. &dsp->fw_id_version))
  494. goto err;
  495. for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
  496. if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
  497. S_IRUGO, root, dsp,
  498. &wm_adsp_debugfs_fops[i].fops))
  499. goto err;
  500. }
  501. dsp->debugfs_root = root;
  502. return;
  503. err:
  504. debugfs_remove_recursive(root);
  505. adsp_err(dsp, "Failed to create debugfs\n");
  506. }
  507. static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
  508. {
  509. wm_adsp_debugfs_clear(dsp);
  510. debugfs_remove_recursive(dsp->debugfs_root);
  511. }
  512. #else
  513. static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
  514. struct snd_soc_codec *codec)
  515. {
  516. }
  517. static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
  518. {
  519. }
  520. static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
  521. const char *s)
  522. {
  523. }
  524. static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
  525. const char *s)
  526. {
  527. }
  528. static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
  529. {
  530. }
  531. #endif
  532. static int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
  533. struct snd_ctl_elem_value *ucontrol)
  534. {
  535. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  536. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  537. struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
  538. ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
  539. return 0;
  540. }
  541. static int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
  542. struct snd_ctl_elem_value *ucontrol)
  543. {
  544. struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
  545. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  546. struct wm_adsp *dsp = snd_soc_codec_get_drvdata(codec);
  547. int ret = 0;
  548. if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
  549. return 0;
  550. if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
  551. return -EINVAL;
  552. mutex_lock(&dsp[e->shift_l].pwr_lock);
  553. if (dsp[e->shift_l].booted || dsp[e->shift_l].compr)
  554. ret = -EBUSY;
  555. else
  556. dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
  557. mutex_unlock(&dsp[e->shift_l].pwr_lock);
  558. return ret;
  559. }
  560. static const struct soc_enum wm_adsp_fw_enum[] = {
  561. SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
  562. SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
  563. SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
  564. SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
  565. };
  566. const struct snd_kcontrol_new wm_adsp_fw_controls[] = {
  567. SOC_ENUM_EXT("DSP1 Firmware", wm_adsp_fw_enum[0],
  568. wm_adsp_fw_get, wm_adsp_fw_put),
  569. SOC_ENUM_EXT("DSP2 Firmware", wm_adsp_fw_enum[1],
  570. wm_adsp_fw_get, wm_adsp_fw_put),
  571. SOC_ENUM_EXT("DSP3 Firmware", wm_adsp_fw_enum[2],
  572. wm_adsp_fw_get, wm_adsp_fw_put),
  573. SOC_ENUM_EXT("DSP4 Firmware", wm_adsp_fw_enum[3],
  574. wm_adsp_fw_get, wm_adsp_fw_put),
  575. };
  576. EXPORT_SYMBOL_GPL(wm_adsp_fw_controls);
  577. static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
  578. int type)
  579. {
  580. int i;
  581. for (i = 0; i < dsp->num_mems; i++)
  582. if (dsp->mem[i].type == type)
  583. return &dsp->mem[i];
  584. return NULL;
  585. }
  586. static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
  587. unsigned int offset)
  588. {
  589. if (WARN_ON(!mem))
  590. return offset;
  591. switch (mem->type) {
  592. case WMFW_ADSP1_PM:
  593. return mem->base + (offset * 3);
  594. case WMFW_ADSP1_DM:
  595. return mem->base + (offset * 2);
  596. case WMFW_ADSP2_XM:
  597. return mem->base + (offset * 2);
  598. case WMFW_ADSP2_YM:
  599. return mem->base + (offset * 2);
  600. case WMFW_ADSP1_ZM:
  601. return mem->base + (offset * 2);
  602. default:
  603. WARN(1, "Unknown memory region type");
  604. return offset;
  605. }
  606. }
  607. static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
  608. {
  609. u16 scratch[4];
  610. int ret;
  611. ret = regmap_raw_read(dsp->regmap, dsp->base + ADSP2_SCRATCH0,
  612. scratch, sizeof(scratch));
  613. if (ret) {
  614. adsp_err(dsp, "Failed to read SCRATCH regs: %d\n", ret);
  615. return;
  616. }
  617. adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
  618. be16_to_cpu(scratch[0]),
  619. be16_to_cpu(scratch[1]),
  620. be16_to_cpu(scratch[2]),
  621. be16_to_cpu(scratch[3]));
  622. }
  623. static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
  624. {
  625. return container_of(ext, struct wm_coeff_ctl, bytes_ext);
  626. }
  627. static int wm_coeff_info(struct snd_kcontrol *kctl,
  628. struct snd_ctl_elem_info *uinfo)
  629. {
  630. struct soc_bytes_ext *bytes_ext =
  631. (struct soc_bytes_ext *)kctl->private_value;
  632. struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
  633. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  634. uinfo->count = ctl->len;
  635. return 0;
  636. }
  637. static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
  638. const void *buf, size_t len)
  639. {
  640. struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
  641. const struct wm_adsp_region *mem;
  642. struct wm_adsp *dsp = ctl->dsp;
  643. void *scratch;
  644. int ret;
  645. unsigned int reg;
  646. mem = wm_adsp_find_region(dsp, alg_region->type);
  647. if (!mem) {
  648. adsp_err(dsp, "No base for region %x\n",
  649. alg_region->type);
  650. return -EINVAL;
  651. }
  652. reg = ctl->alg_region.base + ctl->offset;
  653. reg = wm_adsp_region_to_reg(mem, reg);
  654. scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
  655. if (!scratch)
  656. return -ENOMEM;
  657. ret = regmap_raw_write(dsp->regmap, reg, scratch,
  658. len);
  659. if (ret) {
  660. adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
  661. len, reg, ret);
  662. kfree(scratch);
  663. return ret;
  664. }
  665. adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
  666. kfree(scratch);
  667. return 0;
  668. }
  669. static int wm_coeff_put(struct snd_kcontrol *kctl,
  670. struct snd_ctl_elem_value *ucontrol)
  671. {
  672. struct soc_bytes_ext *bytes_ext =
  673. (struct soc_bytes_ext *)kctl->private_value;
  674. struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
  675. char *p = ucontrol->value.bytes.data;
  676. int ret = 0;
  677. mutex_lock(&ctl->dsp->pwr_lock);
  678. if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
  679. ret = -EPERM;
  680. else
  681. memcpy(ctl->cache, p, ctl->len);
  682. ctl->set = 1;
  683. if (ctl->enabled && ctl->dsp->running)
  684. ret = wm_coeff_write_control(ctl, p, ctl->len);
  685. mutex_unlock(&ctl->dsp->pwr_lock);
  686. return ret;
  687. }
  688. static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
  689. const unsigned int __user *bytes, unsigned int size)
  690. {
  691. struct soc_bytes_ext *bytes_ext =
  692. (struct soc_bytes_ext *)kctl->private_value;
  693. struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
  694. int ret = 0;
  695. mutex_lock(&ctl->dsp->pwr_lock);
  696. if (copy_from_user(ctl->cache, bytes, size)) {
  697. ret = -EFAULT;
  698. } else {
  699. ctl->set = 1;
  700. if (ctl->enabled && ctl->dsp->running)
  701. ret = wm_coeff_write_control(ctl, ctl->cache, size);
  702. else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
  703. ret = -EPERM;
  704. }
  705. mutex_unlock(&ctl->dsp->pwr_lock);
  706. return ret;
  707. }
  708. static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
  709. void *buf, size_t len)
  710. {
  711. struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
  712. const struct wm_adsp_region *mem;
  713. struct wm_adsp *dsp = ctl->dsp;
  714. void *scratch;
  715. int ret;
  716. unsigned int reg;
  717. mem = wm_adsp_find_region(dsp, alg_region->type);
  718. if (!mem) {
  719. adsp_err(dsp, "No base for region %x\n",
  720. alg_region->type);
  721. return -EINVAL;
  722. }
  723. reg = ctl->alg_region.base + ctl->offset;
  724. reg = wm_adsp_region_to_reg(mem, reg);
  725. scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
  726. if (!scratch)
  727. return -ENOMEM;
  728. ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
  729. if (ret) {
  730. adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
  731. len, reg, ret);
  732. kfree(scratch);
  733. return ret;
  734. }
  735. adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
  736. memcpy(buf, scratch, len);
  737. kfree(scratch);
  738. return 0;
  739. }
  740. static int wm_coeff_get(struct snd_kcontrol *kctl,
  741. struct snd_ctl_elem_value *ucontrol)
  742. {
  743. struct soc_bytes_ext *bytes_ext =
  744. (struct soc_bytes_ext *)kctl->private_value;
  745. struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
  746. char *p = ucontrol->value.bytes.data;
  747. int ret = 0;
  748. mutex_lock(&ctl->dsp->pwr_lock);
  749. if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
  750. if (ctl->enabled && ctl->dsp->running)
  751. ret = wm_coeff_read_control(ctl, p, ctl->len);
  752. else
  753. ret = -EPERM;
  754. } else {
  755. if (!ctl->flags && ctl->enabled && ctl->dsp->running)
  756. ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
  757. memcpy(p, ctl->cache, ctl->len);
  758. }
  759. mutex_unlock(&ctl->dsp->pwr_lock);
  760. return ret;
  761. }
  762. static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
  763. unsigned int __user *bytes, unsigned int size)
  764. {
  765. struct soc_bytes_ext *bytes_ext =
  766. (struct soc_bytes_ext *)kctl->private_value;
  767. struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
  768. int ret = 0;
  769. mutex_lock(&ctl->dsp->pwr_lock);
  770. if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
  771. if (ctl->enabled && ctl->dsp->running)
  772. ret = wm_coeff_read_control(ctl, ctl->cache, size);
  773. else
  774. ret = -EPERM;
  775. } else {
  776. if (!ctl->flags && ctl->enabled && ctl->dsp->running)
  777. ret = wm_coeff_read_control(ctl, ctl->cache, size);
  778. }
  779. if (!ret && copy_to_user(bytes, ctl->cache, size))
  780. ret = -EFAULT;
  781. mutex_unlock(&ctl->dsp->pwr_lock);
  782. return ret;
  783. }
  784. struct wmfw_ctl_work {
  785. struct wm_adsp *dsp;
  786. struct wm_coeff_ctl *ctl;
  787. struct work_struct work;
  788. };
  789. static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
  790. {
  791. unsigned int out, rd, wr, vol;
  792. if (len > ADSP_MAX_STD_CTRL_SIZE) {
  793. rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  794. wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
  795. vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
  796. out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
  797. } else {
  798. rd = SNDRV_CTL_ELEM_ACCESS_READ;
  799. wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
  800. vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
  801. out = 0;
  802. }
  803. if (in) {
  804. if (in & WMFW_CTL_FLAG_READABLE)
  805. out |= rd;
  806. if (in & WMFW_CTL_FLAG_WRITEABLE)
  807. out |= wr;
  808. if (in & WMFW_CTL_FLAG_VOLATILE)
  809. out |= vol;
  810. } else {
  811. out |= rd | wr | vol;
  812. }
  813. return out;
  814. }
  815. static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
  816. {
  817. struct snd_kcontrol_new *kcontrol;
  818. int ret;
  819. if (!ctl || !ctl->name)
  820. return -EINVAL;
  821. kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
  822. if (!kcontrol)
  823. return -ENOMEM;
  824. kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  825. kcontrol->name = ctl->name;
  826. kcontrol->info = wm_coeff_info;
  827. kcontrol->get = wm_coeff_get;
  828. kcontrol->put = wm_coeff_put;
  829. kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  830. kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
  831. kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
  832. ctl->bytes_ext.max = ctl->len;
  833. ctl->bytes_ext.get = wm_coeff_tlv_get;
  834. ctl->bytes_ext.put = wm_coeff_tlv_put;
  835. kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
  836. ret = snd_soc_add_card_controls(dsp->card, kcontrol, 1);
  837. if (ret < 0)
  838. goto err_kcontrol;
  839. kfree(kcontrol);
  840. ctl->kcontrol = snd_soc_card_get_kcontrol(dsp->card, ctl->name);
  841. return 0;
  842. err_kcontrol:
  843. kfree(kcontrol);
  844. return ret;
  845. }
  846. static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
  847. {
  848. struct wm_coeff_ctl *ctl;
  849. int ret;
  850. list_for_each_entry(ctl, &dsp->ctl_list, list) {
  851. if (!ctl->enabled || ctl->set)
  852. continue;
  853. if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
  854. continue;
  855. ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
  856. if (ret < 0)
  857. return ret;
  858. }
  859. return 0;
  860. }
  861. static int wm_coeff_sync_controls(struct wm_adsp *dsp)
  862. {
  863. struct wm_coeff_ctl *ctl;
  864. int ret;
  865. list_for_each_entry(ctl, &dsp->ctl_list, list) {
  866. if (!ctl->enabled)
  867. continue;
  868. if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
  869. ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
  870. if (ret < 0)
  871. return ret;
  872. }
  873. }
  874. return 0;
  875. }
  876. static void wm_adsp_ctl_work(struct work_struct *work)
  877. {
  878. struct wmfw_ctl_work *ctl_work = container_of(work,
  879. struct wmfw_ctl_work,
  880. work);
  881. wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
  882. kfree(ctl_work);
  883. }
  884. static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
  885. {
  886. kfree(ctl->cache);
  887. kfree(ctl->name);
  888. kfree(ctl);
  889. }
  890. static int wm_adsp_create_control(struct wm_adsp *dsp,
  891. const struct wm_adsp_alg_region *alg_region,
  892. unsigned int offset, unsigned int len,
  893. const char *subname, unsigned int subname_len,
  894. unsigned int flags)
  895. {
  896. struct wm_coeff_ctl *ctl;
  897. struct wmfw_ctl_work *ctl_work;
  898. char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
  899. char *region_name;
  900. int ret;
  901. if (flags & WMFW_CTL_FLAG_SYS)
  902. return 0;
  903. switch (alg_region->type) {
  904. case WMFW_ADSP1_PM:
  905. region_name = "PM";
  906. break;
  907. case WMFW_ADSP1_DM:
  908. region_name = "DM";
  909. break;
  910. case WMFW_ADSP2_XM:
  911. region_name = "XM";
  912. break;
  913. case WMFW_ADSP2_YM:
  914. region_name = "YM";
  915. break;
  916. case WMFW_ADSP1_ZM:
  917. region_name = "ZM";
  918. break;
  919. default:
  920. adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
  921. return -EINVAL;
  922. }
  923. switch (dsp->fw_ver) {
  924. case 0:
  925. case 1:
  926. snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "DSP%d %s %x",
  927. dsp->num, region_name, alg_region->alg);
  928. break;
  929. default:
  930. ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
  931. "DSP%d%c %.12s %x", dsp->num, *region_name,
  932. wm_adsp_fw_text[dsp->fw], alg_region->alg);
  933. /* Truncate the subname from the start if it is too long */
  934. if (subname) {
  935. int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
  936. int skip = 0;
  937. if (subname_len > avail)
  938. skip = subname_len - avail;
  939. snprintf(name + ret,
  940. SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
  941. subname_len - skip, subname + skip);
  942. }
  943. break;
  944. }
  945. list_for_each_entry(ctl, &dsp->ctl_list, list) {
  946. if (!strcmp(ctl->name, name)) {
  947. if (!ctl->enabled)
  948. ctl->enabled = 1;
  949. return 0;
  950. }
  951. }
  952. ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
  953. if (!ctl)
  954. return -ENOMEM;
  955. ctl->fw_name = wm_adsp_fw_text[dsp->fw];
  956. ctl->alg_region = *alg_region;
  957. ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
  958. if (!ctl->name) {
  959. ret = -ENOMEM;
  960. goto err_ctl;
  961. }
  962. ctl->enabled = 1;
  963. ctl->set = 0;
  964. ctl->ops.xget = wm_coeff_get;
  965. ctl->ops.xput = wm_coeff_put;
  966. ctl->dsp = dsp;
  967. ctl->flags = flags;
  968. ctl->offset = offset;
  969. ctl->len = len;
  970. ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
  971. if (!ctl->cache) {
  972. ret = -ENOMEM;
  973. goto err_ctl_name;
  974. }
  975. list_add(&ctl->list, &dsp->ctl_list);
  976. ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
  977. if (!ctl_work) {
  978. ret = -ENOMEM;
  979. goto err_ctl_cache;
  980. }
  981. ctl_work->dsp = dsp;
  982. ctl_work->ctl = ctl;
  983. INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
  984. schedule_work(&ctl_work->work);
  985. return 0;
  986. err_ctl_cache:
  987. kfree(ctl->cache);
  988. err_ctl_name:
  989. kfree(ctl->name);
  990. err_ctl:
  991. kfree(ctl);
  992. return ret;
  993. }
  994. struct wm_coeff_parsed_alg {
  995. int id;
  996. const u8 *name;
  997. int name_len;
  998. int ncoeff;
  999. };
  1000. struct wm_coeff_parsed_coeff {
  1001. int offset;
  1002. int mem_type;
  1003. const u8 *name;
  1004. int name_len;
  1005. int ctl_type;
  1006. int flags;
  1007. int len;
  1008. };
  1009. static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
  1010. {
  1011. int length;
  1012. switch (bytes) {
  1013. case 1:
  1014. length = **pos;
  1015. break;
  1016. case 2:
  1017. length = le16_to_cpu(*((__le16 *)*pos));
  1018. break;
  1019. default:
  1020. return 0;
  1021. }
  1022. if (str)
  1023. *str = *pos + bytes;
  1024. *pos += ((length + bytes) + 3) & ~0x03;
  1025. return length;
  1026. }
  1027. static int wm_coeff_parse_int(int bytes, const u8 **pos)
  1028. {
  1029. int val = 0;
  1030. switch (bytes) {
  1031. case 2:
  1032. val = le16_to_cpu(*((__le16 *)*pos));
  1033. break;
  1034. case 4:
  1035. val = le32_to_cpu(*((__le32 *)*pos));
  1036. break;
  1037. default:
  1038. break;
  1039. }
  1040. *pos += bytes;
  1041. return val;
  1042. }
  1043. static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
  1044. struct wm_coeff_parsed_alg *blk)
  1045. {
  1046. const struct wmfw_adsp_alg_data *raw;
  1047. switch (dsp->fw_ver) {
  1048. case 0:
  1049. case 1:
  1050. raw = (const struct wmfw_adsp_alg_data *)*data;
  1051. *data = raw->data;
  1052. blk->id = le32_to_cpu(raw->id);
  1053. blk->name = raw->name;
  1054. blk->name_len = strlen(raw->name);
  1055. blk->ncoeff = le32_to_cpu(raw->ncoeff);
  1056. break;
  1057. default:
  1058. blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
  1059. blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
  1060. &blk->name);
  1061. wm_coeff_parse_string(sizeof(u16), data, NULL);
  1062. blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
  1063. break;
  1064. }
  1065. adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
  1066. adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
  1067. adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
  1068. }
  1069. static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
  1070. struct wm_coeff_parsed_coeff *blk)
  1071. {
  1072. const struct wmfw_adsp_coeff_data *raw;
  1073. const u8 *tmp;
  1074. int length;
  1075. switch (dsp->fw_ver) {
  1076. case 0:
  1077. case 1:
  1078. raw = (const struct wmfw_adsp_coeff_data *)*data;
  1079. *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
  1080. blk->offset = le16_to_cpu(raw->hdr.offset);
  1081. blk->mem_type = le16_to_cpu(raw->hdr.type);
  1082. blk->name = raw->name;
  1083. blk->name_len = strlen(raw->name);
  1084. blk->ctl_type = le16_to_cpu(raw->ctl_type);
  1085. blk->flags = le16_to_cpu(raw->flags);
  1086. blk->len = le32_to_cpu(raw->len);
  1087. break;
  1088. default:
  1089. tmp = *data;
  1090. blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
  1091. blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
  1092. length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
  1093. blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
  1094. &blk->name);
  1095. wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
  1096. wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
  1097. blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
  1098. blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
  1099. blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
  1100. *data = *data + sizeof(raw->hdr) + length;
  1101. break;
  1102. }
  1103. adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
  1104. adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
  1105. adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
  1106. adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
  1107. adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
  1108. adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
  1109. }
  1110. static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
  1111. const struct wmfw_region *region)
  1112. {
  1113. struct wm_adsp_alg_region alg_region = {};
  1114. struct wm_coeff_parsed_alg alg_blk;
  1115. struct wm_coeff_parsed_coeff coeff_blk;
  1116. const u8 *data = region->data;
  1117. int i, ret;
  1118. wm_coeff_parse_alg(dsp, &data, &alg_blk);
  1119. for (i = 0; i < alg_blk.ncoeff; i++) {
  1120. wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
  1121. switch (coeff_blk.ctl_type) {
  1122. case SNDRV_CTL_ELEM_TYPE_BYTES:
  1123. break;
  1124. default:
  1125. adsp_err(dsp, "Unknown control type: %d\n",
  1126. coeff_blk.ctl_type);
  1127. return -EINVAL;
  1128. }
  1129. alg_region.type = coeff_blk.mem_type;
  1130. alg_region.alg = alg_blk.id;
  1131. ret = wm_adsp_create_control(dsp, &alg_region,
  1132. coeff_blk.offset,
  1133. coeff_blk.len,
  1134. coeff_blk.name,
  1135. coeff_blk.name_len,
  1136. coeff_blk.flags);
  1137. if (ret < 0)
  1138. adsp_err(dsp, "Failed to create control: %.*s, %d\n",
  1139. coeff_blk.name_len, coeff_blk.name, ret);
  1140. }
  1141. return 0;
  1142. }
  1143. static int wm_adsp_load(struct wm_adsp *dsp)
  1144. {
  1145. LIST_HEAD(buf_list);
  1146. const struct firmware *firmware;
  1147. struct regmap *regmap = dsp->regmap;
  1148. unsigned int pos = 0;
  1149. const struct wmfw_header *header;
  1150. const struct wmfw_adsp1_sizes *adsp1_sizes;
  1151. const struct wmfw_adsp2_sizes *adsp2_sizes;
  1152. const struct wmfw_footer *footer;
  1153. const struct wmfw_region *region;
  1154. const struct wm_adsp_region *mem;
  1155. const char *region_name;
  1156. char *file, *text = NULL;
  1157. struct wm_adsp_buf *buf;
  1158. unsigned int reg;
  1159. int regions = 0;
  1160. int ret, offset, type, sizes;
  1161. file = kzalloc(PAGE_SIZE, GFP_KERNEL);
  1162. if (file == NULL)
  1163. return -ENOMEM;
  1164. snprintf(file, PAGE_SIZE, "/*(DEBLOBBED)*/", dsp->part, dsp->num,
  1165. wm_adsp_fw[dsp->fw].file);
  1166. file[PAGE_SIZE - 1] = '\0';
  1167. ret = reject_firmware(&firmware, file, dsp->dev);
  1168. if (ret != 0) {
  1169. adsp_err(dsp, "Failed to request '%s'\n", file);
  1170. goto out;
  1171. }
  1172. ret = -EINVAL;
  1173. pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
  1174. if (pos >= firmware->size) {
  1175. adsp_err(dsp, "%s: file too short, %zu bytes\n",
  1176. file, firmware->size);
  1177. goto out_fw;
  1178. }
  1179. header = (void *)&firmware->data[0];
  1180. if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
  1181. adsp_err(dsp, "%s: invalid magic\n", file);
  1182. goto out_fw;
  1183. }
  1184. switch (header->ver) {
  1185. case 0:
  1186. adsp_warn(dsp, "%s: Depreciated file format %d\n",
  1187. file, header->ver);
  1188. break;
  1189. case 1:
  1190. case 2:
  1191. break;
  1192. default:
  1193. adsp_err(dsp, "%s: unknown file format %d\n",
  1194. file, header->ver);
  1195. goto out_fw;
  1196. }
  1197. adsp_info(dsp, "Firmware version: %d\n", header->ver);
  1198. dsp->fw_ver = header->ver;
  1199. if (header->core != dsp->type) {
  1200. adsp_err(dsp, "%s: invalid core %d != %d\n",
  1201. file, header->core, dsp->type);
  1202. goto out_fw;
  1203. }
  1204. switch (dsp->type) {
  1205. case WMFW_ADSP1:
  1206. pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
  1207. adsp1_sizes = (void *)&(header[1]);
  1208. footer = (void *)&(adsp1_sizes[1]);
  1209. sizes = sizeof(*adsp1_sizes);
  1210. adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
  1211. file, le32_to_cpu(adsp1_sizes->dm),
  1212. le32_to_cpu(adsp1_sizes->pm),
  1213. le32_to_cpu(adsp1_sizes->zm));
  1214. break;
  1215. case WMFW_ADSP2:
  1216. pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
  1217. adsp2_sizes = (void *)&(header[1]);
  1218. footer = (void *)&(adsp2_sizes[1]);
  1219. sizes = sizeof(*adsp2_sizes);
  1220. adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
  1221. file, le32_to_cpu(adsp2_sizes->xm),
  1222. le32_to_cpu(adsp2_sizes->ym),
  1223. le32_to_cpu(adsp2_sizes->pm),
  1224. le32_to_cpu(adsp2_sizes->zm));
  1225. break;
  1226. default:
  1227. WARN(1, "Unknown DSP type");
  1228. goto out_fw;
  1229. }
  1230. if (le32_to_cpu(header->len) != sizeof(*header) +
  1231. sizes + sizeof(*footer)) {
  1232. adsp_err(dsp, "%s: unexpected header length %d\n",
  1233. file, le32_to_cpu(header->len));
  1234. goto out_fw;
  1235. }
  1236. adsp_dbg(dsp, "%s: timestamp %llu\n", file,
  1237. le64_to_cpu(footer->timestamp));
  1238. while (pos < firmware->size &&
  1239. sizeof(*region) < firmware->size - pos) {
  1240. region = (void *)&(firmware->data[pos]);
  1241. region_name = "Unknown";
  1242. reg = 0;
  1243. text = NULL;
  1244. offset = le32_to_cpu(region->offset) & 0xffffff;
  1245. type = be32_to_cpu(region->type) & 0xff;
  1246. mem = wm_adsp_find_region(dsp, type);
  1247. switch (type) {
  1248. case WMFW_NAME_TEXT:
  1249. region_name = "Firmware name";
  1250. text = kzalloc(le32_to_cpu(region->len) + 1,
  1251. GFP_KERNEL);
  1252. break;
  1253. case WMFW_ALGORITHM_DATA:
  1254. region_name = "Algorithm";
  1255. ret = wm_adsp_parse_coeff(dsp, region);
  1256. if (ret != 0)
  1257. goto out_fw;
  1258. break;
  1259. case WMFW_INFO_TEXT:
  1260. region_name = "Information";
  1261. text = kzalloc(le32_to_cpu(region->len) + 1,
  1262. GFP_KERNEL);
  1263. break;
  1264. case WMFW_ABSOLUTE:
  1265. region_name = "Absolute";
  1266. reg = offset;
  1267. break;
  1268. case WMFW_ADSP1_PM:
  1269. region_name = "PM";
  1270. reg = wm_adsp_region_to_reg(mem, offset);
  1271. break;
  1272. case WMFW_ADSP1_DM:
  1273. region_name = "DM";
  1274. reg = wm_adsp_region_to_reg(mem, offset);
  1275. break;
  1276. case WMFW_ADSP2_XM:
  1277. region_name = "XM";
  1278. reg = wm_adsp_region_to_reg(mem, offset);
  1279. break;
  1280. case WMFW_ADSP2_YM:
  1281. region_name = "YM";
  1282. reg = wm_adsp_region_to_reg(mem, offset);
  1283. break;
  1284. case WMFW_ADSP1_ZM:
  1285. region_name = "ZM";
  1286. reg = wm_adsp_region_to_reg(mem, offset);
  1287. break;
  1288. default:
  1289. adsp_warn(dsp,
  1290. "%s.%d: Unknown region type %x at %d(%x)\n",
  1291. file, regions, type, pos, pos);
  1292. break;
  1293. }
  1294. adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
  1295. regions, le32_to_cpu(region->len), offset,
  1296. region_name);
  1297. if (le32_to_cpu(region->len) >
  1298. firmware->size - pos - sizeof(*region)) {
  1299. adsp_err(dsp,
  1300. "%s.%d: %s region len %d bytes exceeds file length %zu\n",
  1301. file, regions, region_name,
  1302. le32_to_cpu(region->len), firmware->size);
  1303. ret = -EINVAL;
  1304. goto out_fw;
  1305. }
  1306. if (text) {
  1307. memcpy(text, region->data, le32_to_cpu(region->len));
  1308. adsp_info(dsp, "%s: %s\n", file, text);
  1309. kfree(text);
  1310. text = NULL;
  1311. }
  1312. if (reg) {
  1313. buf = wm_adsp_buf_alloc(region->data,
  1314. le32_to_cpu(region->len),
  1315. &buf_list);
  1316. if (!buf) {
  1317. adsp_err(dsp, "Out of memory\n");
  1318. ret = -ENOMEM;
  1319. goto out_fw;
  1320. }
  1321. ret = regmap_raw_write_async(regmap, reg, buf->buf,
  1322. le32_to_cpu(region->len));
  1323. if (ret != 0) {
  1324. adsp_err(dsp,
  1325. "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
  1326. file, regions,
  1327. le32_to_cpu(region->len), offset,
  1328. region_name, ret);
  1329. goto out_fw;
  1330. }
  1331. }
  1332. pos += le32_to_cpu(region->len) + sizeof(*region);
  1333. regions++;
  1334. }
  1335. ret = regmap_async_complete(regmap);
  1336. if (ret != 0) {
  1337. adsp_err(dsp, "Failed to complete async write: %d\n", ret);
  1338. goto out_fw;
  1339. }
  1340. if (pos > firmware->size)
  1341. adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
  1342. file, regions, pos - firmware->size);
  1343. wm_adsp_debugfs_save_wmfwname(dsp, file);
  1344. out_fw:
  1345. regmap_async_complete(regmap);
  1346. wm_adsp_buf_free(&buf_list);
  1347. release_firmware(firmware);
  1348. kfree(text);
  1349. out:
  1350. kfree(file);
  1351. return ret;
  1352. }
  1353. static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
  1354. const struct wm_adsp_alg_region *alg_region)
  1355. {
  1356. struct wm_coeff_ctl *ctl;
  1357. list_for_each_entry(ctl, &dsp->ctl_list, list) {
  1358. if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
  1359. alg_region->alg == ctl->alg_region.alg &&
  1360. alg_region->type == ctl->alg_region.type) {
  1361. ctl->alg_region.base = alg_region->base;
  1362. }
  1363. }
  1364. }
  1365. static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
  1366. unsigned int pos, unsigned int len)
  1367. {
  1368. void *alg;
  1369. int ret;
  1370. __be32 val;
  1371. if (n_algs == 0) {
  1372. adsp_err(dsp, "No algorithms\n");
  1373. return ERR_PTR(-EINVAL);
  1374. }
  1375. if (n_algs > 1024) {
  1376. adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
  1377. return ERR_PTR(-EINVAL);
  1378. }
  1379. /* Read the terminator first to validate the length */
  1380. ret = regmap_raw_read(dsp->regmap, pos + len, &val, sizeof(val));
  1381. if (ret != 0) {
  1382. adsp_err(dsp, "Failed to read algorithm list end: %d\n",
  1383. ret);
  1384. return ERR_PTR(ret);
  1385. }
  1386. if (be32_to_cpu(val) != 0xbedead)
  1387. adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbeadead\n",
  1388. pos + len, be32_to_cpu(val));
  1389. alg = kzalloc(len * 2, GFP_KERNEL | GFP_DMA);
  1390. if (!alg)
  1391. return ERR_PTR(-ENOMEM);
  1392. ret = regmap_raw_read(dsp->regmap, pos, alg, len * 2);
  1393. if (ret != 0) {
  1394. adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
  1395. kfree(alg);
  1396. return ERR_PTR(ret);
  1397. }
  1398. return alg;
  1399. }
  1400. static struct wm_adsp_alg_region *
  1401. wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
  1402. {
  1403. struct wm_adsp_alg_region *alg_region;
  1404. list_for_each_entry(alg_region, &dsp->alg_regions, list) {
  1405. if (id == alg_region->alg && type == alg_region->type)
  1406. return alg_region;
  1407. }
  1408. return NULL;
  1409. }
  1410. static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
  1411. int type, __be32 id,
  1412. __be32 base)
  1413. {
  1414. struct wm_adsp_alg_region *alg_region;
  1415. alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
  1416. if (!alg_region)
  1417. return ERR_PTR(-ENOMEM);
  1418. alg_region->type = type;
  1419. alg_region->alg = be32_to_cpu(id);
  1420. alg_region->base = be32_to_cpu(base);
  1421. list_add_tail(&alg_region->list, &dsp->alg_regions);
  1422. if (dsp->fw_ver > 0)
  1423. wm_adsp_ctl_fixup_base(dsp, alg_region);
  1424. return alg_region;
  1425. }
  1426. static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
  1427. {
  1428. struct wm_adsp_alg_region *alg_region;
  1429. while (!list_empty(&dsp->alg_regions)) {
  1430. alg_region = list_first_entry(&dsp->alg_regions,
  1431. struct wm_adsp_alg_region,
  1432. list);
  1433. list_del(&alg_region->list);
  1434. kfree(alg_region);
  1435. }
  1436. }
  1437. static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
  1438. {
  1439. struct wmfw_adsp1_id_hdr adsp1_id;
  1440. struct wmfw_adsp1_alg_hdr *adsp1_alg;
  1441. struct wm_adsp_alg_region *alg_region;
  1442. const struct wm_adsp_region *mem;
  1443. unsigned int pos, len;
  1444. size_t n_algs;
  1445. int i, ret;
  1446. mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
  1447. if (WARN_ON(!mem))
  1448. return -EINVAL;
  1449. ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
  1450. sizeof(adsp1_id));
  1451. if (ret != 0) {
  1452. adsp_err(dsp, "Failed to read algorithm info: %d\n",
  1453. ret);
  1454. return ret;
  1455. }
  1456. n_algs = be32_to_cpu(adsp1_id.n_algs);
  1457. dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
  1458. adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
  1459. dsp->fw_id,
  1460. (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
  1461. (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
  1462. be32_to_cpu(adsp1_id.fw.ver) & 0xff,
  1463. n_algs);
  1464. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
  1465. adsp1_id.fw.id, adsp1_id.zm);
  1466. if (IS_ERR(alg_region))
  1467. return PTR_ERR(alg_region);
  1468. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
  1469. adsp1_id.fw.id, adsp1_id.dm);
  1470. if (IS_ERR(alg_region))
  1471. return PTR_ERR(alg_region);
  1472. pos = sizeof(adsp1_id) / 2;
  1473. len = (sizeof(*adsp1_alg) * n_algs) / 2;
  1474. adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
  1475. if (IS_ERR(adsp1_alg))
  1476. return PTR_ERR(adsp1_alg);
  1477. for (i = 0; i < n_algs; i++) {
  1478. adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
  1479. i, be32_to_cpu(adsp1_alg[i].alg.id),
  1480. (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
  1481. (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
  1482. be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
  1483. be32_to_cpu(adsp1_alg[i].dm),
  1484. be32_to_cpu(adsp1_alg[i].zm));
  1485. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
  1486. adsp1_alg[i].alg.id,
  1487. adsp1_alg[i].dm);
  1488. if (IS_ERR(alg_region)) {
  1489. ret = PTR_ERR(alg_region);
  1490. goto out;
  1491. }
  1492. if (dsp->fw_ver == 0) {
  1493. if (i + 1 < n_algs) {
  1494. len = be32_to_cpu(adsp1_alg[i + 1].dm);
  1495. len -= be32_to_cpu(adsp1_alg[i].dm);
  1496. len *= 4;
  1497. wm_adsp_create_control(dsp, alg_region, 0,
  1498. len, NULL, 0, 0);
  1499. } else {
  1500. adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
  1501. be32_to_cpu(adsp1_alg[i].alg.id));
  1502. }
  1503. }
  1504. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
  1505. adsp1_alg[i].alg.id,
  1506. adsp1_alg[i].zm);
  1507. if (IS_ERR(alg_region)) {
  1508. ret = PTR_ERR(alg_region);
  1509. goto out;
  1510. }
  1511. if (dsp->fw_ver == 0) {
  1512. if (i + 1 < n_algs) {
  1513. len = be32_to_cpu(adsp1_alg[i + 1].zm);
  1514. len -= be32_to_cpu(adsp1_alg[i].zm);
  1515. len *= 4;
  1516. wm_adsp_create_control(dsp, alg_region, 0,
  1517. len, NULL, 0, 0);
  1518. } else {
  1519. adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
  1520. be32_to_cpu(adsp1_alg[i].alg.id));
  1521. }
  1522. }
  1523. }
  1524. out:
  1525. kfree(adsp1_alg);
  1526. return ret;
  1527. }
  1528. static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
  1529. {
  1530. struct wmfw_adsp2_id_hdr adsp2_id;
  1531. struct wmfw_adsp2_alg_hdr *adsp2_alg;
  1532. struct wm_adsp_alg_region *alg_region;
  1533. const struct wm_adsp_region *mem;
  1534. unsigned int pos, len;
  1535. size_t n_algs;
  1536. int i, ret;
  1537. mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
  1538. if (WARN_ON(!mem))
  1539. return -EINVAL;
  1540. ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
  1541. sizeof(adsp2_id));
  1542. if (ret != 0) {
  1543. adsp_err(dsp, "Failed to read algorithm info: %d\n",
  1544. ret);
  1545. return ret;
  1546. }
  1547. n_algs = be32_to_cpu(adsp2_id.n_algs);
  1548. dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
  1549. dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
  1550. adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
  1551. dsp->fw_id,
  1552. (dsp->fw_id_version & 0xff0000) >> 16,
  1553. (dsp->fw_id_version & 0xff00) >> 8,
  1554. dsp->fw_id_version & 0xff,
  1555. n_algs);
  1556. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
  1557. adsp2_id.fw.id, adsp2_id.xm);
  1558. if (IS_ERR(alg_region))
  1559. return PTR_ERR(alg_region);
  1560. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
  1561. adsp2_id.fw.id, adsp2_id.ym);
  1562. if (IS_ERR(alg_region))
  1563. return PTR_ERR(alg_region);
  1564. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
  1565. adsp2_id.fw.id, adsp2_id.zm);
  1566. if (IS_ERR(alg_region))
  1567. return PTR_ERR(alg_region);
  1568. pos = sizeof(adsp2_id) / 2;
  1569. len = (sizeof(*adsp2_alg) * n_algs) / 2;
  1570. adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem->base + pos, len);
  1571. if (IS_ERR(adsp2_alg))
  1572. return PTR_ERR(adsp2_alg);
  1573. for (i = 0; i < n_algs; i++) {
  1574. adsp_info(dsp,
  1575. "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
  1576. i, be32_to_cpu(adsp2_alg[i].alg.id),
  1577. (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
  1578. (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
  1579. be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
  1580. be32_to_cpu(adsp2_alg[i].xm),
  1581. be32_to_cpu(adsp2_alg[i].ym),
  1582. be32_to_cpu(adsp2_alg[i].zm));
  1583. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
  1584. adsp2_alg[i].alg.id,
  1585. adsp2_alg[i].xm);
  1586. if (IS_ERR(alg_region)) {
  1587. ret = PTR_ERR(alg_region);
  1588. goto out;
  1589. }
  1590. if (dsp->fw_ver == 0) {
  1591. if (i + 1 < n_algs) {
  1592. len = be32_to_cpu(adsp2_alg[i + 1].xm);
  1593. len -= be32_to_cpu(adsp2_alg[i].xm);
  1594. len *= 4;
  1595. wm_adsp_create_control(dsp, alg_region, 0,
  1596. len, NULL, 0, 0);
  1597. } else {
  1598. adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
  1599. be32_to_cpu(adsp2_alg[i].alg.id));
  1600. }
  1601. }
  1602. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
  1603. adsp2_alg[i].alg.id,
  1604. adsp2_alg[i].ym);
  1605. if (IS_ERR(alg_region)) {
  1606. ret = PTR_ERR(alg_region);
  1607. goto out;
  1608. }
  1609. if (dsp->fw_ver == 0) {
  1610. if (i + 1 < n_algs) {
  1611. len = be32_to_cpu(adsp2_alg[i + 1].ym);
  1612. len -= be32_to_cpu(adsp2_alg[i].ym);
  1613. len *= 4;
  1614. wm_adsp_create_control(dsp, alg_region, 0,
  1615. len, NULL, 0, 0);
  1616. } else {
  1617. adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
  1618. be32_to_cpu(adsp2_alg[i].alg.id));
  1619. }
  1620. }
  1621. alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
  1622. adsp2_alg[i].alg.id,
  1623. adsp2_alg[i].zm);
  1624. if (IS_ERR(alg_region)) {
  1625. ret = PTR_ERR(alg_region);
  1626. goto out;
  1627. }
  1628. if (dsp->fw_ver == 0) {
  1629. if (i + 1 < n_algs) {
  1630. len = be32_to_cpu(adsp2_alg[i + 1].zm);
  1631. len -= be32_to_cpu(adsp2_alg[i].zm);
  1632. len *= 4;
  1633. wm_adsp_create_control(dsp, alg_region, 0,
  1634. len, NULL, 0, 0);
  1635. } else {
  1636. adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
  1637. be32_to_cpu(adsp2_alg[i].alg.id));
  1638. }
  1639. }
  1640. }
  1641. out:
  1642. kfree(adsp2_alg);
  1643. return ret;
  1644. }
  1645. static int wm_adsp_load_coeff(struct wm_adsp *dsp)
  1646. {
  1647. LIST_HEAD(buf_list);
  1648. struct regmap *regmap = dsp->regmap;
  1649. struct wmfw_coeff_hdr *hdr;
  1650. struct wmfw_coeff_item *blk;
  1651. const struct firmware *firmware;
  1652. const struct wm_adsp_region *mem;
  1653. struct wm_adsp_alg_region *alg_region;
  1654. const char *region_name;
  1655. int ret, pos, blocks, type, offset, reg;
  1656. char *file;
  1657. struct wm_adsp_buf *buf;
  1658. file = kzalloc(PAGE_SIZE, GFP_KERNEL);
  1659. if (file == NULL)
  1660. return -ENOMEM;
  1661. snprintf(file, PAGE_SIZE, "/*(DEBLOBBED)*/", dsp->part, dsp->num,
  1662. wm_adsp_fw[dsp->fw].file);
  1663. file[PAGE_SIZE - 1] = '\0';
  1664. ret = reject_firmware(&firmware, file, dsp->dev);
  1665. if (ret != 0) {
  1666. adsp_warn(dsp, "Failed to request '%s'\n", file);
  1667. ret = 0;
  1668. goto out;
  1669. }
  1670. ret = -EINVAL;
  1671. if (sizeof(*hdr) >= firmware->size) {
  1672. adsp_err(dsp, "%s: file too short, %zu bytes\n",
  1673. file, firmware->size);
  1674. goto out_fw;
  1675. }
  1676. hdr = (void *)&firmware->data[0];
  1677. if (memcmp(hdr->magic, "WMDR", 4) != 0) {
  1678. adsp_err(dsp, "%s: invalid magic\n", file);
  1679. goto out_fw;
  1680. }
  1681. switch (be32_to_cpu(hdr->rev) & 0xff) {
  1682. case 1:
  1683. break;
  1684. default:
  1685. adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
  1686. file, be32_to_cpu(hdr->rev) & 0xff);
  1687. ret = -EINVAL;
  1688. goto out_fw;
  1689. }
  1690. adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
  1691. (le32_to_cpu(hdr->ver) >> 16) & 0xff,
  1692. (le32_to_cpu(hdr->ver) >> 8) & 0xff,
  1693. le32_to_cpu(hdr->ver) & 0xff);
  1694. pos = le32_to_cpu(hdr->len);
  1695. blocks = 0;
  1696. while (pos < firmware->size &&
  1697. sizeof(*blk) < firmware->size - pos) {
  1698. blk = (void *)(&firmware->data[pos]);
  1699. type = le16_to_cpu(blk->type);
  1700. offset = le16_to_cpu(blk->offset);
  1701. adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
  1702. file, blocks, le32_to_cpu(blk->id),
  1703. (le32_to_cpu(blk->ver) >> 16) & 0xff,
  1704. (le32_to_cpu(blk->ver) >> 8) & 0xff,
  1705. le32_to_cpu(blk->ver) & 0xff);
  1706. adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
  1707. file, blocks, le32_to_cpu(blk->len), offset, type);
  1708. reg = 0;
  1709. region_name = "Unknown";
  1710. switch (type) {
  1711. case (WMFW_NAME_TEXT << 8):
  1712. case (WMFW_INFO_TEXT << 8):
  1713. break;
  1714. case (WMFW_ABSOLUTE << 8):
  1715. /*
  1716. * Old files may use this for global
  1717. * coefficients.
  1718. */
  1719. if (le32_to_cpu(blk->id) == dsp->fw_id &&
  1720. offset == 0) {
  1721. region_name = "global coefficients";
  1722. mem = wm_adsp_find_region(dsp, type);
  1723. if (!mem) {
  1724. adsp_err(dsp, "No ZM\n");
  1725. break;
  1726. }
  1727. reg = wm_adsp_region_to_reg(mem, 0);
  1728. } else {
  1729. region_name = "register";
  1730. reg = offset;
  1731. }
  1732. break;
  1733. case WMFW_ADSP1_DM:
  1734. case WMFW_ADSP1_ZM:
  1735. case WMFW_ADSP2_XM:
  1736. case WMFW_ADSP2_YM:
  1737. adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
  1738. file, blocks, le32_to_cpu(blk->len),
  1739. type, le32_to_cpu(blk->id));
  1740. mem = wm_adsp_find_region(dsp, type);
  1741. if (!mem) {
  1742. adsp_err(dsp, "No base for region %x\n", type);
  1743. break;
  1744. }
  1745. alg_region = wm_adsp_find_alg_region(dsp, type,
  1746. le32_to_cpu(blk->id));
  1747. if (alg_region) {
  1748. reg = alg_region->base;
  1749. reg = wm_adsp_region_to_reg(mem, reg);
  1750. reg += offset;
  1751. } else {
  1752. adsp_err(dsp, "No %x for algorithm %x\n",
  1753. type, le32_to_cpu(blk->id));
  1754. }
  1755. break;
  1756. default:
  1757. adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
  1758. file, blocks, type, pos);
  1759. break;
  1760. }
  1761. if (reg) {
  1762. if (le32_to_cpu(blk->len) >
  1763. firmware->size - pos - sizeof(*blk)) {
  1764. adsp_err(dsp,
  1765. "%s.%d: %s region len %d bytes exceeds file length %zu\n",
  1766. file, blocks, region_name,
  1767. le32_to_cpu(blk->len),
  1768. firmware->size);
  1769. ret = -EINVAL;
  1770. goto out_fw;
  1771. }
  1772. buf = wm_adsp_buf_alloc(blk->data,
  1773. le32_to_cpu(blk->len),
  1774. &buf_list);
  1775. if (!buf) {
  1776. adsp_err(dsp, "Out of memory\n");
  1777. ret = -ENOMEM;
  1778. goto out_fw;
  1779. }
  1780. adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
  1781. file, blocks, le32_to_cpu(blk->len),
  1782. reg);
  1783. ret = regmap_raw_write_async(regmap, reg, buf->buf,
  1784. le32_to_cpu(blk->len));
  1785. if (ret != 0) {
  1786. adsp_err(dsp,
  1787. "%s.%d: Failed to write to %x in %s: %d\n",
  1788. file, blocks, reg, region_name, ret);
  1789. }
  1790. }
  1791. pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
  1792. blocks++;
  1793. }
  1794. ret = regmap_async_complete(regmap);
  1795. if (ret != 0)
  1796. adsp_err(dsp, "Failed to complete async write: %d\n", ret);
  1797. if (pos > firmware->size)
  1798. adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
  1799. file, blocks, pos - firmware->size);
  1800. wm_adsp_debugfs_save_binname(dsp, file);
  1801. out_fw:
  1802. regmap_async_complete(regmap);
  1803. release_firmware(firmware);
  1804. wm_adsp_buf_free(&buf_list);
  1805. out:
  1806. kfree(file);
  1807. return ret;
  1808. }
  1809. int wm_adsp1_init(struct wm_adsp *dsp)
  1810. {
  1811. INIT_LIST_HEAD(&dsp->alg_regions);
  1812. mutex_init(&dsp->pwr_lock);
  1813. return 0;
  1814. }
  1815. EXPORT_SYMBOL_GPL(wm_adsp1_init);
  1816. int wm_adsp1_event(struct snd_soc_dapm_widget *w,
  1817. struct snd_kcontrol *kcontrol,
  1818. int event)
  1819. {
  1820. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1821. struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
  1822. struct wm_adsp *dsp = &dsps[w->shift];
  1823. struct wm_coeff_ctl *ctl;
  1824. int ret;
  1825. unsigned int val;
  1826. dsp->card = codec->component.card;
  1827. mutex_lock(&dsp->pwr_lock);
  1828. switch (event) {
  1829. case SND_SOC_DAPM_POST_PMU:
  1830. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
  1831. ADSP1_SYS_ENA, ADSP1_SYS_ENA);
  1832. /*
  1833. * For simplicity set the DSP clock rate to be the
  1834. * SYSCLK rate rather than making it configurable.
  1835. */
  1836. if (dsp->sysclk_reg) {
  1837. ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
  1838. if (ret != 0) {
  1839. adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
  1840. ret);
  1841. goto err_mutex;
  1842. }
  1843. val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
  1844. ret = regmap_update_bits(dsp->regmap,
  1845. dsp->base + ADSP1_CONTROL_31,
  1846. ADSP1_CLK_SEL_MASK, val);
  1847. if (ret != 0) {
  1848. adsp_err(dsp, "Failed to set clock rate: %d\n",
  1849. ret);
  1850. goto err_mutex;
  1851. }
  1852. }
  1853. ret = wm_adsp_load(dsp);
  1854. if (ret != 0)
  1855. goto err_ena;
  1856. ret = wm_adsp1_setup_algs(dsp);
  1857. if (ret != 0)
  1858. goto err_ena;
  1859. ret = wm_adsp_load_coeff(dsp);
  1860. if (ret != 0)
  1861. goto err_ena;
  1862. /* Initialize caches for enabled and unset controls */
  1863. ret = wm_coeff_init_control_caches(dsp);
  1864. if (ret != 0)
  1865. goto err_ena;
  1866. /* Sync set controls */
  1867. ret = wm_coeff_sync_controls(dsp);
  1868. if (ret != 0)
  1869. goto err_ena;
  1870. dsp->booted = true;
  1871. /* Start the core running */
  1872. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
  1873. ADSP1_CORE_ENA | ADSP1_START,
  1874. ADSP1_CORE_ENA | ADSP1_START);
  1875. dsp->running = true;
  1876. break;
  1877. case SND_SOC_DAPM_PRE_PMD:
  1878. dsp->running = false;
  1879. dsp->booted = false;
  1880. /* Halt the core */
  1881. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
  1882. ADSP1_CORE_ENA | ADSP1_START, 0);
  1883. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
  1884. ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
  1885. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
  1886. ADSP1_SYS_ENA, 0);
  1887. list_for_each_entry(ctl, &dsp->ctl_list, list)
  1888. ctl->enabled = 0;
  1889. wm_adsp_free_alg_regions(dsp);
  1890. break;
  1891. default:
  1892. break;
  1893. }
  1894. mutex_unlock(&dsp->pwr_lock);
  1895. return 0;
  1896. err_ena:
  1897. regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
  1898. ADSP1_SYS_ENA, 0);
  1899. err_mutex:
  1900. mutex_unlock(&dsp->pwr_lock);
  1901. return ret;
  1902. }
  1903. EXPORT_SYMBOL_GPL(wm_adsp1_event);
  1904. static int wm_adsp2_ena(struct wm_adsp *dsp)
  1905. {
  1906. unsigned int val;
  1907. int ret, count;
  1908. ret = regmap_update_bits_async(dsp->regmap, dsp->base + ADSP2_CONTROL,
  1909. ADSP2_SYS_ENA, ADSP2_SYS_ENA);
  1910. if (ret != 0)
  1911. return ret;
  1912. /* Wait for the RAM to start, should be near instantaneous */
  1913. for (count = 0; count < 10; ++count) {
  1914. ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
  1915. if (ret != 0)
  1916. return ret;
  1917. if (val & ADSP2_RAM_RDY)
  1918. break;
  1919. usleep_range(250, 500);
  1920. }
  1921. if (!(val & ADSP2_RAM_RDY)) {
  1922. adsp_err(dsp, "Failed to start DSP RAM\n");
  1923. return -EBUSY;
  1924. }
  1925. adsp_dbg(dsp, "RAM ready after %d polls\n", count);
  1926. return 0;
  1927. }
  1928. static void wm_adsp2_boot_work(struct work_struct *work)
  1929. {
  1930. struct wm_adsp *dsp = container_of(work,
  1931. struct wm_adsp,
  1932. boot_work);
  1933. int ret;
  1934. mutex_lock(&dsp->pwr_lock);
  1935. ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  1936. ADSP2_MEM_ENA, ADSP2_MEM_ENA);
  1937. if (ret != 0)
  1938. goto err_mutex;
  1939. ret = wm_adsp2_ena(dsp);
  1940. if (ret != 0)
  1941. goto err_mutex;
  1942. ret = wm_adsp_load(dsp);
  1943. if (ret != 0)
  1944. goto err_ena;
  1945. ret = wm_adsp2_setup_algs(dsp);
  1946. if (ret != 0)
  1947. goto err_ena;
  1948. ret = wm_adsp_load_coeff(dsp);
  1949. if (ret != 0)
  1950. goto err_ena;
  1951. /* Initialize caches for enabled and unset controls */
  1952. ret = wm_coeff_init_control_caches(dsp);
  1953. if (ret != 0)
  1954. goto err_ena;
  1955. dsp->booted = true;
  1956. /* Turn DSP back off until we are ready to run */
  1957. ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  1958. ADSP2_SYS_ENA, 0);
  1959. if (ret != 0)
  1960. goto err_ena;
  1961. mutex_unlock(&dsp->pwr_lock);
  1962. return;
  1963. err_ena:
  1964. regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  1965. ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
  1966. err_mutex:
  1967. mutex_unlock(&dsp->pwr_lock);
  1968. }
  1969. static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
  1970. {
  1971. int ret;
  1972. ret = regmap_update_bits_async(dsp->regmap,
  1973. dsp->base + ADSP2_CLOCKING,
  1974. ADSP2_CLK_SEL_MASK,
  1975. freq << ADSP2_CLK_SEL_SHIFT);
  1976. if (ret != 0)
  1977. adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
  1978. }
  1979. int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
  1980. struct snd_kcontrol *kcontrol, int event,
  1981. unsigned int freq)
  1982. {
  1983. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  1984. struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
  1985. struct wm_adsp *dsp = &dsps[w->shift];
  1986. struct wm_coeff_ctl *ctl;
  1987. dsp->card = codec->component.card;
  1988. switch (event) {
  1989. case SND_SOC_DAPM_PRE_PMU:
  1990. wm_adsp2_set_dspclk(dsp, freq);
  1991. queue_work(system_unbound_wq, &dsp->boot_work);
  1992. break;
  1993. case SND_SOC_DAPM_PRE_PMD:
  1994. wm_adsp_debugfs_clear(dsp);
  1995. dsp->fw_id = 0;
  1996. dsp->fw_id_version = 0;
  1997. dsp->booted = false;
  1998. regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  1999. ADSP2_MEM_ENA, 0);
  2000. list_for_each_entry(ctl, &dsp->ctl_list, list)
  2001. ctl->enabled = 0;
  2002. wm_adsp_free_alg_regions(dsp);
  2003. adsp_dbg(dsp, "Shutdown complete\n");
  2004. break;
  2005. default:
  2006. break;
  2007. }
  2008. return 0;
  2009. }
  2010. EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
  2011. int wm_adsp2_event(struct snd_soc_dapm_widget *w,
  2012. struct snd_kcontrol *kcontrol, int event)
  2013. {
  2014. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  2015. struct wm_adsp *dsps = snd_soc_codec_get_drvdata(codec);
  2016. struct wm_adsp *dsp = &dsps[w->shift];
  2017. int ret;
  2018. switch (event) {
  2019. case SND_SOC_DAPM_POST_PMU:
  2020. flush_work(&dsp->boot_work);
  2021. if (!dsp->booted)
  2022. return -EIO;
  2023. ret = wm_adsp2_ena(dsp);
  2024. if (ret != 0)
  2025. goto err;
  2026. /* Sync set controls */
  2027. ret = wm_coeff_sync_controls(dsp);
  2028. if (ret != 0)
  2029. goto err;
  2030. ret = regmap_update_bits(dsp->regmap,
  2031. dsp->base + ADSP2_CONTROL,
  2032. ADSP2_CORE_ENA | ADSP2_START,
  2033. ADSP2_CORE_ENA | ADSP2_START);
  2034. if (ret != 0)
  2035. goto err;
  2036. dsp->running = true;
  2037. mutex_lock(&dsp->pwr_lock);
  2038. if (wm_adsp_fw[dsp->fw].num_caps != 0)
  2039. ret = wm_adsp_buffer_init(dsp);
  2040. mutex_unlock(&dsp->pwr_lock);
  2041. break;
  2042. case SND_SOC_DAPM_PRE_PMD:
  2043. /* Log firmware state, it can be useful for analysis */
  2044. wm_adsp2_show_fw_status(dsp);
  2045. mutex_lock(&dsp->pwr_lock);
  2046. dsp->running = false;
  2047. regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  2048. ADSP2_CORE_ENA | ADSP2_START, 0);
  2049. /* Make sure DMAs are quiesced */
  2050. regmap_write(dsp->regmap, dsp->base + ADSP2_RDMA_CONFIG_1, 0);
  2051. regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_1, 0);
  2052. regmap_write(dsp->regmap, dsp->base + ADSP2_WDMA_CONFIG_2, 0);
  2053. regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  2054. ADSP2_SYS_ENA, 0);
  2055. if (wm_adsp_fw[dsp->fw].num_caps != 0)
  2056. wm_adsp_buffer_free(dsp);
  2057. mutex_unlock(&dsp->pwr_lock);
  2058. adsp_dbg(dsp, "Execution stopped\n");
  2059. break;
  2060. default:
  2061. break;
  2062. }
  2063. return 0;
  2064. err:
  2065. regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  2066. ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
  2067. return ret;
  2068. }
  2069. EXPORT_SYMBOL_GPL(wm_adsp2_event);
  2070. int wm_adsp2_codec_probe(struct wm_adsp *dsp, struct snd_soc_codec *codec)
  2071. {
  2072. wm_adsp2_init_debugfs(dsp, codec);
  2073. return snd_soc_add_codec_controls(codec,
  2074. &wm_adsp_fw_controls[dsp->num - 1],
  2075. 1);
  2076. }
  2077. EXPORT_SYMBOL_GPL(wm_adsp2_codec_probe);
  2078. int wm_adsp2_codec_remove(struct wm_adsp *dsp, struct snd_soc_codec *codec)
  2079. {
  2080. wm_adsp2_cleanup_debugfs(dsp);
  2081. return 0;
  2082. }
  2083. EXPORT_SYMBOL_GPL(wm_adsp2_codec_remove);
  2084. int wm_adsp2_init(struct wm_adsp *dsp)
  2085. {
  2086. int ret;
  2087. /*
  2088. * Disable the DSP memory by default when in reset for a small
  2089. * power saving.
  2090. */
  2091. ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
  2092. ADSP2_MEM_ENA, 0);
  2093. if (ret != 0) {
  2094. adsp_err(dsp, "Failed to clear memory retention: %d\n", ret);
  2095. return ret;
  2096. }
  2097. INIT_LIST_HEAD(&dsp->alg_regions);
  2098. INIT_LIST_HEAD(&dsp->ctl_list);
  2099. INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
  2100. mutex_init(&dsp->pwr_lock);
  2101. return 0;
  2102. }
  2103. EXPORT_SYMBOL_GPL(wm_adsp2_init);
  2104. void wm_adsp2_remove(struct wm_adsp *dsp)
  2105. {
  2106. struct wm_coeff_ctl *ctl;
  2107. while (!list_empty(&dsp->ctl_list)) {
  2108. ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
  2109. list);
  2110. list_del(&ctl->list);
  2111. wm_adsp_free_ctl_blk(ctl);
  2112. }
  2113. }
  2114. EXPORT_SYMBOL_GPL(wm_adsp2_remove);
  2115. static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
  2116. {
  2117. return compr->buf != NULL;
  2118. }
  2119. static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
  2120. {
  2121. /*
  2122. * Note this will be more complex once each DSP can support multiple
  2123. * streams
  2124. */
  2125. if (!compr->dsp->buffer)
  2126. return -EINVAL;
  2127. compr->buf = compr->dsp->buffer;
  2128. compr->buf->compr = compr;
  2129. return 0;
  2130. }
  2131. static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
  2132. {
  2133. if (!compr)
  2134. return;
  2135. /* Wake the poll so it can see buffer is no longer attached */
  2136. if (compr->stream)
  2137. snd_compr_fragment_elapsed(compr->stream);
  2138. if (wm_adsp_compr_attached(compr)) {
  2139. compr->buf->compr = NULL;
  2140. compr->buf = NULL;
  2141. }
  2142. }
  2143. int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
  2144. {
  2145. struct wm_adsp_compr *compr;
  2146. int ret = 0;
  2147. mutex_lock(&dsp->pwr_lock);
  2148. if (wm_adsp_fw[dsp->fw].num_caps == 0) {
  2149. adsp_err(dsp, "Firmware does not support compressed API\n");
  2150. ret = -ENXIO;
  2151. goto out;
  2152. }
  2153. if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
  2154. adsp_err(dsp, "Firmware does not support stream direction\n");
  2155. ret = -EINVAL;
  2156. goto out;
  2157. }
  2158. if (dsp->compr) {
  2159. /* It is expect this limitation will be removed in future */
  2160. adsp_err(dsp, "Only a single stream supported per DSP\n");
  2161. ret = -EBUSY;
  2162. goto out;
  2163. }
  2164. compr = kzalloc(sizeof(*compr), GFP_KERNEL);
  2165. if (!compr) {
  2166. ret = -ENOMEM;
  2167. goto out;
  2168. }
  2169. compr->dsp = dsp;
  2170. compr->stream = stream;
  2171. dsp->compr = compr;
  2172. stream->runtime->private_data = compr;
  2173. out:
  2174. mutex_unlock(&dsp->pwr_lock);
  2175. return ret;
  2176. }
  2177. EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
  2178. int wm_adsp_compr_free(struct snd_compr_stream *stream)
  2179. {
  2180. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2181. struct wm_adsp *dsp = compr->dsp;
  2182. mutex_lock(&dsp->pwr_lock);
  2183. wm_adsp_compr_detach(compr);
  2184. dsp->compr = NULL;
  2185. kfree(compr->raw_buf);
  2186. kfree(compr);
  2187. mutex_unlock(&dsp->pwr_lock);
  2188. return 0;
  2189. }
  2190. EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
  2191. static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
  2192. struct snd_compr_params *params)
  2193. {
  2194. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2195. struct wm_adsp *dsp = compr->dsp;
  2196. const struct wm_adsp_fw_caps *caps;
  2197. const struct snd_codec_desc *desc;
  2198. int i, j;
  2199. if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
  2200. params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
  2201. params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
  2202. params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
  2203. params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
  2204. adsp_err(dsp, "Invalid buffer fragsize=%d fragments=%d\n",
  2205. params->buffer.fragment_size,
  2206. params->buffer.fragments);
  2207. return -EINVAL;
  2208. }
  2209. for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
  2210. caps = &wm_adsp_fw[dsp->fw].caps[i];
  2211. desc = &caps->desc;
  2212. if (caps->id != params->codec.id)
  2213. continue;
  2214. if (stream->direction == SND_COMPRESS_PLAYBACK) {
  2215. if (desc->max_ch < params->codec.ch_out)
  2216. continue;
  2217. } else {
  2218. if (desc->max_ch < params->codec.ch_in)
  2219. continue;
  2220. }
  2221. if (!(desc->formats & (1 << params->codec.format)))
  2222. continue;
  2223. for (j = 0; j < desc->num_sample_rates; ++j)
  2224. if (desc->sample_rates[j] == params->codec.sample_rate)
  2225. return 0;
  2226. }
  2227. adsp_err(dsp, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
  2228. params->codec.id, params->codec.ch_in, params->codec.ch_out,
  2229. params->codec.sample_rate, params->codec.format);
  2230. return -EINVAL;
  2231. }
  2232. static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
  2233. {
  2234. return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
  2235. }
  2236. int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
  2237. struct snd_compr_params *params)
  2238. {
  2239. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2240. unsigned int size;
  2241. int ret;
  2242. ret = wm_adsp_compr_check_params(stream, params);
  2243. if (ret)
  2244. return ret;
  2245. compr->size = params->buffer;
  2246. adsp_dbg(compr->dsp, "fragment_size=%d fragments=%d\n",
  2247. compr->size.fragment_size, compr->size.fragments);
  2248. size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
  2249. compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
  2250. if (!compr->raw_buf)
  2251. return -ENOMEM;
  2252. compr->sample_rate = params->codec.sample_rate;
  2253. return 0;
  2254. }
  2255. EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
  2256. int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
  2257. struct snd_compr_caps *caps)
  2258. {
  2259. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2260. int fw = compr->dsp->fw;
  2261. int i;
  2262. if (wm_adsp_fw[fw].caps) {
  2263. for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
  2264. caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
  2265. caps->num_codecs = i;
  2266. caps->direction = wm_adsp_fw[fw].compr_direction;
  2267. caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
  2268. caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
  2269. caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
  2270. caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
  2271. }
  2272. return 0;
  2273. }
  2274. EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
  2275. static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
  2276. unsigned int mem_addr,
  2277. unsigned int num_words, u32 *data)
  2278. {
  2279. struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
  2280. unsigned int i, reg;
  2281. int ret;
  2282. if (!mem)
  2283. return -EINVAL;
  2284. reg = wm_adsp_region_to_reg(mem, mem_addr);
  2285. ret = regmap_raw_read(dsp->regmap, reg, data,
  2286. sizeof(*data) * num_words);
  2287. if (ret < 0)
  2288. return ret;
  2289. for (i = 0; i < num_words; ++i)
  2290. data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
  2291. return 0;
  2292. }
  2293. static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
  2294. unsigned int mem_addr, u32 *data)
  2295. {
  2296. return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
  2297. }
  2298. static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
  2299. unsigned int mem_addr, u32 data)
  2300. {
  2301. struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
  2302. unsigned int reg;
  2303. if (!mem)
  2304. return -EINVAL;
  2305. reg = wm_adsp_region_to_reg(mem, mem_addr);
  2306. data = cpu_to_be32(data & 0x00ffffffu);
  2307. return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
  2308. }
  2309. static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
  2310. unsigned int field_offset, u32 *data)
  2311. {
  2312. return wm_adsp_read_data_word(buf->dsp, WMFW_ADSP2_XM,
  2313. buf->host_buf_ptr + field_offset, data);
  2314. }
  2315. static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
  2316. unsigned int field_offset, u32 data)
  2317. {
  2318. return wm_adsp_write_data_word(buf->dsp, WMFW_ADSP2_XM,
  2319. buf->host_buf_ptr + field_offset, data);
  2320. }
  2321. static int wm_adsp_buffer_locate(struct wm_adsp_compr_buf *buf)
  2322. {
  2323. struct wm_adsp_alg_region *alg_region;
  2324. struct wm_adsp *dsp = buf->dsp;
  2325. u32 xmalg, addr, magic;
  2326. int i, ret;
  2327. alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
  2328. xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
  2329. addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
  2330. ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
  2331. if (ret < 0)
  2332. return ret;
  2333. if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
  2334. return -EINVAL;
  2335. addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
  2336. for (i = 0; i < 5; ++i) {
  2337. ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
  2338. &buf->host_buf_ptr);
  2339. if (ret < 0)
  2340. return ret;
  2341. if (buf->host_buf_ptr)
  2342. break;
  2343. usleep_range(1000, 2000);
  2344. }
  2345. if (!buf->host_buf_ptr)
  2346. return -EIO;
  2347. adsp_dbg(dsp, "host_buf_ptr=%x\n", buf->host_buf_ptr);
  2348. return 0;
  2349. }
  2350. static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
  2351. {
  2352. const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
  2353. struct wm_adsp_buffer_region *region;
  2354. u32 offset = 0;
  2355. int i, ret;
  2356. for (i = 0; i < caps->num_regions; ++i) {
  2357. region = &buf->regions[i];
  2358. region->offset = offset;
  2359. region->mem_type = caps->region_defs[i].mem_type;
  2360. ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
  2361. &region->base_addr);
  2362. if (ret < 0)
  2363. return ret;
  2364. ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
  2365. &offset);
  2366. if (ret < 0)
  2367. return ret;
  2368. region->cumulative_size = offset;
  2369. adsp_dbg(buf->dsp,
  2370. "region=%d type=%d base=%04x off=%04x size=%04x\n",
  2371. i, region->mem_type, region->base_addr,
  2372. region->offset, region->cumulative_size);
  2373. }
  2374. return 0;
  2375. }
  2376. static int wm_adsp_buffer_init(struct wm_adsp *dsp)
  2377. {
  2378. struct wm_adsp_compr_buf *buf;
  2379. int ret;
  2380. buf = kzalloc(sizeof(*buf), GFP_KERNEL);
  2381. if (!buf)
  2382. return -ENOMEM;
  2383. buf->dsp = dsp;
  2384. buf->read_index = -1;
  2385. buf->irq_count = 0xFFFFFFFF;
  2386. ret = wm_adsp_buffer_locate(buf);
  2387. if (ret < 0) {
  2388. adsp_err(dsp, "Failed to acquire host buffer: %d\n", ret);
  2389. goto err_buffer;
  2390. }
  2391. buf->regions = kcalloc(wm_adsp_fw[dsp->fw].caps->num_regions,
  2392. sizeof(*buf->regions), GFP_KERNEL);
  2393. if (!buf->regions) {
  2394. ret = -ENOMEM;
  2395. goto err_buffer;
  2396. }
  2397. ret = wm_adsp_buffer_populate(buf);
  2398. if (ret < 0) {
  2399. adsp_err(dsp, "Failed to populate host buffer: %d\n", ret);
  2400. goto err_regions;
  2401. }
  2402. dsp->buffer = buf;
  2403. return 0;
  2404. err_regions:
  2405. kfree(buf->regions);
  2406. err_buffer:
  2407. kfree(buf);
  2408. return ret;
  2409. }
  2410. static int wm_adsp_buffer_free(struct wm_adsp *dsp)
  2411. {
  2412. if (dsp->buffer) {
  2413. wm_adsp_compr_detach(dsp->buffer->compr);
  2414. kfree(dsp->buffer->regions);
  2415. kfree(dsp->buffer);
  2416. dsp->buffer = NULL;
  2417. }
  2418. return 0;
  2419. }
  2420. int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
  2421. {
  2422. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2423. struct wm_adsp *dsp = compr->dsp;
  2424. int ret = 0;
  2425. adsp_dbg(dsp, "Trigger: %d\n", cmd);
  2426. mutex_lock(&dsp->pwr_lock);
  2427. switch (cmd) {
  2428. case SNDRV_PCM_TRIGGER_START:
  2429. if (wm_adsp_compr_attached(compr))
  2430. break;
  2431. ret = wm_adsp_compr_attach(compr);
  2432. if (ret < 0) {
  2433. adsp_err(dsp, "Failed to link buffer and stream: %d\n",
  2434. ret);
  2435. break;
  2436. }
  2437. /* Trigger the IRQ at one fragment of data */
  2438. ret = wm_adsp_buffer_write(compr->buf,
  2439. HOST_BUFFER_FIELD(high_water_mark),
  2440. wm_adsp_compr_frag_words(compr));
  2441. if (ret < 0) {
  2442. adsp_err(dsp, "Failed to set high water mark: %d\n",
  2443. ret);
  2444. break;
  2445. }
  2446. break;
  2447. case SNDRV_PCM_TRIGGER_STOP:
  2448. break;
  2449. default:
  2450. ret = -EINVAL;
  2451. break;
  2452. }
  2453. mutex_unlock(&dsp->pwr_lock);
  2454. return ret;
  2455. }
  2456. EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
  2457. static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
  2458. {
  2459. int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
  2460. return buf->regions[last_region].cumulative_size;
  2461. }
  2462. static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
  2463. {
  2464. u32 next_read_index, next_write_index;
  2465. int write_index, read_index, avail;
  2466. int ret;
  2467. /* Only sync read index if we haven't already read a valid index */
  2468. if (buf->read_index < 0) {
  2469. ret = wm_adsp_buffer_read(buf,
  2470. HOST_BUFFER_FIELD(next_read_index),
  2471. &next_read_index);
  2472. if (ret < 0)
  2473. return ret;
  2474. read_index = sign_extend32(next_read_index, 23);
  2475. if (read_index < 0) {
  2476. adsp_dbg(buf->dsp, "Avail check on unstarted stream\n");
  2477. return 0;
  2478. }
  2479. buf->read_index = read_index;
  2480. }
  2481. ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
  2482. &next_write_index);
  2483. if (ret < 0)
  2484. return ret;
  2485. write_index = sign_extend32(next_write_index, 23);
  2486. avail = write_index - buf->read_index;
  2487. if (avail < 0)
  2488. avail += wm_adsp_buffer_size(buf);
  2489. adsp_dbg(buf->dsp, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
  2490. buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
  2491. buf->avail = avail;
  2492. return 0;
  2493. }
  2494. static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
  2495. {
  2496. int ret;
  2497. ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
  2498. if (ret < 0) {
  2499. adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
  2500. return ret;
  2501. }
  2502. if (buf->error != 0) {
  2503. adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
  2504. return -EIO;
  2505. }
  2506. return 0;
  2507. }
  2508. int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
  2509. {
  2510. struct wm_adsp_compr_buf *buf;
  2511. struct wm_adsp_compr *compr;
  2512. int ret = 0;
  2513. mutex_lock(&dsp->pwr_lock);
  2514. buf = dsp->buffer;
  2515. compr = dsp->compr;
  2516. if (!buf) {
  2517. ret = -ENODEV;
  2518. goto out;
  2519. }
  2520. adsp_dbg(dsp, "Handling buffer IRQ\n");
  2521. ret = wm_adsp_buffer_get_error(buf);
  2522. if (ret < 0)
  2523. goto out_notify; /* Wake poll to report error */
  2524. ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
  2525. &buf->irq_count);
  2526. if (ret < 0) {
  2527. adsp_err(dsp, "Failed to get irq_count: %d\n", ret);
  2528. goto out;
  2529. }
  2530. ret = wm_adsp_buffer_update_avail(buf);
  2531. if (ret < 0) {
  2532. adsp_err(dsp, "Error reading avail: %d\n", ret);
  2533. goto out;
  2534. }
  2535. if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
  2536. ret = WM_ADSP_COMPR_VOICE_TRIGGER;
  2537. out_notify:
  2538. if (compr && compr->stream)
  2539. snd_compr_fragment_elapsed(compr->stream);
  2540. out:
  2541. mutex_unlock(&dsp->pwr_lock);
  2542. return ret;
  2543. }
  2544. EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
  2545. static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
  2546. {
  2547. if (buf->irq_count & 0x01)
  2548. return 0;
  2549. adsp_dbg(buf->dsp, "Enable IRQ(0x%x) for next fragment\n",
  2550. buf->irq_count);
  2551. buf->irq_count |= 0x01;
  2552. return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
  2553. buf->irq_count);
  2554. }
  2555. int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
  2556. struct snd_compr_tstamp *tstamp)
  2557. {
  2558. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2559. struct wm_adsp *dsp = compr->dsp;
  2560. struct wm_adsp_compr_buf *buf;
  2561. int ret = 0;
  2562. adsp_dbg(dsp, "Pointer request\n");
  2563. mutex_lock(&dsp->pwr_lock);
  2564. buf = compr->buf;
  2565. if (!compr->buf || compr->buf->error) {
  2566. snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
  2567. ret = -EIO;
  2568. goto out;
  2569. }
  2570. if (buf->avail < wm_adsp_compr_frag_words(compr)) {
  2571. ret = wm_adsp_buffer_update_avail(buf);
  2572. if (ret < 0) {
  2573. adsp_err(dsp, "Error reading avail: %d\n", ret);
  2574. goto out;
  2575. }
  2576. /*
  2577. * If we really have less than 1 fragment available tell the
  2578. * DSP to inform us once a whole fragment is available.
  2579. */
  2580. if (buf->avail < wm_adsp_compr_frag_words(compr)) {
  2581. ret = wm_adsp_buffer_get_error(buf);
  2582. if (ret < 0) {
  2583. if (compr->buf->error)
  2584. snd_compr_stop_error(stream,
  2585. SNDRV_PCM_STATE_XRUN);
  2586. goto out;
  2587. }
  2588. ret = wm_adsp_buffer_reenable_irq(buf);
  2589. if (ret < 0) {
  2590. adsp_err(dsp,
  2591. "Failed to re-enable buffer IRQ: %d\n",
  2592. ret);
  2593. goto out;
  2594. }
  2595. }
  2596. }
  2597. tstamp->copied_total = compr->copied_total;
  2598. tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
  2599. tstamp->sampling_rate = compr->sample_rate;
  2600. out:
  2601. mutex_unlock(&dsp->pwr_lock);
  2602. return ret;
  2603. }
  2604. EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
  2605. static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
  2606. {
  2607. struct wm_adsp_compr_buf *buf = compr->buf;
  2608. u8 *pack_in = (u8 *)compr->raw_buf;
  2609. u8 *pack_out = (u8 *)compr->raw_buf;
  2610. unsigned int adsp_addr;
  2611. int mem_type, nwords, max_read;
  2612. int i, j, ret;
  2613. /* Calculate read parameters */
  2614. for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
  2615. if (buf->read_index < buf->regions[i].cumulative_size)
  2616. break;
  2617. if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
  2618. return -EINVAL;
  2619. mem_type = buf->regions[i].mem_type;
  2620. adsp_addr = buf->regions[i].base_addr +
  2621. (buf->read_index - buf->regions[i].offset);
  2622. max_read = wm_adsp_compr_frag_words(compr);
  2623. nwords = buf->regions[i].cumulative_size - buf->read_index;
  2624. if (nwords > target)
  2625. nwords = target;
  2626. if (nwords > buf->avail)
  2627. nwords = buf->avail;
  2628. if (nwords > max_read)
  2629. nwords = max_read;
  2630. if (!nwords)
  2631. return 0;
  2632. /* Read data from DSP */
  2633. ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
  2634. nwords, compr->raw_buf);
  2635. if (ret < 0)
  2636. return ret;
  2637. /* Remove the padding bytes from the data read from the DSP */
  2638. for (i = 0; i < nwords; i++) {
  2639. for (j = 0; j < WM_ADSP_DATA_WORD_SIZE; j++)
  2640. *pack_out++ = *pack_in++;
  2641. pack_in += sizeof(*(compr->raw_buf)) - WM_ADSP_DATA_WORD_SIZE;
  2642. }
  2643. /* update read index to account for words read */
  2644. buf->read_index += nwords;
  2645. if (buf->read_index == wm_adsp_buffer_size(buf))
  2646. buf->read_index = 0;
  2647. ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
  2648. buf->read_index);
  2649. if (ret < 0)
  2650. return ret;
  2651. /* update avail to account for words read */
  2652. buf->avail -= nwords;
  2653. return nwords;
  2654. }
  2655. static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
  2656. char __user *buf, size_t count)
  2657. {
  2658. struct wm_adsp *dsp = compr->dsp;
  2659. int ntotal = 0;
  2660. int nwords, nbytes;
  2661. adsp_dbg(dsp, "Requested read of %zu bytes\n", count);
  2662. if (!compr->buf || compr->buf->error) {
  2663. snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
  2664. return -EIO;
  2665. }
  2666. count /= WM_ADSP_DATA_WORD_SIZE;
  2667. do {
  2668. nwords = wm_adsp_buffer_capture_block(compr, count);
  2669. if (nwords < 0) {
  2670. adsp_err(dsp, "Failed to capture block: %d\n", nwords);
  2671. return nwords;
  2672. }
  2673. nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
  2674. adsp_dbg(dsp, "Read %d bytes\n", nbytes);
  2675. if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
  2676. adsp_err(dsp, "Failed to copy data to user: %d, %d\n",
  2677. ntotal, nbytes);
  2678. return -EFAULT;
  2679. }
  2680. count -= nwords;
  2681. ntotal += nbytes;
  2682. } while (nwords > 0 && count > 0);
  2683. compr->copied_total += ntotal;
  2684. return ntotal;
  2685. }
  2686. int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
  2687. size_t count)
  2688. {
  2689. struct wm_adsp_compr *compr = stream->runtime->private_data;
  2690. struct wm_adsp *dsp = compr->dsp;
  2691. int ret;
  2692. mutex_lock(&dsp->pwr_lock);
  2693. if (stream->direction == SND_COMPRESS_CAPTURE)
  2694. ret = wm_adsp_compr_read(compr, buf, count);
  2695. else
  2696. ret = -ENOTSUPP;
  2697. mutex_unlock(&dsp->pwr_lock);
  2698. return ret;
  2699. }
  2700. EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
  2701. MODULE_LICENSE("GPL v2");