wm8804.c 18 KB

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  1. /*
  2. * wm8804.c -- WM8804 S/PDIF transceiver driver
  3. *
  4. * Copyright 2010-11 Wolfson Microelectronics plc
  5. *
  6. * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/gpio/consumer.h>
  16. #include <linux/delay.h>
  17. #include <linux/pm.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/of_device.h>
  20. #include <linux/regulator/consumer.h>
  21. #include <linux/slab.h>
  22. #include <sound/core.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/initval.h>
  27. #include <sound/tlv.h>
  28. #include <sound/soc-dapm.h>
  29. #include "wm8804.h"
  30. #define WM8804_NUM_SUPPLIES 2
  31. static const char *wm8804_supply_names[WM8804_NUM_SUPPLIES] = {
  32. "PVDD",
  33. "DVDD"
  34. };
  35. static const struct reg_default wm8804_reg_defaults[] = {
  36. { 3, 0x21 }, /* R3 - PLL1 */
  37. { 4, 0xFD }, /* R4 - PLL2 */
  38. { 5, 0x36 }, /* R5 - PLL3 */
  39. { 6, 0x07 }, /* R6 - PLL4 */
  40. { 7, 0x16 }, /* R7 - PLL5 */
  41. { 8, 0x18 }, /* R8 - PLL6 */
  42. { 9, 0xFF }, /* R9 - SPDMODE */
  43. { 10, 0x00 }, /* R10 - INTMASK */
  44. { 18, 0x00 }, /* R18 - SPDTX1 */
  45. { 19, 0x00 }, /* R19 - SPDTX2 */
  46. { 20, 0x00 }, /* R20 - SPDTX3 */
  47. { 21, 0x71 }, /* R21 - SPDTX4 */
  48. { 22, 0x0B }, /* R22 - SPDTX5 */
  49. { 23, 0x70 }, /* R23 - GPO0 */
  50. { 24, 0x57 }, /* R24 - GPO1 */
  51. { 26, 0x42 }, /* R26 - GPO2 */
  52. { 27, 0x06 }, /* R27 - AIFTX */
  53. { 28, 0x06 }, /* R28 - AIFRX */
  54. { 29, 0x80 }, /* R29 - SPDRX1 */
  55. { 30, 0x07 }, /* R30 - PWRDN */
  56. };
  57. struct wm8804_priv {
  58. struct device *dev;
  59. struct regmap *regmap;
  60. struct regulator_bulk_data supplies[WM8804_NUM_SUPPLIES];
  61. struct notifier_block disable_nb[WM8804_NUM_SUPPLIES];
  62. int mclk_div;
  63. struct gpio_desc *reset;
  64. int aif_pwr;
  65. };
  66. static int txsrc_put(struct snd_kcontrol *kcontrol,
  67. struct snd_ctl_elem_value *ucontrol);
  68. static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
  69. struct snd_kcontrol *kcontrol, int event);
  70. /*
  71. * We can't use the same notifier block for more than one supply and
  72. * there's no way I can see to get from a callback to the caller
  73. * except container_of().
  74. */
  75. #define WM8804_REGULATOR_EVENT(n) \
  76. static int wm8804_regulator_event_##n(struct notifier_block *nb, \
  77. unsigned long event, void *data) \
  78. { \
  79. struct wm8804_priv *wm8804 = container_of(nb, struct wm8804_priv, \
  80. disable_nb[n]); \
  81. if (event & REGULATOR_EVENT_DISABLE) { \
  82. regcache_mark_dirty(wm8804->regmap); \
  83. } \
  84. return 0; \
  85. }
  86. WM8804_REGULATOR_EVENT(0)
  87. WM8804_REGULATOR_EVENT(1)
  88. static const char *txsrc_text[] = { "S/PDIF RX", "AIF" };
  89. static SOC_ENUM_SINGLE_DECL(txsrc, WM8804_SPDTX4, 6, txsrc_text);
  90. static const struct snd_kcontrol_new wm8804_tx_source_mux[] = {
  91. SOC_DAPM_ENUM_EXT("Input Source", txsrc,
  92. snd_soc_dapm_get_enum_double, txsrc_put),
  93. };
  94. static const struct snd_soc_dapm_widget wm8804_dapm_widgets[] = {
  95. SND_SOC_DAPM_OUTPUT("SPDIF Out"),
  96. SND_SOC_DAPM_INPUT("SPDIF In"),
  97. SND_SOC_DAPM_PGA("SPDIFTX", WM8804_PWRDN, 2, 1, NULL, 0),
  98. SND_SOC_DAPM_PGA("SPDIFRX", WM8804_PWRDN, 1, 1, NULL, 0),
  99. SND_SOC_DAPM_MUX("Tx Source", SND_SOC_NOPM, 6, 0, wm8804_tx_source_mux),
  100. SND_SOC_DAPM_AIF_OUT_E("AIFTX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
  101. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  102. SND_SOC_DAPM_AIF_IN_E("AIFRX", NULL, 0, SND_SOC_NOPM, 0, 0, wm8804_aif_event,
  103. SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
  104. };
  105. static const struct snd_soc_dapm_route wm8804_dapm_routes[] = {
  106. { "AIFRX", NULL, "Playback" },
  107. { "Tx Source", "AIF", "AIFRX" },
  108. { "SPDIFRX", NULL, "SPDIF In" },
  109. { "Tx Source", "S/PDIF RX", "SPDIFRX" },
  110. { "SPDIFTX", NULL, "Tx Source" },
  111. { "SPDIF Out", NULL, "SPDIFTX" },
  112. { "AIFTX", NULL, "SPDIFRX" },
  113. { "Capture", NULL, "AIFTX" },
  114. };
  115. static int wm8804_aif_event(struct snd_soc_dapm_widget *w,
  116. struct snd_kcontrol *kcontrol, int event)
  117. {
  118. struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
  119. struct wm8804_priv *wm8804 = snd_soc_codec_get_drvdata(codec);
  120. switch (event) {
  121. case SND_SOC_DAPM_POST_PMU:
  122. /* power up the aif */
  123. if (!wm8804->aif_pwr)
  124. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0x0);
  125. wm8804->aif_pwr++;
  126. break;
  127. case SND_SOC_DAPM_POST_PMD:
  128. /* power down only both paths are disabled */
  129. wm8804->aif_pwr--;
  130. if (!wm8804->aif_pwr)
  131. snd_soc_update_bits(codec, WM8804_PWRDN, 0x10, 0x10);
  132. break;
  133. }
  134. return 0;
  135. }
  136. static int txsrc_put(struct snd_kcontrol *kcontrol,
  137. struct snd_ctl_elem_value *ucontrol)
  138. {
  139. struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
  140. struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
  141. struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
  142. unsigned int val = ucontrol->value.enumerated.item[0] << e->shift_l;
  143. unsigned int mask = 1 << e->shift_l;
  144. unsigned int txpwr;
  145. if (val != 0 && val != mask)
  146. return -EINVAL;
  147. snd_soc_dapm_mutex_lock(dapm);
  148. if (snd_soc_test_bits(codec, e->reg, mask, val)) {
  149. /* save the current power state of the transmitter */
  150. txpwr = snd_soc_read(codec, WM8804_PWRDN) & 0x4;
  151. /* power down the transmitter */
  152. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, 0x4);
  153. /* set the tx source */
  154. snd_soc_update_bits(codec, e->reg, mask, val);
  155. /* restore the transmitter's configuration */
  156. snd_soc_update_bits(codec, WM8804_PWRDN, 0x4, txpwr);
  157. }
  158. snd_soc_dapm_mutex_unlock(dapm);
  159. return 0;
  160. }
  161. static bool wm8804_volatile(struct device *dev, unsigned int reg)
  162. {
  163. switch (reg) {
  164. case WM8804_RST_DEVID1:
  165. case WM8804_DEVID2:
  166. case WM8804_DEVREV:
  167. case WM8804_INTSTAT:
  168. case WM8804_SPDSTAT:
  169. case WM8804_RXCHAN1:
  170. case WM8804_RXCHAN2:
  171. case WM8804_RXCHAN3:
  172. case WM8804_RXCHAN4:
  173. case WM8804_RXCHAN5:
  174. return true;
  175. default:
  176. return false;
  177. }
  178. }
  179. static int wm8804_soft_reset(struct wm8804_priv *wm8804)
  180. {
  181. return regmap_write(wm8804->regmap, WM8804_RST_DEVID1, 0x0);
  182. }
  183. static int wm8804_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  184. {
  185. struct snd_soc_codec *codec;
  186. u16 format, master, bcp, lrp;
  187. codec = dai->codec;
  188. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  189. case SND_SOC_DAIFMT_I2S:
  190. format = 0x2;
  191. break;
  192. case SND_SOC_DAIFMT_RIGHT_J:
  193. format = 0x0;
  194. break;
  195. case SND_SOC_DAIFMT_LEFT_J:
  196. format = 0x1;
  197. break;
  198. case SND_SOC_DAIFMT_DSP_A:
  199. case SND_SOC_DAIFMT_DSP_B:
  200. format = 0x3;
  201. break;
  202. default:
  203. dev_err(dai->dev, "Unknown dai format\n");
  204. return -EINVAL;
  205. }
  206. /* set data format */
  207. snd_soc_update_bits(codec, WM8804_AIFTX, 0x3, format);
  208. snd_soc_update_bits(codec, WM8804_AIFRX, 0x3, format);
  209. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  210. case SND_SOC_DAIFMT_CBM_CFM:
  211. master = 1;
  212. break;
  213. case SND_SOC_DAIFMT_CBS_CFS:
  214. master = 0;
  215. break;
  216. default:
  217. dev_err(dai->dev, "Unknown master/slave configuration\n");
  218. return -EINVAL;
  219. }
  220. /* set master/slave mode */
  221. snd_soc_update_bits(codec, WM8804_AIFRX, 0x40, master << 6);
  222. bcp = lrp = 0;
  223. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  224. case SND_SOC_DAIFMT_NB_NF:
  225. break;
  226. case SND_SOC_DAIFMT_IB_IF:
  227. bcp = lrp = 1;
  228. break;
  229. case SND_SOC_DAIFMT_IB_NF:
  230. bcp = 1;
  231. break;
  232. case SND_SOC_DAIFMT_NB_IF:
  233. lrp = 1;
  234. break;
  235. default:
  236. dev_err(dai->dev, "Unknown polarity configuration\n");
  237. return -EINVAL;
  238. }
  239. /* set frame inversion */
  240. snd_soc_update_bits(codec, WM8804_AIFTX, 0x10 | 0x20,
  241. (bcp << 4) | (lrp << 5));
  242. snd_soc_update_bits(codec, WM8804_AIFRX, 0x10 | 0x20,
  243. (bcp << 4) | (lrp << 5));
  244. return 0;
  245. }
  246. static int wm8804_hw_params(struct snd_pcm_substream *substream,
  247. struct snd_pcm_hw_params *params,
  248. struct snd_soc_dai *dai)
  249. {
  250. struct snd_soc_codec *codec;
  251. u16 blen;
  252. codec = dai->codec;
  253. switch (params_width(params)) {
  254. case 16:
  255. blen = 0x0;
  256. break;
  257. case 20:
  258. blen = 0x1;
  259. break;
  260. case 24:
  261. blen = 0x2;
  262. break;
  263. default:
  264. dev_err(dai->dev, "Unsupported word length: %u\n",
  265. params_width(params));
  266. return -EINVAL;
  267. }
  268. /* set word length */
  269. snd_soc_update_bits(codec, WM8804_AIFTX, 0xc, blen << 2);
  270. snd_soc_update_bits(codec, WM8804_AIFRX, 0xc, blen << 2);
  271. return 0;
  272. }
  273. struct pll_div {
  274. u32 prescale:1;
  275. u32 mclkdiv:1;
  276. u32 freqmode:2;
  277. u32 n:4;
  278. u32 k:22;
  279. };
  280. /* PLL rate to output rate divisions */
  281. static struct {
  282. unsigned int div;
  283. unsigned int freqmode;
  284. unsigned int mclkdiv;
  285. } post_table[] = {
  286. { 2, 0, 0 },
  287. { 4, 0, 1 },
  288. { 4, 1, 0 },
  289. { 8, 1, 1 },
  290. { 8, 2, 0 },
  291. { 16, 2, 1 },
  292. { 12, 3, 0 },
  293. { 24, 3, 1 }
  294. };
  295. #define FIXED_PLL_SIZE ((1ULL << 22) * 10)
  296. static int pll_factors(struct pll_div *pll_div, unsigned int target,
  297. unsigned int source, unsigned int mclk_div)
  298. {
  299. u64 Kpart;
  300. unsigned long int K, Ndiv, Nmod, tmp;
  301. int i;
  302. /*
  303. * Scale the output frequency up; the PLL should run in the
  304. * region of 90-100MHz.
  305. */
  306. for (i = 0; i < ARRAY_SIZE(post_table); i++) {
  307. tmp = target * post_table[i].div;
  308. if ((tmp >= 90000000 && tmp <= 100000000) &&
  309. (mclk_div == post_table[i].mclkdiv)) {
  310. pll_div->freqmode = post_table[i].freqmode;
  311. pll_div->mclkdiv = post_table[i].mclkdiv;
  312. target *= post_table[i].div;
  313. break;
  314. }
  315. }
  316. if (i == ARRAY_SIZE(post_table)) {
  317. pr_err("%s: Unable to scale output frequency: %uHz\n",
  318. __func__, target);
  319. return -EINVAL;
  320. }
  321. pll_div->prescale = 0;
  322. Ndiv = target / source;
  323. if (Ndiv < 5) {
  324. source >>= 1;
  325. pll_div->prescale = 1;
  326. Ndiv = target / source;
  327. }
  328. if (Ndiv < 5 || Ndiv > 13) {
  329. pr_err("%s: WM8804 N value is not within the recommended range: %lu\n",
  330. __func__, Ndiv);
  331. return -EINVAL;
  332. }
  333. pll_div->n = Ndiv;
  334. Nmod = target % source;
  335. Kpart = FIXED_PLL_SIZE * (u64)Nmod;
  336. do_div(Kpart, source);
  337. K = Kpart & 0xffffffff;
  338. if ((K % 10) >= 5)
  339. K += 5;
  340. K /= 10;
  341. pll_div->k = K;
  342. return 0;
  343. }
  344. static int wm8804_set_pll(struct snd_soc_dai *dai, int pll_id,
  345. int source, unsigned int freq_in,
  346. unsigned int freq_out)
  347. {
  348. struct snd_soc_codec *codec = dai->codec;
  349. struct wm8804_priv *wm8804 = snd_soc_codec_get_drvdata(codec);
  350. bool change;
  351. if (!freq_in || !freq_out) {
  352. /* disable the PLL */
  353. regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
  354. 0x1, 0x1, &change);
  355. if (change)
  356. pm_runtime_put(wm8804->dev);
  357. } else {
  358. int ret;
  359. struct pll_div pll_div;
  360. ret = pll_factors(&pll_div, freq_out, freq_in,
  361. wm8804->mclk_div);
  362. if (ret)
  363. return ret;
  364. /* power down the PLL before reprogramming it */
  365. regmap_update_bits_check(wm8804->regmap, WM8804_PWRDN,
  366. 0x1, 0x1, &change);
  367. if (!change)
  368. pm_runtime_get_sync(wm8804->dev);
  369. /* set PLLN and PRESCALE */
  370. snd_soc_update_bits(codec, WM8804_PLL4, 0xf | 0x10,
  371. pll_div.n | (pll_div.prescale << 4));
  372. /* set mclkdiv and freqmode */
  373. snd_soc_update_bits(codec, WM8804_PLL5, 0x3 | 0x8,
  374. pll_div.freqmode | (pll_div.mclkdiv << 3));
  375. /* set PLLK */
  376. snd_soc_write(codec, WM8804_PLL1, pll_div.k & 0xff);
  377. snd_soc_write(codec, WM8804_PLL2, (pll_div.k >> 8) & 0xff);
  378. snd_soc_write(codec, WM8804_PLL3, pll_div.k >> 16);
  379. /* power up the PLL */
  380. snd_soc_update_bits(codec, WM8804_PWRDN, 0x1, 0);
  381. }
  382. return 0;
  383. }
  384. static int wm8804_set_sysclk(struct snd_soc_dai *dai,
  385. int clk_id, unsigned int freq, int dir)
  386. {
  387. struct snd_soc_codec *codec;
  388. codec = dai->codec;
  389. switch (clk_id) {
  390. case WM8804_TX_CLKSRC_MCLK:
  391. if ((freq >= 10000000 && freq <= 14400000)
  392. || (freq >= 16280000 && freq <= 27000000))
  393. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0x80);
  394. else {
  395. dev_err(dai->dev, "OSCCLOCK is not within the "
  396. "recommended range: %uHz\n", freq);
  397. return -EINVAL;
  398. }
  399. break;
  400. case WM8804_TX_CLKSRC_PLL:
  401. snd_soc_update_bits(codec, WM8804_PLL6, 0x80, 0);
  402. break;
  403. case WM8804_CLKOUT_SRC_CLK1:
  404. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0);
  405. break;
  406. case WM8804_CLKOUT_SRC_OSCCLK:
  407. snd_soc_update_bits(codec, WM8804_PLL6, 0x8, 0x8);
  408. break;
  409. default:
  410. dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
  411. return -EINVAL;
  412. }
  413. return 0;
  414. }
  415. static int wm8804_set_clkdiv(struct snd_soc_dai *dai,
  416. int div_id, int div)
  417. {
  418. struct snd_soc_codec *codec;
  419. struct wm8804_priv *wm8804;
  420. codec = dai->codec;
  421. switch (div_id) {
  422. case WM8804_CLKOUT_DIV:
  423. snd_soc_update_bits(codec, WM8804_PLL5, 0x30,
  424. (div & 0x3) << 4);
  425. break;
  426. case WM8804_MCLK_DIV:
  427. wm8804 = snd_soc_codec_get_drvdata(codec);
  428. wm8804->mclk_div = div;
  429. break;
  430. default:
  431. dev_err(dai->dev, "Unknown clock divider: %d\n", div_id);
  432. return -EINVAL;
  433. }
  434. return 0;
  435. }
  436. static const struct snd_soc_dai_ops wm8804_dai_ops = {
  437. .hw_params = wm8804_hw_params,
  438. .set_fmt = wm8804_set_fmt,
  439. .set_sysclk = wm8804_set_sysclk,
  440. .set_clkdiv = wm8804_set_clkdiv,
  441. .set_pll = wm8804_set_pll
  442. };
  443. #define WM8804_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
  444. SNDRV_PCM_FMTBIT_S24_LE)
  445. #define WM8804_RATES (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  446. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
  447. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | \
  448. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000)
  449. static struct snd_soc_dai_driver wm8804_dai = {
  450. .name = "wm8804-spdif",
  451. .playback = {
  452. .stream_name = "Playback",
  453. .channels_min = 2,
  454. .channels_max = 2,
  455. .rates = WM8804_RATES,
  456. .formats = WM8804_FORMATS,
  457. },
  458. .capture = {
  459. .stream_name = "Capture",
  460. .channels_min = 2,
  461. .channels_max = 2,
  462. .rates = WM8804_RATES,
  463. .formats = WM8804_FORMATS,
  464. },
  465. .ops = &wm8804_dai_ops,
  466. .symmetric_rates = 1
  467. };
  468. static const struct snd_soc_codec_driver soc_codec_dev_wm8804 = {
  469. .idle_bias_off = true,
  470. .component_driver = {
  471. .dapm_widgets = wm8804_dapm_widgets,
  472. .num_dapm_widgets = ARRAY_SIZE(wm8804_dapm_widgets),
  473. .dapm_routes = wm8804_dapm_routes,
  474. .num_dapm_routes = ARRAY_SIZE(wm8804_dapm_routes),
  475. },
  476. };
  477. const struct regmap_config wm8804_regmap_config = {
  478. .reg_bits = 8,
  479. .val_bits = 8,
  480. .max_register = WM8804_MAX_REGISTER,
  481. .volatile_reg = wm8804_volatile,
  482. .cache_type = REGCACHE_RBTREE,
  483. .reg_defaults = wm8804_reg_defaults,
  484. .num_reg_defaults = ARRAY_SIZE(wm8804_reg_defaults),
  485. };
  486. EXPORT_SYMBOL_GPL(wm8804_regmap_config);
  487. int wm8804_probe(struct device *dev, struct regmap *regmap)
  488. {
  489. struct wm8804_priv *wm8804;
  490. unsigned int id1, id2;
  491. int i, ret;
  492. wm8804 = devm_kzalloc(dev, sizeof(*wm8804), GFP_KERNEL);
  493. if (!wm8804)
  494. return -ENOMEM;
  495. dev_set_drvdata(dev, wm8804);
  496. wm8804->dev = dev;
  497. wm8804->regmap = regmap;
  498. wm8804->reset = devm_gpiod_get_optional(dev, "wlf,reset",
  499. GPIOD_OUT_LOW);
  500. if (IS_ERR(wm8804->reset)) {
  501. ret = PTR_ERR(wm8804->reset);
  502. dev_err(dev, "Failed to get reset line: %d\n", ret);
  503. return ret;
  504. }
  505. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++)
  506. wm8804->supplies[i].supply = wm8804_supply_names[i];
  507. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(wm8804->supplies),
  508. wm8804->supplies);
  509. if (ret) {
  510. dev_err(dev, "Failed to request supplies: %d\n", ret);
  511. return ret;
  512. }
  513. wm8804->disable_nb[0].notifier_call = wm8804_regulator_event_0;
  514. wm8804->disable_nb[1].notifier_call = wm8804_regulator_event_1;
  515. /* This should really be moved into the regulator core */
  516. for (i = 0; i < ARRAY_SIZE(wm8804->supplies); i++) {
  517. struct regulator *regulator = wm8804->supplies[i].consumer;
  518. ret = devm_regulator_register_notifier(regulator,
  519. &wm8804->disable_nb[i]);
  520. if (ret != 0) {
  521. dev_err(dev,
  522. "Failed to register regulator notifier: %d\n",
  523. ret);
  524. return ret;
  525. }
  526. }
  527. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  528. wm8804->supplies);
  529. if (ret) {
  530. dev_err(dev, "Failed to enable supplies: %d\n", ret);
  531. return ret;
  532. }
  533. if (wm8804->reset)
  534. gpiod_set_value_cansleep(wm8804->reset, 1);
  535. ret = regmap_read(regmap, WM8804_RST_DEVID1, &id1);
  536. if (ret < 0) {
  537. dev_err(dev, "Failed to read device ID: %d\n", ret);
  538. goto err_reg_enable;
  539. }
  540. ret = regmap_read(regmap, WM8804_DEVID2, &id2);
  541. if (ret < 0) {
  542. dev_err(dev, "Failed to read device ID: %d\n", ret);
  543. goto err_reg_enable;
  544. }
  545. id2 = (id2 << 8) | id1;
  546. if (id2 != 0x8805) {
  547. dev_err(dev, "Invalid device ID: %#x\n", id2);
  548. ret = -EINVAL;
  549. goto err_reg_enable;
  550. }
  551. ret = regmap_read(regmap, WM8804_DEVREV, &id1);
  552. if (ret < 0) {
  553. dev_err(dev, "Failed to read device revision: %d\n",
  554. ret);
  555. goto err_reg_enable;
  556. }
  557. dev_info(dev, "revision %c\n", id1 + 'A');
  558. if (!wm8804->reset) {
  559. ret = wm8804_soft_reset(wm8804);
  560. if (ret < 0) {
  561. dev_err(dev, "Failed to issue reset: %d\n", ret);
  562. goto err_reg_enable;
  563. }
  564. }
  565. ret = snd_soc_register_codec(dev, &soc_codec_dev_wm8804,
  566. &wm8804_dai, 1);
  567. if (ret < 0) {
  568. dev_err(dev, "Failed to register CODEC: %d\n", ret);
  569. goto err_reg_enable;
  570. }
  571. pm_runtime_set_active(dev);
  572. pm_runtime_enable(dev);
  573. pm_runtime_idle(dev);
  574. return 0;
  575. err_reg_enable:
  576. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies), wm8804->supplies);
  577. return ret;
  578. }
  579. EXPORT_SYMBOL_GPL(wm8804_probe);
  580. void wm8804_remove(struct device *dev)
  581. {
  582. pm_runtime_disable(dev);
  583. snd_soc_unregister_codec(dev);
  584. }
  585. EXPORT_SYMBOL_GPL(wm8804_remove);
  586. #if IS_ENABLED(CONFIG_PM)
  587. static int wm8804_runtime_resume(struct device *dev)
  588. {
  589. struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
  590. int ret;
  591. ret = regulator_bulk_enable(ARRAY_SIZE(wm8804->supplies),
  592. wm8804->supplies);
  593. if (ret) {
  594. dev_err(wm8804->dev, "Failed to enable supplies: %d\n", ret);
  595. return ret;
  596. }
  597. regcache_sync(wm8804->regmap);
  598. /* Power up OSCCLK */
  599. regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x0);
  600. return 0;
  601. }
  602. static int wm8804_runtime_suspend(struct device *dev)
  603. {
  604. struct wm8804_priv *wm8804 = dev_get_drvdata(dev);
  605. /* Power down OSCCLK */
  606. regmap_update_bits(wm8804->regmap, WM8804_PWRDN, 0x8, 0x8);
  607. regulator_bulk_disable(ARRAY_SIZE(wm8804->supplies),
  608. wm8804->supplies);
  609. return 0;
  610. }
  611. #endif
  612. const struct dev_pm_ops wm8804_pm = {
  613. SET_RUNTIME_PM_OPS(wm8804_runtime_suspend, wm8804_runtime_resume, NULL)
  614. };
  615. EXPORT_SYMBOL_GPL(wm8804_pm);
  616. MODULE_DESCRIPTION("ASoC WM8804 driver");
  617. MODULE_AUTHOR("Dimitris Papastamos <dp@opensource.wolfsonmicro.com>");
  618. MODULE_LICENSE("GPL");