adau1701.c 23 KB

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  1. /*
  2. * Driver for ADAU1701 SigmaDSP processor
  3. *
  4. * Copyright 2011 Analog Devices Inc.
  5. * Author: Lars-Peter Clausen <lars@metafoo.de>
  6. * based on an inital version by Cliff Cai <cliff.cai@analog.com>
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/init.h>
  12. #include <linux/i2c.h>
  13. #include <linux/delay.h>
  14. #include <linux/slab.h>
  15. #include <linux/of.h>
  16. #include <linux/of_gpio.h>
  17. #include <linux/of_device.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/regmap.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/pcm_params.h>
  23. #include <sound/soc.h>
  24. #include <asm/unaligned.h>
  25. #include "sigmadsp.h"
  26. #include "adau1701.h"
  27. #define ADAU1701_SAFELOAD_DATA(i) (0x0810 + (i))
  28. #define ADAU1701_SAFELOAD_ADDR(i) (0x0815 + (i))
  29. #define ADAU1701_DSPCTRL 0x081c
  30. #define ADAU1701_SEROCTL 0x081e
  31. #define ADAU1701_SERICTL 0x081f
  32. #define ADAU1701_AUXNPOW 0x0822
  33. #define ADAU1701_PINCONF_0 0x0820
  34. #define ADAU1701_PINCONF_1 0x0821
  35. #define ADAU1701_AUXNPOW 0x0822
  36. #define ADAU1701_OSCIPOW 0x0826
  37. #define ADAU1701_DACSET 0x0827
  38. #define ADAU1701_MAX_REGISTER 0x0828
  39. #define ADAU1701_DSPCTRL_CR (1 << 2)
  40. #define ADAU1701_DSPCTRL_DAM (1 << 3)
  41. #define ADAU1701_DSPCTRL_ADM (1 << 4)
  42. #define ADAU1701_DSPCTRL_IST (1 << 5)
  43. #define ADAU1701_DSPCTRL_SR_48 0x00
  44. #define ADAU1701_DSPCTRL_SR_96 0x01
  45. #define ADAU1701_DSPCTRL_SR_192 0x02
  46. #define ADAU1701_DSPCTRL_SR_MASK 0x03
  47. #define ADAU1701_SEROCTL_INV_LRCLK 0x2000
  48. #define ADAU1701_SEROCTL_INV_BCLK 0x1000
  49. #define ADAU1701_SEROCTL_MASTER 0x0800
  50. #define ADAU1701_SEROCTL_OBF16 0x0000
  51. #define ADAU1701_SEROCTL_OBF8 0x0200
  52. #define ADAU1701_SEROCTL_OBF4 0x0400
  53. #define ADAU1701_SEROCTL_OBF2 0x0600
  54. #define ADAU1701_SEROCTL_OBF_MASK 0x0600
  55. #define ADAU1701_SEROCTL_OLF1024 0x0000
  56. #define ADAU1701_SEROCTL_OLF512 0x0080
  57. #define ADAU1701_SEROCTL_OLF256 0x0100
  58. #define ADAU1701_SEROCTL_OLF_MASK 0x0180
  59. #define ADAU1701_SEROCTL_MSB_DEALY1 0x0000
  60. #define ADAU1701_SEROCTL_MSB_DEALY0 0x0004
  61. #define ADAU1701_SEROCTL_MSB_DEALY8 0x0008
  62. #define ADAU1701_SEROCTL_MSB_DEALY12 0x000c
  63. #define ADAU1701_SEROCTL_MSB_DEALY16 0x0010
  64. #define ADAU1701_SEROCTL_MSB_DEALY_MASK 0x001c
  65. #define ADAU1701_SEROCTL_WORD_LEN_24 0x0000
  66. #define ADAU1701_SEROCTL_WORD_LEN_20 0x0001
  67. #define ADAU1701_SEROCTL_WORD_LEN_16 0x0002
  68. #define ADAU1701_SEROCTL_WORD_LEN_MASK 0x0003
  69. #define ADAU1701_AUXNPOW_VBPD 0x40
  70. #define ADAU1701_AUXNPOW_VRPD 0x20
  71. #define ADAU1701_SERICTL_I2S 0
  72. #define ADAU1701_SERICTL_LEFTJ 1
  73. #define ADAU1701_SERICTL_TDM 2
  74. #define ADAU1701_SERICTL_RIGHTJ_24 3
  75. #define ADAU1701_SERICTL_RIGHTJ_20 4
  76. #define ADAU1701_SERICTL_RIGHTJ_18 5
  77. #define ADAU1701_SERICTL_RIGHTJ_16 6
  78. #define ADAU1701_SERICTL_MODE_MASK 7
  79. #define ADAU1701_SERICTL_INV_BCLK BIT(3)
  80. #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
  81. #define ADAU1701_OSCIPOW_OPD 0x04
  82. #define ADAU1701_DACSET_DACINIT 1
  83. #define ADAU1707_CLKDIV_UNSET (-1U)
  84. #define ADAU1701_FIRMWARE "/*(DEBLOBBED)*/"
  85. static const char * const supply_names[] = {
  86. "dvdd", "avdd"
  87. };
  88. struct adau1701 {
  89. int gpio_nreset;
  90. int gpio_pll_mode[2];
  91. unsigned int dai_fmt;
  92. unsigned int pll_clkdiv;
  93. unsigned int sysclk;
  94. struct regmap *regmap;
  95. struct i2c_client *client;
  96. u8 pin_config[12];
  97. struct sigmadsp *sigmadsp;
  98. struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  99. };
  100. static const struct snd_kcontrol_new adau1701_controls[] = {
  101. SOC_SINGLE("Master Capture Switch", ADAU1701_DSPCTRL, 4, 1, 0),
  102. };
  103. static const struct snd_soc_dapm_widget adau1701_dapm_widgets[] = {
  104. SND_SOC_DAPM_DAC("DAC0", "Playback", ADAU1701_AUXNPOW, 3, 1),
  105. SND_SOC_DAPM_DAC("DAC1", "Playback", ADAU1701_AUXNPOW, 2, 1),
  106. SND_SOC_DAPM_DAC("DAC2", "Playback", ADAU1701_AUXNPOW, 1, 1),
  107. SND_SOC_DAPM_DAC("DAC3", "Playback", ADAU1701_AUXNPOW, 0, 1),
  108. SND_SOC_DAPM_ADC("ADC", "Capture", ADAU1701_AUXNPOW, 7, 1),
  109. SND_SOC_DAPM_OUTPUT("OUT0"),
  110. SND_SOC_DAPM_OUTPUT("OUT1"),
  111. SND_SOC_DAPM_OUTPUT("OUT2"),
  112. SND_SOC_DAPM_OUTPUT("OUT3"),
  113. SND_SOC_DAPM_INPUT("IN0"),
  114. SND_SOC_DAPM_INPUT("IN1"),
  115. };
  116. static const struct snd_soc_dapm_route adau1701_dapm_routes[] = {
  117. { "OUT0", NULL, "DAC0" },
  118. { "OUT1", NULL, "DAC1" },
  119. { "OUT2", NULL, "DAC2" },
  120. { "OUT3", NULL, "DAC3" },
  121. { "ADC", NULL, "IN0" },
  122. { "ADC", NULL, "IN1" },
  123. };
  124. static unsigned int adau1701_register_size(struct device *dev,
  125. unsigned int reg)
  126. {
  127. switch (reg) {
  128. case ADAU1701_PINCONF_0:
  129. case ADAU1701_PINCONF_1:
  130. return 3;
  131. case ADAU1701_DSPCTRL:
  132. case ADAU1701_SEROCTL:
  133. case ADAU1701_AUXNPOW:
  134. case ADAU1701_OSCIPOW:
  135. case ADAU1701_DACSET:
  136. return 2;
  137. case ADAU1701_SERICTL:
  138. return 1;
  139. }
  140. dev_err(dev, "Unsupported register address: %d\n", reg);
  141. return 0;
  142. }
  143. static bool adau1701_volatile_reg(struct device *dev, unsigned int reg)
  144. {
  145. switch (reg) {
  146. case ADAU1701_DACSET:
  147. case ADAU1701_DSPCTRL:
  148. return true;
  149. default:
  150. return false;
  151. }
  152. }
  153. static int adau1701_reg_write(void *context, unsigned int reg,
  154. unsigned int value)
  155. {
  156. struct i2c_client *client = context;
  157. unsigned int i;
  158. unsigned int size;
  159. uint8_t buf[5];
  160. int ret;
  161. size = adau1701_register_size(&client->dev, reg);
  162. if (size == 0)
  163. return -EINVAL;
  164. buf[0] = reg >> 8;
  165. buf[1] = reg & 0xff;
  166. for (i = size + 1; i >= 2; --i) {
  167. buf[i] = value;
  168. value >>= 8;
  169. }
  170. ret = i2c_master_send(client, buf, size + 2);
  171. if (ret == size + 2)
  172. return 0;
  173. else if (ret < 0)
  174. return ret;
  175. else
  176. return -EIO;
  177. }
  178. static int adau1701_reg_read(void *context, unsigned int reg,
  179. unsigned int *value)
  180. {
  181. int ret;
  182. unsigned int i;
  183. unsigned int size;
  184. uint8_t send_buf[2], recv_buf[3];
  185. struct i2c_client *client = context;
  186. struct i2c_msg msgs[2];
  187. size = adau1701_register_size(&client->dev, reg);
  188. if (size == 0)
  189. return -EINVAL;
  190. send_buf[0] = reg >> 8;
  191. send_buf[1] = reg & 0xff;
  192. msgs[0].addr = client->addr;
  193. msgs[0].len = sizeof(send_buf);
  194. msgs[0].buf = send_buf;
  195. msgs[0].flags = 0;
  196. msgs[1].addr = client->addr;
  197. msgs[1].len = size;
  198. msgs[1].buf = recv_buf;
  199. msgs[1].flags = I2C_M_RD;
  200. ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
  201. if (ret < 0)
  202. return ret;
  203. else if (ret != ARRAY_SIZE(msgs))
  204. return -EIO;
  205. *value = 0;
  206. for (i = 0; i < size; i++) {
  207. *value <<= 8;
  208. *value |= recv_buf[i];
  209. }
  210. return 0;
  211. }
  212. static int adau1701_safeload(struct sigmadsp *sigmadsp, unsigned int addr,
  213. const uint8_t bytes[], size_t len)
  214. {
  215. struct i2c_client *client = to_i2c_client(sigmadsp->dev);
  216. struct adau1701 *adau1701 = i2c_get_clientdata(client);
  217. unsigned int val;
  218. unsigned int i;
  219. uint8_t buf[10];
  220. int ret;
  221. ret = regmap_read(adau1701->regmap, ADAU1701_DSPCTRL, &val);
  222. if (ret)
  223. return ret;
  224. if (val & ADAU1701_DSPCTRL_IST)
  225. msleep(50);
  226. for (i = 0; i < len / 4; i++) {
  227. put_unaligned_le16(ADAU1701_SAFELOAD_DATA(i), buf);
  228. buf[2] = 0x00;
  229. memcpy(buf + 3, bytes + i * 4, 4);
  230. ret = i2c_master_send(client, buf, 7);
  231. if (ret < 0)
  232. return ret;
  233. else if (ret != 7)
  234. return -EIO;
  235. put_unaligned_le16(ADAU1701_SAFELOAD_ADDR(i), buf);
  236. put_unaligned_le16(addr + i, buf + 2);
  237. ret = i2c_master_send(client, buf, 4);
  238. if (ret < 0)
  239. return ret;
  240. else if (ret != 4)
  241. return -EIO;
  242. }
  243. return regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  244. ADAU1701_DSPCTRL_IST, ADAU1701_DSPCTRL_IST);
  245. }
  246. static const struct sigmadsp_ops adau1701_sigmadsp_ops = {
  247. .safeload = adau1701_safeload,
  248. };
  249. static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv,
  250. unsigned int rate)
  251. {
  252. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  253. int ret;
  254. sigmadsp_reset(adau1701->sigmadsp);
  255. if (clkdiv != ADAU1707_CLKDIV_UNSET &&
  256. gpio_is_valid(adau1701->gpio_pll_mode[0]) &&
  257. gpio_is_valid(adau1701->gpio_pll_mode[1])) {
  258. switch (clkdiv) {
  259. case 64:
  260. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  261. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  262. break;
  263. case 256:
  264. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0);
  265. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  266. break;
  267. case 384:
  268. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  269. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0);
  270. break;
  271. case 0: /* fallback */
  272. case 512:
  273. gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1);
  274. gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1);
  275. break;
  276. }
  277. }
  278. adau1701->pll_clkdiv = clkdiv;
  279. if (gpio_is_valid(adau1701->gpio_nreset)) {
  280. gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
  281. /* minimum reset time is 20ns */
  282. udelay(1);
  283. gpio_set_value_cansleep(adau1701->gpio_nreset, 1);
  284. /* power-up time may be as long as 85ms */
  285. mdelay(85);
  286. }
  287. /*
  288. * Postpone the firmware download to a point in time when we
  289. * know the correct PLL setup
  290. */
  291. if (clkdiv != ADAU1707_CLKDIV_UNSET) {
  292. ret = sigmadsp_setup(adau1701->sigmadsp, rate);
  293. if (ret) {
  294. dev_warn(codec->dev, "Failed to load firmware\n");
  295. return ret;
  296. }
  297. }
  298. regmap_write(adau1701->regmap, ADAU1701_DACSET, ADAU1701_DACSET_DACINIT);
  299. regmap_write(adau1701->regmap, ADAU1701_DSPCTRL, ADAU1701_DSPCTRL_CR);
  300. regcache_mark_dirty(adau1701->regmap);
  301. regcache_sync(adau1701->regmap);
  302. return 0;
  303. }
  304. static int adau1701_set_capture_pcm_format(struct snd_soc_codec *codec,
  305. struct snd_pcm_hw_params *params)
  306. {
  307. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  308. unsigned int mask = ADAU1701_SEROCTL_WORD_LEN_MASK;
  309. unsigned int val;
  310. switch (params_width(params)) {
  311. case 16:
  312. val = ADAU1701_SEROCTL_WORD_LEN_16;
  313. break;
  314. case 20:
  315. val = ADAU1701_SEROCTL_WORD_LEN_20;
  316. break;
  317. case 24:
  318. val = ADAU1701_SEROCTL_WORD_LEN_24;
  319. break;
  320. default:
  321. return -EINVAL;
  322. }
  323. if (adau1701->dai_fmt == SND_SOC_DAIFMT_RIGHT_J) {
  324. switch (params_width(params)) {
  325. case 16:
  326. val |= ADAU1701_SEROCTL_MSB_DEALY16;
  327. break;
  328. case 20:
  329. val |= ADAU1701_SEROCTL_MSB_DEALY12;
  330. break;
  331. case 24:
  332. val |= ADAU1701_SEROCTL_MSB_DEALY8;
  333. break;
  334. }
  335. mask |= ADAU1701_SEROCTL_MSB_DEALY_MASK;
  336. }
  337. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL, mask, val);
  338. return 0;
  339. }
  340. static int adau1701_set_playback_pcm_format(struct snd_soc_codec *codec,
  341. struct snd_pcm_hw_params *params)
  342. {
  343. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  344. unsigned int val;
  345. if (adau1701->dai_fmt != SND_SOC_DAIFMT_RIGHT_J)
  346. return 0;
  347. switch (params_width(params)) {
  348. case 16:
  349. val = ADAU1701_SERICTL_RIGHTJ_16;
  350. break;
  351. case 20:
  352. val = ADAU1701_SERICTL_RIGHTJ_20;
  353. break;
  354. case 24:
  355. val = ADAU1701_SERICTL_RIGHTJ_24;
  356. break;
  357. default:
  358. return -EINVAL;
  359. }
  360. regmap_update_bits(adau1701->regmap, ADAU1701_SERICTL,
  361. ADAU1701_SERICTL_MODE_MASK, val);
  362. return 0;
  363. }
  364. static int adau1701_hw_params(struct snd_pcm_substream *substream,
  365. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  366. {
  367. struct snd_soc_codec *codec = dai->codec;
  368. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  369. unsigned int clkdiv = adau1701->sysclk / params_rate(params);
  370. unsigned int val;
  371. int ret;
  372. /*
  373. * If the mclk/lrclk ratio changes, the chip needs updated PLL
  374. * mode GPIO settings, and a full reset cycle, including a new
  375. * firmware upload.
  376. */
  377. if (clkdiv != adau1701->pll_clkdiv) {
  378. ret = adau1701_reset(codec, clkdiv, params_rate(params));
  379. if (ret < 0)
  380. return ret;
  381. }
  382. switch (params_rate(params)) {
  383. case 192000:
  384. val = ADAU1701_DSPCTRL_SR_192;
  385. break;
  386. case 96000:
  387. val = ADAU1701_DSPCTRL_SR_96;
  388. break;
  389. case 48000:
  390. val = ADAU1701_DSPCTRL_SR_48;
  391. break;
  392. default:
  393. return -EINVAL;
  394. }
  395. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL,
  396. ADAU1701_DSPCTRL_SR_MASK, val);
  397. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  398. return adau1701_set_playback_pcm_format(codec, params);
  399. else
  400. return adau1701_set_capture_pcm_format(codec, params);
  401. }
  402. static int adau1701_set_dai_fmt(struct snd_soc_dai *codec_dai,
  403. unsigned int fmt)
  404. {
  405. struct snd_soc_codec *codec = codec_dai->codec;
  406. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  407. unsigned int serictl = 0x00, seroctl = 0x00;
  408. bool invert_lrclk;
  409. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  410. case SND_SOC_DAIFMT_CBM_CFM:
  411. /* master, 64-bits per sample, 1 frame per sample */
  412. seroctl |= ADAU1701_SEROCTL_MASTER | ADAU1701_SEROCTL_OBF16
  413. | ADAU1701_SEROCTL_OLF1024;
  414. break;
  415. case SND_SOC_DAIFMT_CBS_CFS:
  416. break;
  417. default:
  418. return -EINVAL;
  419. }
  420. /* clock inversion */
  421. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  422. case SND_SOC_DAIFMT_NB_NF:
  423. invert_lrclk = false;
  424. break;
  425. case SND_SOC_DAIFMT_NB_IF:
  426. invert_lrclk = true;
  427. break;
  428. case SND_SOC_DAIFMT_IB_NF:
  429. invert_lrclk = false;
  430. serictl |= ADAU1701_SERICTL_INV_BCLK;
  431. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  432. break;
  433. case SND_SOC_DAIFMT_IB_IF:
  434. invert_lrclk = true;
  435. serictl |= ADAU1701_SERICTL_INV_BCLK;
  436. seroctl |= ADAU1701_SEROCTL_INV_BCLK;
  437. break;
  438. default:
  439. return -EINVAL;
  440. }
  441. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  442. case SND_SOC_DAIFMT_I2S:
  443. break;
  444. case SND_SOC_DAIFMT_LEFT_J:
  445. serictl |= ADAU1701_SERICTL_LEFTJ;
  446. seroctl |= ADAU1701_SEROCTL_MSB_DEALY0;
  447. invert_lrclk = !invert_lrclk;
  448. break;
  449. case SND_SOC_DAIFMT_RIGHT_J:
  450. serictl |= ADAU1701_SERICTL_RIGHTJ_24;
  451. seroctl |= ADAU1701_SEROCTL_MSB_DEALY8;
  452. invert_lrclk = !invert_lrclk;
  453. break;
  454. default:
  455. return -EINVAL;
  456. }
  457. if (invert_lrclk) {
  458. seroctl |= ADAU1701_SEROCTL_INV_LRCLK;
  459. serictl |= ADAU1701_SERICTL_INV_LRCLK;
  460. }
  461. adau1701->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
  462. regmap_write(adau1701->regmap, ADAU1701_SERICTL, serictl);
  463. regmap_update_bits(adau1701->regmap, ADAU1701_SEROCTL,
  464. ~ADAU1701_SEROCTL_WORD_LEN_MASK, seroctl);
  465. return 0;
  466. }
  467. static int adau1701_set_bias_level(struct snd_soc_codec *codec,
  468. enum snd_soc_bias_level level)
  469. {
  470. unsigned int mask = ADAU1701_AUXNPOW_VBPD | ADAU1701_AUXNPOW_VRPD;
  471. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  472. switch (level) {
  473. case SND_SOC_BIAS_ON:
  474. break;
  475. case SND_SOC_BIAS_PREPARE:
  476. break;
  477. case SND_SOC_BIAS_STANDBY:
  478. /* Enable VREF and VREF buffer */
  479. regmap_update_bits(adau1701->regmap,
  480. ADAU1701_AUXNPOW, mask, 0x00);
  481. break;
  482. case SND_SOC_BIAS_OFF:
  483. /* Disable VREF and VREF buffer */
  484. regmap_update_bits(adau1701->regmap,
  485. ADAU1701_AUXNPOW, mask, mask);
  486. break;
  487. }
  488. return 0;
  489. }
  490. static int adau1701_digital_mute(struct snd_soc_dai *dai, int mute)
  491. {
  492. struct snd_soc_codec *codec = dai->codec;
  493. unsigned int mask = ADAU1701_DSPCTRL_DAM;
  494. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  495. unsigned int val;
  496. if (mute)
  497. val = 0;
  498. else
  499. val = mask;
  500. regmap_update_bits(adau1701->regmap, ADAU1701_DSPCTRL, mask, val);
  501. return 0;
  502. }
  503. static int adau1701_set_sysclk(struct snd_soc_codec *codec, int clk_id,
  504. int source, unsigned int freq, int dir)
  505. {
  506. unsigned int val;
  507. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  508. switch (clk_id) {
  509. case ADAU1701_CLK_SRC_OSC:
  510. val = 0x0;
  511. break;
  512. case ADAU1701_CLK_SRC_MCLK:
  513. val = ADAU1701_OSCIPOW_OPD;
  514. break;
  515. default:
  516. return -EINVAL;
  517. }
  518. regmap_update_bits(adau1701->regmap, ADAU1701_OSCIPOW,
  519. ADAU1701_OSCIPOW_OPD, val);
  520. adau1701->sysclk = freq;
  521. return 0;
  522. }
  523. static int adau1701_startup(struct snd_pcm_substream *substream,
  524. struct snd_soc_dai *dai)
  525. {
  526. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(dai->codec);
  527. return sigmadsp_restrict_params(adau1701->sigmadsp, substream);
  528. }
  529. #define ADAU1701_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000 | \
  530. SNDRV_PCM_RATE_192000)
  531. #define ADAU1701_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
  532. SNDRV_PCM_FMTBIT_S24_LE)
  533. static const struct snd_soc_dai_ops adau1701_dai_ops = {
  534. .set_fmt = adau1701_set_dai_fmt,
  535. .hw_params = adau1701_hw_params,
  536. .digital_mute = adau1701_digital_mute,
  537. .startup = adau1701_startup,
  538. };
  539. static struct snd_soc_dai_driver adau1701_dai = {
  540. .name = "adau1701",
  541. .playback = {
  542. .stream_name = "Playback",
  543. .channels_min = 2,
  544. .channels_max = 8,
  545. .rates = ADAU1701_RATES,
  546. .formats = ADAU1701_FORMATS,
  547. },
  548. .capture = {
  549. .stream_name = "Capture",
  550. .channels_min = 2,
  551. .channels_max = 8,
  552. .rates = ADAU1701_RATES,
  553. .formats = ADAU1701_FORMATS,
  554. },
  555. .ops = &adau1701_dai_ops,
  556. .symmetric_rates = 1,
  557. };
  558. #ifdef CONFIG_OF
  559. static const struct of_device_id adau1701_dt_ids[] = {
  560. { .compatible = "adi,adau1701", },
  561. { }
  562. };
  563. MODULE_DEVICE_TABLE(of, adau1701_dt_ids);
  564. #endif
  565. static int adau1701_probe(struct snd_soc_codec *codec)
  566. {
  567. int i, ret;
  568. unsigned int val;
  569. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  570. ret = sigmadsp_attach(adau1701->sigmadsp, &codec->component);
  571. if (ret)
  572. return ret;
  573. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  574. adau1701->supplies);
  575. if (ret < 0) {
  576. dev_err(codec->dev, "Failed to enable regulators: %d\n", ret);
  577. return ret;
  578. }
  579. /*
  580. * Let the pll_clkdiv variable default to something that won't happen
  581. * at runtime. That way, we can postpone the firmware download from
  582. * adau1701_reset() to a point in time when we know the correct PLL
  583. * mode parameters.
  584. */
  585. adau1701->pll_clkdiv = ADAU1707_CLKDIV_UNSET;
  586. /* initalize with pre-configured pll mode settings */
  587. ret = adau1701_reset(codec, adau1701->pll_clkdiv, 0);
  588. if (ret < 0)
  589. goto exit_regulators_disable;
  590. /* set up pin config */
  591. val = 0;
  592. for (i = 0; i < 6; i++)
  593. val |= adau1701->pin_config[i] << (i * 4);
  594. regmap_write(adau1701->regmap, ADAU1701_PINCONF_0, val);
  595. val = 0;
  596. for (i = 0; i < 6; i++)
  597. val |= adau1701->pin_config[i + 6] << (i * 4);
  598. regmap_write(adau1701->regmap, ADAU1701_PINCONF_1, val);
  599. return 0;
  600. exit_regulators_disable:
  601. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  602. return ret;
  603. }
  604. static int adau1701_remove(struct snd_soc_codec *codec)
  605. {
  606. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  607. if (gpio_is_valid(adau1701->gpio_nreset))
  608. gpio_set_value_cansleep(adau1701->gpio_nreset, 0);
  609. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  610. return 0;
  611. }
  612. #ifdef CONFIG_PM
  613. static int adau1701_suspend(struct snd_soc_codec *codec)
  614. {
  615. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  616. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies),
  617. adau1701->supplies);
  618. return 0;
  619. }
  620. static int adau1701_resume(struct snd_soc_codec *codec)
  621. {
  622. struct adau1701 *adau1701 = snd_soc_codec_get_drvdata(codec);
  623. int ret;
  624. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  625. adau1701->supplies);
  626. if (ret < 0) {
  627. dev_err(codec->dev, "Failed to enable regulators: %d\n", ret);
  628. return ret;
  629. }
  630. return adau1701_reset(codec, adau1701->pll_clkdiv, 0);
  631. }
  632. #else
  633. #define adau1701_resume NULL
  634. #define adau1701_suspend NULL
  635. #endif /* CONFIG_PM */
  636. static struct snd_soc_codec_driver adau1701_codec_drv = {
  637. .probe = adau1701_probe,
  638. .remove = adau1701_remove,
  639. .resume = adau1701_resume,
  640. .suspend = adau1701_suspend,
  641. .set_bias_level = adau1701_set_bias_level,
  642. .idle_bias_off = true,
  643. .component_driver = {
  644. .controls = adau1701_controls,
  645. .num_controls = ARRAY_SIZE(adau1701_controls),
  646. .dapm_widgets = adau1701_dapm_widgets,
  647. .num_dapm_widgets = ARRAY_SIZE(adau1701_dapm_widgets),
  648. .dapm_routes = adau1701_dapm_routes,
  649. .num_dapm_routes = ARRAY_SIZE(adau1701_dapm_routes),
  650. },
  651. .set_sysclk = adau1701_set_sysclk,
  652. };
  653. static const struct regmap_config adau1701_regmap = {
  654. .reg_bits = 16,
  655. .val_bits = 32,
  656. .max_register = ADAU1701_MAX_REGISTER,
  657. .cache_type = REGCACHE_RBTREE,
  658. .volatile_reg = adau1701_volatile_reg,
  659. .reg_write = adau1701_reg_write,
  660. .reg_read = adau1701_reg_read,
  661. };
  662. static int adau1701_i2c_probe(struct i2c_client *client,
  663. const struct i2c_device_id *id)
  664. {
  665. struct adau1701 *adau1701;
  666. struct device *dev = &client->dev;
  667. int gpio_nreset = -EINVAL;
  668. int gpio_pll_mode[2] = { -EINVAL, -EINVAL };
  669. int ret, i;
  670. adau1701 = devm_kzalloc(dev, sizeof(*adau1701), GFP_KERNEL);
  671. if (!adau1701)
  672. return -ENOMEM;
  673. for (i = 0; i < ARRAY_SIZE(supply_names); i++)
  674. adau1701->supplies[i].supply = supply_names[i];
  675. ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(adau1701->supplies),
  676. adau1701->supplies);
  677. if (ret < 0) {
  678. dev_err(dev, "Failed to get regulators: %d\n", ret);
  679. return ret;
  680. }
  681. ret = regulator_bulk_enable(ARRAY_SIZE(adau1701->supplies),
  682. adau1701->supplies);
  683. if (ret < 0) {
  684. dev_err(dev, "Failed to enable regulators: %d\n", ret);
  685. return ret;
  686. }
  687. adau1701->client = client;
  688. adau1701->regmap = devm_regmap_init(dev, NULL, client,
  689. &adau1701_regmap);
  690. if (IS_ERR(adau1701->regmap)) {
  691. ret = PTR_ERR(adau1701->regmap);
  692. goto exit_regulators_disable;
  693. }
  694. if (dev->of_node) {
  695. gpio_nreset = of_get_named_gpio(dev->of_node, "reset-gpio", 0);
  696. if (gpio_nreset < 0 && gpio_nreset != -ENOENT) {
  697. ret = gpio_nreset;
  698. goto exit_regulators_disable;
  699. }
  700. gpio_pll_mode[0] = of_get_named_gpio(dev->of_node,
  701. "adi,pll-mode-gpios", 0);
  702. if (gpio_pll_mode[0] < 0 && gpio_pll_mode[0] != -ENOENT) {
  703. ret = gpio_pll_mode[0];
  704. goto exit_regulators_disable;
  705. }
  706. gpio_pll_mode[1] = of_get_named_gpio(dev->of_node,
  707. "adi,pll-mode-gpios", 1);
  708. if (gpio_pll_mode[1] < 0 && gpio_pll_mode[1] != -ENOENT) {
  709. ret = gpio_pll_mode[1];
  710. goto exit_regulators_disable;
  711. }
  712. of_property_read_u32(dev->of_node, "adi,pll-clkdiv",
  713. &adau1701->pll_clkdiv);
  714. of_property_read_u8_array(dev->of_node, "adi,pin-config",
  715. adau1701->pin_config,
  716. ARRAY_SIZE(adau1701->pin_config));
  717. }
  718. if (gpio_is_valid(gpio_nreset)) {
  719. ret = devm_gpio_request_one(dev, gpio_nreset, GPIOF_OUT_INIT_LOW,
  720. "ADAU1701 Reset");
  721. if (ret < 0)
  722. goto exit_regulators_disable;
  723. }
  724. if (gpio_is_valid(gpio_pll_mode[0]) &&
  725. gpio_is_valid(gpio_pll_mode[1])) {
  726. ret = devm_gpio_request_one(dev, gpio_pll_mode[0],
  727. GPIOF_OUT_INIT_LOW,
  728. "ADAU1701 PLL mode 0");
  729. if (ret < 0)
  730. goto exit_regulators_disable;
  731. ret = devm_gpio_request_one(dev, gpio_pll_mode[1],
  732. GPIOF_OUT_INIT_LOW,
  733. "ADAU1701 PLL mode 1");
  734. if (ret < 0)
  735. goto exit_regulators_disable;
  736. }
  737. adau1701->gpio_nreset = gpio_nreset;
  738. adau1701->gpio_pll_mode[0] = gpio_pll_mode[0];
  739. adau1701->gpio_pll_mode[1] = gpio_pll_mode[1];
  740. i2c_set_clientdata(client, adau1701);
  741. adau1701->sigmadsp = devm_sigmadsp_init_i2c(client,
  742. &adau1701_sigmadsp_ops, ADAU1701_FIRMWARE);
  743. if (IS_ERR(adau1701->sigmadsp)) {
  744. ret = PTR_ERR(adau1701->sigmadsp);
  745. goto exit_regulators_disable;
  746. }
  747. ret = snd_soc_register_codec(&client->dev, &adau1701_codec_drv,
  748. &adau1701_dai, 1);
  749. exit_regulators_disable:
  750. regulator_bulk_disable(ARRAY_SIZE(adau1701->supplies), adau1701->supplies);
  751. return ret;
  752. }
  753. static int adau1701_i2c_remove(struct i2c_client *client)
  754. {
  755. snd_soc_unregister_codec(&client->dev);
  756. return 0;
  757. }
  758. static const struct i2c_device_id adau1701_i2c_id[] = {
  759. { "adau1401", 0 },
  760. { "adau1401a", 0 },
  761. { "adau1701", 0 },
  762. { "adau1702", 0 },
  763. { }
  764. };
  765. MODULE_DEVICE_TABLE(i2c, adau1701_i2c_id);
  766. static struct i2c_driver adau1701_i2c_driver = {
  767. .driver = {
  768. .name = "adau1701",
  769. .of_match_table = of_match_ptr(adau1701_dt_ids),
  770. },
  771. .probe = adau1701_i2c_probe,
  772. .remove = adau1701_i2c_remove,
  773. .id_table = adau1701_i2c_id,
  774. };
  775. module_i2c_driver(adau1701_i2c_driver);
  776. MODULE_DESCRIPTION("ASoC ADAU1701 SigmaDSP driver");
  777. MODULE_AUTHOR("Cliff Cai <cliff.cai@analog.com>");
  778. MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
  779. MODULE_LICENSE("GPL");