bf5xx-sport.c 28 KB

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  1. /*
  2. * File: bf5xx_sport.c
  3. * Based on:
  4. * Author: Roy Huang <roy.huang@analog.com>
  5. *
  6. * Created: Tue Sep 21 10:52:42 CEST 2004
  7. * Description:
  8. * Blackfin SPORT Driver
  9. *
  10. * Copyright 2004-2007 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/kernel.h>
  30. #include <linux/slab.h>
  31. #include <linux/delay.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/gpio.h>
  34. #include <linux/bug.h>
  35. #include <linux/module.h>
  36. #include <asm/portmux.h>
  37. #include <asm/dma.h>
  38. #include <asm/blackfin.h>
  39. #include <asm/cacheflush.h>
  40. #include "bf5xx-sport.h"
  41. /* delay between frame sync pulse and first data bit in multichannel mode */
  42. #define FRAME_DELAY (1<<12)
  43. /* note: multichannel is in units of 8 channels,
  44. * tdm_count is # channels NOT / 8 ! */
  45. int sport_set_multichannel(struct sport_device *sport,
  46. int tdm_count, u32 tx_mask, u32 rx_mask, int packed)
  47. {
  48. pr_debug("%s tdm_count=%d tx_mask:0x%08x rx_mask:0x%08x packed=%d\n",
  49. __func__, tdm_count, tx_mask, rx_mask, packed);
  50. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  51. return -EBUSY;
  52. if (tdm_count & 0x7)
  53. return -EINVAL;
  54. if (tdm_count > 32)
  55. return -EINVAL; /* Only support less than 32 channels now */
  56. if (tdm_count) {
  57. sport->regs->mcmc1 = ((tdm_count>>3)-1) << 12;
  58. sport->regs->mcmc2 = FRAME_DELAY | MCMEN | \
  59. (packed ? (MCDTXPE|MCDRXPE) : 0);
  60. sport->regs->mtcs0 = tx_mask;
  61. sport->regs->mrcs0 = rx_mask;
  62. sport->regs->mtcs1 = 0;
  63. sport->regs->mrcs1 = 0;
  64. sport->regs->mtcs2 = 0;
  65. sport->regs->mrcs2 = 0;
  66. sport->regs->mtcs3 = 0;
  67. sport->regs->mrcs3 = 0;
  68. } else {
  69. sport->regs->mcmc1 = 0;
  70. sport->regs->mcmc2 = 0;
  71. sport->regs->mtcs0 = 0;
  72. sport->regs->mrcs0 = 0;
  73. }
  74. sport->regs->mtcs1 = 0; sport->regs->mtcs2 = 0; sport->regs->mtcs3 = 0;
  75. sport->regs->mrcs1 = 0; sport->regs->mrcs2 = 0; sport->regs->mrcs3 = 0;
  76. SSYNC();
  77. return 0;
  78. }
  79. EXPORT_SYMBOL(sport_set_multichannel);
  80. int sport_config_rx(struct sport_device *sport, unsigned int rcr1,
  81. unsigned int rcr2, unsigned int clkdiv, unsigned int fsdiv)
  82. {
  83. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  84. return -EBUSY;
  85. sport->regs->rcr1 = rcr1;
  86. sport->regs->rcr2 = rcr2;
  87. sport->regs->rclkdiv = clkdiv;
  88. sport->regs->rfsdiv = fsdiv;
  89. SSYNC();
  90. return 0;
  91. }
  92. EXPORT_SYMBOL(sport_config_rx);
  93. int sport_config_tx(struct sport_device *sport, unsigned int tcr1,
  94. unsigned int tcr2, unsigned int clkdiv, unsigned int fsdiv)
  95. {
  96. if ((sport->regs->tcr1 & TSPEN) || (sport->regs->rcr1 & RSPEN))
  97. return -EBUSY;
  98. sport->regs->tcr1 = tcr1;
  99. sport->regs->tcr2 = tcr2;
  100. sport->regs->tclkdiv = clkdiv;
  101. sport->regs->tfsdiv = fsdiv;
  102. SSYNC();
  103. return 0;
  104. }
  105. EXPORT_SYMBOL(sport_config_tx);
  106. static void setup_desc(struct dmasg *desc, void *buf, int fragcount,
  107. size_t fragsize, unsigned int cfg,
  108. unsigned int x_count, unsigned int ycount, size_t wdsize)
  109. {
  110. int i;
  111. for (i = 0; i < fragcount; ++i) {
  112. desc[i].next_desc_addr = &(desc[i + 1]);
  113. desc[i].start_addr = (unsigned long)buf + i*fragsize;
  114. desc[i].cfg = cfg;
  115. desc[i].x_count = x_count;
  116. desc[i].x_modify = wdsize;
  117. desc[i].y_count = ycount;
  118. desc[i].y_modify = wdsize;
  119. }
  120. /* make circular */
  121. desc[fragcount-1].next_desc_addr = desc;
  122. pr_debug("setup desc: desc0=%p, next0=%p, desc1=%p,"
  123. "next1=%p\nx_count=%x,y_count=%x,addr=0x%lx,cfs=0x%x\n",
  124. desc, desc[0].next_desc_addr,
  125. desc+1, desc[1].next_desc_addr,
  126. desc[0].x_count, desc[0].y_count,
  127. desc[0].start_addr, desc[0].cfg);
  128. }
  129. static int sport_start(struct sport_device *sport)
  130. {
  131. enable_dma(sport->dma_rx_chan);
  132. enable_dma(sport->dma_tx_chan);
  133. sport->regs->rcr1 |= RSPEN;
  134. sport->regs->tcr1 |= TSPEN;
  135. SSYNC();
  136. return 0;
  137. }
  138. static int sport_stop(struct sport_device *sport)
  139. {
  140. sport->regs->tcr1 &= ~TSPEN;
  141. sport->regs->rcr1 &= ~RSPEN;
  142. SSYNC();
  143. disable_dma(sport->dma_rx_chan);
  144. disable_dma(sport->dma_tx_chan);
  145. return 0;
  146. }
  147. static inline int sport_hook_rx_dummy(struct sport_device *sport)
  148. {
  149. struct dmasg *desc, temp_desc;
  150. unsigned long flags;
  151. if (WARN_ON(!sport->dummy_rx_desc) ||
  152. WARN_ON(sport->curr_rx_desc == sport->dummy_rx_desc))
  153. return -EINVAL;
  154. /* Maybe the dummy buffer descriptor ring is damaged */
  155. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc + 1;
  156. local_irq_save(flags);
  157. desc = get_dma_next_desc_ptr(sport->dma_rx_chan);
  158. /* Copy the descriptor which will be damaged to backup */
  159. temp_desc = *desc;
  160. desc->x_count = sport->dummy_count / 2;
  161. desc->y_count = 0;
  162. desc->next_desc_addr = sport->dummy_rx_desc;
  163. local_irq_restore(flags);
  164. /* Waiting for dummy buffer descriptor is already hooked*/
  165. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  166. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  167. continue;
  168. sport->curr_rx_desc = sport->dummy_rx_desc;
  169. /* Restore the damaged descriptor */
  170. *desc = temp_desc;
  171. return 0;
  172. }
  173. static inline int sport_rx_dma_start(struct sport_device *sport, int dummy)
  174. {
  175. if (dummy) {
  176. sport->dummy_rx_desc->next_desc_addr = sport->dummy_rx_desc;
  177. sport->curr_rx_desc = sport->dummy_rx_desc;
  178. } else
  179. sport->curr_rx_desc = sport->dma_rx_desc;
  180. set_dma_next_desc_addr(sport->dma_rx_chan, sport->curr_rx_desc);
  181. set_dma_x_count(sport->dma_rx_chan, 0);
  182. set_dma_x_modify(sport->dma_rx_chan, 0);
  183. set_dma_config(sport->dma_rx_chan, (DMAFLOW_LARGE | NDSIZE_9 | \
  184. WDSIZE_32 | WNR));
  185. set_dma_curr_addr(sport->dma_rx_chan, sport->curr_rx_desc->start_addr);
  186. SSYNC();
  187. return 0;
  188. }
  189. static inline int sport_tx_dma_start(struct sport_device *sport, int dummy)
  190. {
  191. if (dummy) {
  192. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc;
  193. sport->curr_tx_desc = sport->dummy_tx_desc;
  194. } else
  195. sport->curr_tx_desc = sport->dma_tx_desc;
  196. set_dma_next_desc_addr(sport->dma_tx_chan, sport->curr_tx_desc);
  197. set_dma_x_count(sport->dma_tx_chan, 0);
  198. set_dma_x_modify(sport->dma_tx_chan, 0);
  199. set_dma_config(sport->dma_tx_chan,
  200. (DMAFLOW_LARGE | NDSIZE_9 | WDSIZE_32));
  201. set_dma_curr_addr(sport->dma_tx_chan, sport->curr_tx_desc->start_addr);
  202. SSYNC();
  203. return 0;
  204. }
  205. int sport_rx_start(struct sport_device *sport)
  206. {
  207. unsigned long flags;
  208. pr_debug("%s enter\n", __func__);
  209. if (sport->rx_run)
  210. return -EBUSY;
  211. if (sport->tx_run) {
  212. /* tx is running, rx is not running */
  213. if (WARN_ON(!sport->dma_rx_desc) ||
  214. WARN_ON(sport->curr_rx_desc != sport->dummy_rx_desc))
  215. return -EINVAL;
  216. local_irq_save(flags);
  217. while ((get_dma_curr_desc_ptr(sport->dma_rx_chan) -
  218. sizeof(struct dmasg)) != sport->dummy_rx_desc)
  219. continue;
  220. sport->dummy_rx_desc->next_desc_addr = sport->dma_rx_desc;
  221. local_irq_restore(flags);
  222. sport->curr_rx_desc = sport->dma_rx_desc;
  223. } else {
  224. sport_tx_dma_start(sport, 1);
  225. sport_rx_dma_start(sport, 0);
  226. sport_start(sport);
  227. }
  228. sport->rx_run = 1;
  229. return 0;
  230. }
  231. EXPORT_SYMBOL(sport_rx_start);
  232. int sport_rx_stop(struct sport_device *sport)
  233. {
  234. pr_debug("%s enter\n", __func__);
  235. if (!sport->rx_run)
  236. return 0;
  237. if (sport->tx_run) {
  238. /* TX dma is still running, hook the dummy buffer */
  239. sport_hook_rx_dummy(sport);
  240. } else {
  241. /* Both rx and tx dma will be stopped */
  242. sport_stop(sport);
  243. sport->curr_rx_desc = NULL;
  244. sport->curr_tx_desc = NULL;
  245. }
  246. sport->rx_run = 0;
  247. return 0;
  248. }
  249. EXPORT_SYMBOL(sport_rx_stop);
  250. static inline int sport_hook_tx_dummy(struct sport_device *sport)
  251. {
  252. struct dmasg *desc, temp_desc;
  253. unsigned long flags;
  254. if (WARN_ON(!sport->dummy_tx_desc) ||
  255. WARN_ON(sport->curr_tx_desc == sport->dummy_tx_desc))
  256. return -EINVAL;
  257. sport->dummy_tx_desc->next_desc_addr = sport->dummy_tx_desc + 1;
  258. /* Shorten the time on last normal descriptor */
  259. local_irq_save(flags);
  260. desc = get_dma_next_desc_ptr(sport->dma_tx_chan);
  261. /* Store the descriptor which will be damaged */
  262. temp_desc = *desc;
  263. desc->x_count = sport->dummy_count / 2;
  264. desc->y_count = 0;
  265. desc->next_desc_addr = sport->dummy_tx_desc;
  266. local_irq_restore(flags);
  267. /* Waiting for dummy buffer descriptor is already hooked*/
  268. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) - \
  269. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  270. continue;
  271. sport->curr_tx_desc = sport->dummy_tx_desc;
  272. /* Restore the damaged descriptor */
  273. *desc = temp_desc;
  274. return 0;
  275. }
  276. int sport_tx_start(struct sport_device *sport)
  277. {
  278. unsigned long flags;
  279. pr_debug("%s: tx_run:%d, rx_run:%d\n", __func__,
  280. sport->tx_run, sport->rx_run);
  281. if (sport->tx_run)
  282. return -EBUSY;
  283. if (sport->rx_run) {
  284. if (WARN_ON(!sport->dma_tx_desc) ||
  285. WARN_ON(sport->curr_tx_desc != sport->dummy_tx_desc))
  286. return -EINVAL;
  287. /* Hook the normal buffer descriptor */
  288. local_irq_save(flags);
  289. while ((get_dma_curr_desc_ptr(sport->dma_tx_chan) -
  290. sizeof(struct dmasg)) != sport->dummy_tx_desc)
  291. continue;
  292. sport->dummy_tx_desc->next_desc_addr = sport->dma_tx_desc;
  293. local_irq_restore(flags);
  294. sport->curr_tx_desc = sport->dma_tx_desc;
  295. } else {
  296. sport_tx_dma_start(sport, 0);
  297. /* Let rx dma run the dummy buffer */
  298. sport_rx_dma_start(sport, 1);
  299. sport_start(sport);
  300. }
  301. sport->tx_run = 1;
  302. return 0;
  303. }
  304. EXPORT_SYMBOL(sport_tx_start);
  305. int sport_tx_stop(struct sport_device *sport)
  306. {
  307. if (!sport->tx_run)
  308. return 0;
  309. if (sport->rx_run) {
  310. /* RX is still running, hook the dummy buffer */
  311. sport_hook_tx_dummy(sport);
  312. } else {
  313. /* Both rx and tx dma stopped */
  314. sport_stop(sport);
  315. sport->curr_rx_desc = NULL;
  316. sport->curr_tx_desc = NULL;
  317. }
  318. sport->tx_run = 0;
  319. return 0;
  320. }
  321. EXPORT_SYMBOL(sport_tx_stop);
  322. static inline int compute_wdsize(size_t wdsize)
  323. {
  324. switch (wdsize) {
  325. case 1:
  326. return WDSIZE_8;
  327. case 2:
  328. return WDSIZE_16;
  329. case 4:
  330. default:
  331. return WDSIZE_32;
  332. }
  333. }
  334. int sport_config_rx_dma(struct sport_device *sport, void *buf,
  335. int fragcount, size_t fragsize)
  336. {
  337. unsigned int x_count;
  338. unsigned int y_count;
  339. unsigned int cfg;
  340. dma_addr_t addr;
  341. pr_debug("%s buf:%p, frag:%d, fragsize:0x%lx\n", __func__, \
  342. buf, fragcount, fragsize);
  343. x_count = fragsize / sport->wdsize;
  344. y_count = 0;
  345. /* for fragments larger than 64k words we use 2d dma,
  346. * denote fragecount as two numbers' mutliply and both of them
  347. * are less than 64k.*/
  348. if (x_count >= 0x10000) {
  349. int i, count = x_count;
  350. for (i = 16; i > 0; i--) {
  351. x_count = 1 << i;
  352. if ((count & (x_count - 1)) == 0) {
  353. y_count = count >> i;
  354. if (y_count < 0x10000)
  355. break;
  356. }
  357. }
  358. if (i == 0)
  359. return -EINVAL;
  360. }
  361. pr_debug("%s(x_count:0x%x, y_count:0x%x)\n", __func__,
  362. x_count, y_count);
  363. if (sport->dma_rx_desc)
  364. dma_free_coherent(NULL, sport->rx_desc_bytes,
  365. sport->dma_rx_desc, 0);
  366. /* Allocate a new descritor ring as current one. */
  367. sport->dma_rx_desc = dma_alloc_coherent(NULL, \
  368. fragcount * sizeof(struct dmasg), &addr, 0);
  369. sport->rx_desc_bytes = fragcount * sizeof(struct dmasg);
  370. if (!sport->dma_rx_desc) {
  371. pr_err("Failed to allocate memory for rx desc\n");
  372. return -ENOMEM;
  373. }
  374. sport->rx_buf = buf;
  375. sport->rx_fragsize = fragsize;
  376. sport->rx_frags = fragcount;
  377. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | WNR | \
  378. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  379. if (y_count != 0)
  380. cfg |= DMA2D;
  381. setup_desc(sport->dma_rx_desc, buf, fragcount, fragsize,
  382. cfg|DMAEN, x_count, y_count, sport->wdsize);
  383. return 0;
  384. }
  385. EXPORT_SYMBOL(sport_config_rx_dma);
  386. int sport_config_tx_dma(struct sport_device *sport, void *buf, \
  387. int fragcount, size_t fragsize)
  388. {
  389. unsigned int x_count;
  390. unsigned int y_count;
  391. unsigned int cfg;
  392. dma_addr_t addr;
  393. pr_debug("%s buf:%p, fragcount:%d, fragsize:0x%lx\n",
  394. __func__, buf, fragcount, fragsize);
  395. x_count = fragsize/sport->wdsize;
  396. y_count = 0;
  397. /* for fragments larger than 64k words we use 2d dma,
  398. * denote fragecount as two numbers' mutliply and both of them
  399. * are less than 64k.*/
  400. if (x_count >= 0x10000) {
  401. int i, count = x_count;
  402. for (i = 16; i > 0; i--) {
  403. x_count = 1 << i;
  404. if ((count & (x_count - 1)) == 0) {
  405. y_count = count >> i;
  406. if (y_count < 0x10000)
  407. break;
  408. }
  409. }
  410. if (i == 0)
  411. return -EINVAL;
  412. }
  413. pr_debug("%s x_count:0x%x, y_count:0x%x\n", __func__,
  414. x_count, y_count);
  415. if (sport->dma_tx_desc) {
  416. dma_free_coherent(NULL, sport->tx_desc_bytes, \
  417. sport->dma_tx_desc, 0);
  418. }
  419. sport->dma_tx_desc = dma_alloc_coherent(NULL, \
  420. fragcount * sizeof(struct dmasg), &addr, 0);
  421. sport->tx_desc_bytes = fragcount * sizeof(struct dmasg);
  422. if (!sport->dma_tx_desc) {
  423. pr_err("Failed to allocate memory for tx desc\n");
  424. return -ENOMEM;
  425. }
  426. sport->tx_buf = buf;
  427. sport->tx_fragsize = fragsize;
  428. sport->tx_frags = fragcount;
  429. cfg = 0x7000 | DI_EN | compute_wdsize(sport->wdsize) | \
  430. (DESC_ELEMENT_COUNT << 8); /* large descriptor mode */
  431. if (y_count != 0)
  432. cfg |= DMA2D;
  433. setup_desc(sport->dma_tx_desc, buf, fragcount, fragsize,
  434. cfg|DMAEN, x_count, y_count, sport->wdsize);
  435. return 0;
  436. }
  437. EXPORT_SYMBOL(sport_config_tx_dma);
  438. /* setup dummy dma descriptor ring, which don't generate interrupts,
  439. * the x_modify is set to 0 */
  440. static int sport_config_rx_dummy(struct sport_device *sport)
  441. {
  442. struct dmasg *desc;
  443. unsigned config;
  444. pr_debug("%s entered\n", __func__);
  445. if (L1_DATA_A_LENGTH)
  446. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  447. else {
  448. dma_addr_t addr;
  449. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  450. memset(desc, 0, 2 * sizeof(*desc));
  451. }
  452. if (desc == NULL) {
  453. pr_err("Failed to allocate memory for dummy rx desc\n");
  454. return -ENOMEM;
  455. }
  456. sport->dummy_rx_desc = desc;
  457. desc->start_addr = (unsigned long)sport->dummy_buf;
  458. config = DMAFLOW_LARGE | NDSIZE_9 | compute_wdsize(sport->wdsize)
  459. | WNR | DMAEN;
  460. desc->cfg = config;
  461. desc->x_count = sport->dummy_count/sport->wdsize;
  462. desc->x_modify = sport->wdsize;
  463. desc->y_count = 0;
  464. desc->y_modify = 0;
  465. memcpy(desc+1, desc, sizeof(*desc));
  466. desc->next_desc_addr = desc + 1;
  467. desc[1].next_desc_addr = desc;
  468. return 0;
  469. }
  470. static int sport_config_tx_dummy(struct sport_device *sport)
  471. {
  472. struct dmasg *desc;
  473. unsigned int config;
  474. pr_debug("%s entered\n", __func__);
  475. if (L1_DATA_A_LENGTH)
  476. desc = l1_data_sram_zalloc(2 * sizeof(*desc));
  477. else {
  478. dma_addr_t addr;
  479. desc = dma_alloc_coherent(NULL, 2 * sizeof(*desc), &addr, 0);
  480. memset(desc, 0, 2 * sizeof(*desc));
  481. }
  482. if (!desc) {
  483. pr_err("Failed to allocate memory for dummy tx desc\n");
  484. return -ENOMEM;
  485. }
  486. sport->dummy_tx_desc = desc;
  487. desc->start_addr = (unsigned long)sport->dummy_buf + \
  488. sport->dummy_count;
  489. config = DMAFLOW_LARGE | NDSIZE_9 |
  490. compute_wdsize(sport->wdsize) | DMAEN;
  491. desc->cfg = config;
  492. desc->x_count = sport->dummy_count/sport->wdsize;
  493. desc->x_modify = sport->wdsize;
  494. desc->y_count = 0;
  495. desc->y_modify = 0;
  496. memcpy(desc+1, desc, sizeof(*desc));
  497. desc->next_desc_addr = desc + 1;
  498. desc[1].next_desc_addr = desc;
  499. return 0;
  500. }
  501. unsigned long sport_curr_offset_rx(struct sport_device *sport)
  502. {
  503. unsigned long curr = get_dma_curr_addr(sport->dma_rx_chan);
  504. return (unsigned char *)curr - sport->rx_buf;
  505. }
  506. EXPORT_SYMBOL(sport_curr_offset_rx);
  507. unsigned long sport_curr_offset_tx(struct sport_device *sport)
  508. {
  509. unsigned long curr = get_dma_curr_addr(sport->dma_tx_chan);
  510. return (unsigned char *)curr - sport->tx_buf;
  511. }
  512. EXPORT_SYMBOL(sport_curr_offset_tx);
  513. void sport_incfrag(struct sport_device *sport, int *frag, int tx)
  514. {
  515. ++(*frag);
  516. if (tx == 1 && *frag == sport->tx_frags)
  517. *frag = 0;
  518. if (tx == 0 && *frag == sport->rx_frags)
  519. *frag = 0;
  520. }
  521. EXPORT_SYMBOL(sport_incfrag);
  522. void sport_decfrag(struct sport_device *sport, int *frag, int tx)
  523. {
  524. --(*frag);
  525. if (tx == 1 && *frag == 0)
  526. *frag = sport->tx_frags;
  527. if (tx == 0 && *frag == 0)
  528. *frag = sport->rx_frags;
  529. }
  530. EXPORT_SYMBOL(sport_decfrag);
  531. static int sport_check_status(struct sport_device *sport,
  532. unsigned int *sport_stat,
  533. unsigned int *rx_stat,
  534. unsigned int *tx_stat)
  535. {
  536. int status = 0;
  537. if (sport_stat) {
  538. SSYNC();
  539. status = sport->regs->stat;
  540. if (status & (TOVF|TUVF|ROVF|RUVF))
  541. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  542. SSYNC();
  543. *sport_stat = status;
  544. }
  545. if (rx_stat) {
  546. SSYNC();
  547. status = get_dma_curr_irqstat(sport->dma_rx_chan);
  548. if (status & (DMA_DONE|DMA_ERR))
  549. clear_dma_irqstat(sport->dma_rx_chan);
  550. SSYNC();
  551. *rx_stat = status;
  552. }
  553. if (tx_stat) {
  554. SSYNC();
  555. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  556. if (status & (DMA_DONE|DMA_ERR))
  557. clear_dma_irqstat(sport->dma_tx_chan);
  558. SSYNC();
  559. *tx_stat = status;
  560. }
  561. return 0;
  562. }
  563. int sport_dump_stat(struct sport_device *sport, char *buf, size_t len)
  564. {
  565. int ret;
  566. ret = snprintf(buf, len,
  567. "sts: 0x%04x\n"
  568. "rx dma %d sts: 0x%04x tx dma %d sts: 0x%04x\n",
  569. sport->regs->stat,
  570. sport->dma_rx_chan,
  571. get_dma_curr_irqstat(sport->dma_rx_chan),
  572. sport->dma_tx_chan,
  573. get_dma_curr_irqstat(sport->dma_tx_chan));
  574. buf += ret;
  575. len -= ret;
  576. ret += snprintf(buf, len,
  577. "curr_rx_desc:0x%p, curr_tx_desc:0x%p\n"
  578. "dma_rx_desc:0x%p, dma_tx_desc:0x%p\n"
  579. "dummy_rx_desc:0x%p, dummy_tx_desc:0x%p\n",
  580. sport->curr_rx_desc, sport->curr_tx_desc,
  581. sport->dma_rx_desc, sport->dma_tx_desc,
  582. sport->dummy_rx_desc, sport->dummy_tx_desc);
  583. return ret;
  584. }
  585. static irqreturn_t rx_handler(int irq, void *dev_id)
  586. {
  587. unsigned int rx_stat;
  588. struct sport_device *sport = dev_id;
  589. pr_debug("%s enter\n", __func__);
  590. sport_check_status(sport, NULL, &rx_stat, NULL);
  591. if (!(rx_stat & DMA_DONE))
  592. pr_err("rx dma is already stopped\n");
  593. if (sport->rx_callback) {
  594. sport->rx_callback(sport->rx_data);
  595. return IRQ_HANDLED;
  596. }
  597. return IRQ_NONE;
  598. }
  599. static irqreturn_t tx_handler(int irq, void *dev_id)
  600. {
  601. unsigned int tx_stat;
  602. struct sport_device *sport = dev_id;
  603. pr_debug("%s enter\n", __func__);
  604. sport_check_status(sport, NULL, NULL, &tx_stat);
  605. if (!(tx_stat & DMA_DONE)) {
  606. pr_err("tx dma is already stopped\n");
  607. return IRQ_HANDLED;
  608. }
  609. if (sport->tx_callback) {
  610. sport->tx_callback(sport->tx_data);
  611. return IRQ_HANDLED;
  612. }
  613. return IRQ_NONE;
  614. }
  615. static irqreturn_t err_handler(int irq, void *dev_id)
  616. {
  617. unsigned int status = 0;
  618. struct sport_device *sport = dev_id;
  619. pr_debug("%s\n", __func__);
  620. if (sport_check_status(sport, &status, NULL, NULL)) {
  621. pr_err("error checking status ??");
  622. return IRQ_NONE;
  623. }
  624. if (status & (TOVF|TUVF|ROVF|RUVF)) {
  625. pr_info("sport status error:%s%s%s%s\n",
  626. status & TOVF ? " TOVF" : "",
  627. status & TUVF ? " TUVF" : "",
  628. status & ROVF ? " ROVF" : "",
  629. status & RUVF ? " RUVF" : "");
  630. if (status & TOVF || status & TUVF) {
  631. disable_dma(sport->dma_tx_chan);
  632. if (sport->tx_run)
  633. sport_tx_dma_start(sport, 0);
  634. else
  635. sport_tx_dma_start(sport, 1);
  636. enable_dma(sport->dma_tx_chan);
  637. } else {
  638. disable_dma(sport->dma_rx_chan);
  639. if (sport->rx_run)
  640. sport_rx_dma_start(sport, 0);
  641. else
  642. sport_rx_dma_start(sport, 1);
  643. enable_dma(sport->dma_rx_chan);
  644. }
  645. }
  646. status = sport->regs->stat;
  647. if (status & (TOVF|TUVF|ROVF|RUVF))
  648. sport->regs->stat = (status & (TOVF|TUVF|ROVF|RUVF));
  649. SSYNC();
  650. if (sport->err_callback)
  651. sport->err_callback(sport->err_data);
  652. return IRQ_HANDLED;
  653. }
  654. int sport_set_rx_callback(struct sport_device *sport,
  655. void (*rx_callback)(void *), void *rx_data)
  656. {
  657. if (WARN_ON(!rx_callback))
  658. return -EINVAL;
  659. sport->rx_callback = rx_callback;
  660. sport->rx_data = rx_data;
  661. return 0;
  662. }
  663. EXPORT_SYMBOL(sport_set_rx_callback);
  664. int sport_set_tx_callback(struct sport_device *sport,
  665. void (*tx_callback)(void *), void *tx_data)
  666. {
  667. if (WARN_ON(!tx_callback))
  668. return -EINVAL;
  669. sport->tx_callback = tx_callback;
  670. sport->tx_data = tx_data;
  671. return 0;
  672. }
  673. EXPORT_SYMBOL(sport_set_tx_callback);
  674. int sport_set_err_callback(struct sport_device *sport,
  675. void (*err_callback)(void *), void *err_data)
  676. {
  677. if (WARN_ON(!err_callback))
  678. return -EINVAL;
  679. sport->err_callback = err_callback;
  680. sport->err_data = err_data;
  681. return 0;
  682. }
  683. EXPORT_SYMBOL(sport_set_err_callback);
  684. static int sport_config_pdev(struct platform_device *pdev, struct sport_param *param)
  685. {
  686. /* Extract settings from platform data */
  687. struct device *dev = &pdev->dev;
  688. struct bfin_snd_platform_data *pdata = dev->platform_data;
  689. struct resource *res;
  690. param->num = pdev->id;
  691. if (!pdata) {
  692. dev_err(dev, "no platform_data\n");
  693. return -ENODEV;
  694. }
  695. param->pin_req = pdata->pin_req;
  696. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  697. if (!res) {
  698. dev_err(dev, "no MEM resource\n");
  699. return -ENODEV;
  700. }
  701. param->regs = (struct sport_register *)res->start;
  702. /* first RX, then TX */
  703. res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
  704. if (!res) {
  705. dev_err(dev, "no rx DMA resource\n");
  706. return -ENODEV;
  707. }
  708. param->dma_rx_chan = res->start;
  709. res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
  710. if (!res) {
  711. dev_err(dev, "no tx DMA resource\n");
  712. return -ENODEV;
  713. }
  714. param->dma_tx_chan = res->start;
  715. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  716. if (!res) {
  717. dev_err(dev, "no irq resource\n");
  718. return -ENODEV;
  719. }
  720. param->err_irq = res->start;
  721. return 0;
  722. }
  723. struct sport_device *sport_init(struct platform_device *pdev,
  724. unsigned int wdsize, unsigned int dummy_count, size_t priv_size)
  725. {
  726. struct device *dev = &pdev->dev;
  727. struct sport_param param;
  728. struct sport_device *sport;
  729. int ret;
  730. dev_dbg(dev, "%s enter\n", __func__);
  731. param.wdsize = wdsize;
  732. param.dummy_count = dummy_count;
  733. if (WARN_ON(param.wdsize == 0 || param.dummy_count == 0))
  734. return NULL;
  735. ret = sport_config_pdev(pdev, &param);
  736. if (ret)
  737. return NULL;
  738. if (peripheral_request_list(param.pin_req, "soc-audio")) {
  739. dev_err(dev, "requesting Peripherals failed\n");
  740. return NULL;
  741. }
  742. sport = kzalloc(sizeof(*sport), GFP_KERNEL);
  743. if (!sport) {
  744. dev_err(dev, "failed to allocate for sport device\n");
  745. goto __init_err0;
  746. }
  747. sport->num = param.num;
  748. sport->dma_rx_chan = param.dma_rx_chan;
  749. sport->dma_tx_chan = param.dma_tx_chan;
  750. sport->err_irq = param.err_irq;
  751. sport->regs = param.regs;
  752. sport->pin_req = param.pin_req;
  753. if (request_dma(sport->dma_rx_chan, "SPORT RX Data") == -EBUSY) {
  754. dev_err(dev, "failed to request RX dma %d\n", sport->dma_rx_chan);
  755. goto __init_err1;
  756. }
  757. if (set_dma_callback(sport->dma_rx_chan, rx_handler, sport) != 0) {
  758. dev_err(dev, "failed to request RX irq %d\n", sport->dma_rx_chan);
  759. goto __init_err2;
  760. }
  761. if (request_dma(sport->dma_tx_chan, "SPORT TX Data") == -EBUSY) {
  762. dev_err(dev, "failed to request TX dma %d\n", sport->dma_tx_chan);
  763. goto __init_err2;
  764. }
  765. if (set_dma_callback(sport->dma_tx_chan, tx_handler, sport) != 0) {
  766. dev_err(dev, "failed to request TX irq %d\n", sport->dma_tx_chan);
  767. goto __init_err3;
  768. }
  769. if (request_irq(sport->err_irq, err_handler, IRQF_SHARED, "SPORT err",
  770. sport) < 0) {
  771. dev_err(dev, "failed to request err irq %d\n", sport->err_irq);
  772. goto __init_err3;
  773. }
  774. dev_info(dev, "dma rx:%d tx:%d, err irq:%d, regs:%p\n",
  775. sport->dma_rx_chan, sport->dma_tx_chan,
  776. sport->err_irq, sport->regs);
  777. sport->wdsize = param.wdsize;
  778. sport->dummy_count = param.dummy_count;
  779. sport->private_data = kzalloc(priv_size, GFP_KERNEL);
  780. if (!sport->private_data) {
  781. dev_err(dev, "could not alloc priv data %zu bytes\n", priv_size);
  782. goto __init_err4;
  783. }
  784. if (L1_DATA_A_LENGTH)
  785. sport->dummy_buf = l1_data_sram_zalloc(param.dummy_count * 2);
  786. else
  787. sport->dummy_buf = kzalloc(param.dummy_count * 2, GFP_KERNEL);
  788. if (sport->dummy_buf == NULL) {
  789. dev_err(dev, "failed to allocate dummy buffer\n");
  790. goto __error1;
  791. }
  792. ret = sport_config_rx_dummy(sport);
  793. if (ret) {
  794. dev_err(dev, "failed to config rx dummy ring\n");
  795. goto __error2;
  796. }
  797. ret = sport_config_tx_dummy(sport);
  798. if (ret) {
  799. dev_err(dev, "failed to config tx dummy ring\n");
  800. goto __error3;
  801. }
  802. platform_set_drvdata(pdev, sport);
  803. return sport;
  804. __error3:
  805. if (L1_DATA_A_LENGTH)
  806. l1_data_sram_free(sport->dummy_rx_desc);
  807. else
  808. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  809. sport->dummy_rx_desc, 0);
  810. __error2:
  811. if (L1_DATA_A_LENGTH)
  812. l1_data_sram_free(sport->dummy_buf);
  813. else
  814. kfree(sport->dummy_buf);
  815. __error1:
  816. kfree(sport->private_data);
  817. __init_err4:
  818. free_irq(sport->err_irq, sport);
  819. __init_err3:
  820. free_dma(sport->dma_tx_chan);
  821. __init_err2:
  822. free_dma(sport->dma_rx_chan);
  823. __init_err1:
  824. kfree(sport);
  825. __init_err0:
  826. peripheral_free_list(param.pin_req);
  827. return NULL;
  828. }
  829. EXPORT_SYMBOL(sport_init);
  830. void sport_done(struct sport_device *sport)
  831. {
  832. if (sport == NULL)
  833. return;
  834. sport_stop(sport);
  835. if (sport->dma_rx_desc)
  836. dma_free_coherent(NULL, sport->rx_desc_bytes,
  837. sport->dma_rx_desc, 0);
  838. if (sport->dma_tx_desc)
  839. dma_free_coherent(NULL, sport->tx_desc_bytes,
  840. sport->dma_tx_desc, 0);
  841. #if L1_DATA_A_LENGTH != 0
  842. l1_data_sram_free(sport->dummy_rx_desc);
  843. l1_data_sram_free(sport->dummy_tx_desc);
  844. l1_data_sram_free(sport->dummy_buf);
  845. #else
  846. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  847. sport->dummy_rx_desc, 0);
  848. dma_free_coherent(NULL, 2*sizeof(struct dmasg),
  849. sport->dummy_tx_desc, 0);
  850. kfree(sport->dummy_buf);
  851. #endif
  852. free_dma(sport->dma_rx_chan);
  853. free_dma(sport->dma_tx_chan);
  854. free_irq(sport->err_irq, sport);
  855. kfree(sport->private_data);
  856. peripheral_free_list(sport->pin_req);
  857. kfree(sport);
  858. }
  859. EXPORT_SYMBOL(sport_done);
  860. /*
  861. * It is only used to send several bytes when dma is not enabled
  862. * sport controller is configured but not enabled.
  863. * Multichannel cannot works with pio mode */
  864. /* Used by ac97 to write and read codec register */
  865. int sport_send_and_recv(struct sport_device *sport, u8 *out_data, \
  866. u8 *in_data, int len)
  867. {
  868. unsigned short dma_config;
  869. unsigned short status;
  870. unsigned long flags;
  871. unsigned long wait = 0;
  872. pr_debug("%s enter, out_data:%p, in_data:%p len:%d\n", \
  873. __func__, out_data, in_data, len);
  874. pr_debug("tcr1:0x%04x, tcr2:0x%04x, tclkdiv:0x%04x, tfsdiv:0x%04x\n"
  875. "mcmc1:0x%04x, mcmc2:0x%04x\n",
  876. sport->regs->tcr1, sport->regs->tcr2,
  877. sport->regs->tclkdiv, sport->regs->tfsdiv,
  878. sport->regs->mcmc1, sport->regs->mcmc2);
  879. flush_dcache_range((unsigned)out_data, (unsigned)(out_data + len));
  880. /* Enable tx dma */
  881. dma_config = (RESTART | WDSIZE_16 | DI_EN);
  882. set_dma_start_addr(sport->dma_tx_chan, (unsigned long)out_data);
  883. set_dma_x_count(sport->dma_tx_chan, len/2);
  884. set_dma_x_modify(sport->dma_tx_chan, 2);
  885. set_dma_config(sport->dma_tx_chan, dma_config);
  886. enable_dma(sport->dma_tx_chan);
  887. if (in_data != NULL) {
  888. invalidate_dcache_range((unsigned)in_data, \
  889. (unsigned)(in_data + len));
  890. /* Enable rx dma */
  891. dma_config = (RESTART | WDSIZE_16 | WNR | DI_EN);
  892. set_dma_start_addr(sport->dma_rx_chan, (unsigned long)in_data);
  893. set_dma_x_count(sport->dma_rx_chan, len/2);
  894. set_dma_x_modify(sport->dma_rx_chan, 2);
  895. set_dma_config(sport->dma_rx_chan, dma_config);
  896. enable_dma(sport->dma_rx_chan);
  897. }
  898. local_irq_save(flags);
  899. sport->regs->tcr1 |= TSPEN;
  900. sport->regs->rcr1 |= RSPEN;
  901. SSYNC();
  902. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  903. while (status & DMA_RUN) {
  904. udelay(1);
  905. status = get_dma_curr_irqstat(sport->dma_tx_chan);
  906. pr_debug("DMA status:0x%04x\n", status);
  907. if (wait++ > 100)
  908. goto __over;
  909. }
  910. status = sport->regs->stat;
  911. wait = 0;
  912. while (!(status & TXHRE)) {
  913. pr_debug("sport status:0x%04x\n", status);
  914. udelay(1);
  915. status = *(unsigned short *)&sport->regs->stat;
  916. if (wait++ > 1000)
  917. goto __over;
  918. }
  919. /* Wait for the last byte sent out */
  920. udelay(20);
  921. pr_debug("sport status:0x%04x\n", status);
  922. __over:
  923. sport->regs->tcr1 &= ~TSPEN;
  924. sport->regs->rcr1 &= ~RSPEN;
  925. SSYNC();
  926. disable_dma(sport->dma_tx_chan);
  927. /* Clear the status */
  928. clear_dma_irqstat(sport->dma_tx_chan);
  929. if (in_data != NULL) {
  930. disable_dma(sport->dma_rx_chan);
  931. clear_dma_irqstat(sport->dma_rx_chan);
  932. }
  933. SSYNC();
  934. local_irq_restore(flags);
  935. return 0;
  936. }
  937. EXPORT_SYMBOL(sport_send_and_recv);
  938. MODULE_AUTHOR("Roy Huang");
  939. MODULE_DESCRIPTION("SPORT driver for ADI Blackfin");
  940. MODULE_LICENSE("GPL");