pm_domains.c 19 KB

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  1. /*
  2. * Rockchip Generic power domain support.
  3. *
  4. * Copyright (c) 2015 ROCKCHIP, Co. Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/io.h>
  11. #include <linux/err.h>
  12. #include <linux/pm_clock.h>
  13. #include <linux/pm_domain.h>
  14. #include <linux/of_address.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/clk.h>
  17. #include <linux/regmap.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <dt-bindings/power/rk3288-power.h>
  20. #include <dt-bindings/power/rk3368-power.h>
  21. #include <dt-bindings/power/rk3399-power.h>
  22. struct rockchip_domain_info {
  23. int pwr_mask;
  24. int status_mask;
  25. int req_mask;
  26. int idle_mask;
  27. int ack_mask;
  28. bool active_wakeup;
  29. };
  30. struct rockchip_pmu_info {
  31. u32 pwr_offset;
  32. u32 status_offset;
  33. u32 req_offset;
  34. u32 idle_offset;
  35. u32 ack_offset;
  36. u32 core_pwrcnt_offset;
  37. u32 gpu_pwrcnt_offset;
  38. unsigned int core_power_transition_time;
  39. unsigned int gpu_power_transition_time;
  40. int num_domains;
  41. const struct rockchip_domain_info *domain_info;
  42. };
  43. #define MAX_QOS_REGS_NUM 5
  44. #define QOS_PRIORITY 0x08
  45. #define QOS_MODE 0x0c
  46. #define QOS_BANDWIDTH 0x10
  47. #define QOS_SATURATION 0x14
  48. #define QOS_EXTCONTROL 0x18
  49. struct rockchip_pm_domain {
  50. struct generic_pm_domain genpd;
  51. const struct rockchip_domain_info *info;
  52. struct rockchip_pmu *pmu;
  53. int num_qos;
  54. struct regmap **qos_regmap;
  55. u32 *qos_save_regs[MAX_QOS_REGS_NUM];
  56. int num_clks;
  57. struct clk *clks[];
  58. };
  59. struct rockchip_pmu {
  60. struct device *dev;
  61. struct regmap *regmap;
  62. const struct rockchip_pmu_info *info;
  63. struct mutex mutex; /* mutex lock for pmu */
  64. struct genpd_onecell_data genpd_data;
  65. struct generic_pm_domain *domains[];
  66. };
  67. #define to_rockchip_pd(gpd) container_of(gpd, struct rockchip_pm_domain, genpd)
  68. #define DOMAIN(pwr, status, req, idle, ack, wakeup) \
  69. { \
  70. .pwr_mask = (pwr >= 0) ? BIT(pwr) : 0, \
  71. .status_mask = (status >= 0) ? BIT(status) : 0, \
  72. .req_mask = (req >= 0) ? BIT(req) : 0, \
  73. .idle_mask = (idle >= 0) ? BIT(idle) : 0, \
  74. .ack_mask = (ack >= 0) ? BIT(ack) : 0, \
  75. .active_wakeup = wakeup, \
  76. }
  77. #define DOMAIN_RK3288(pwr, status, req, wakeup) \
  78. DOMAIN(pwr, status, req, req, (req) + 16, wakeup)
  79. #define DOMAIN_RK3368(pwr, status, req, wakeup) \
  80. DOMAIN(pwr, status, req, (req) + 16, req, wakeup)
  81. #define DOMAIN_RK3399(pwr, status, req, wakeup) \
  82. DOMAIN(pwr, status, req, req, req, wakeup)
  83. static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
  84. {
  85. struct rockchip_pmu *pmu = pd->pmu;
  86. const struct rockchip_domain_info *pd_info = pd->info;
  87. unsigned int val;
  88. regmap_read(pmu->regmap, pmu->info->idle_offset, &val);
  89. return (val & pd_info->idle_mask) == pd_info->idle_mask;
  90. }
  91. static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd,
  92. bool idle)
  93. {
  94. const struct rockchip_domain_info *pd_info = pd->info;
  95. struct rockchip_pmu *pmu = pd->pmu;
  96. unsigned int val;
  97. if (pd_info->req_mask == 0)
  98. return 0;
  99. regmap_update_bits(pmu->regmap, pmu->info->req_offset,
  100. pd_info->req_mask, idle ? -1U : 0);
  101. dsb(sy);
  102. do {
  103. regmap_read(pmu->regmap, pmu->info->ack_offset, &val);
  104. } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0));
  105. while (rockchip_pmu_domain_is_idle(pd) != idle)
  106. cpu_relax();
  107. return 0;
  108. }
  109. static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd)
  110. {
  111. int i;
  112. for (i = 0; i < pd->num_qos; i++) {
  113. regmap_read(pd->qos_regmap[i],
  114. QOS_PRIORITY,
  115. &pd->qos_save_regs[0][i]);
  116. regmap_read(pd->qos_regmap[i],
  117. QOS_MODE,
  118. &pd->qos_save_regs[1][i]);
  119. regmap_read(pd->qos_regmap[i],
  120. QOS_BANDWIDTH,
  121. &pd->qos_save_regs[2][i]);
  122. regmap_read(pd->qos_regmap[i],
  123. QOS_SATURATION,
  124. &pd->qos_save_regs[3][i]);
  125. regmap_read(pd->qos_regmap[i],
  126. QOS_EXTCONTROL,
  127. &pd->qos_save_regs[4][i]);
  128. }
  129. return 0;
  130. }
  131. static int rockchip_pmu_restore_qos(struct rockchip_pm_domain *pd)
  132. {
  133. int i;
  134. for (i = 0; i < pd->num_qos; i++) {
  135. regmap_write(pd->qos_regmap[i],
  136. QOS_PRIORITY,
  137. pd->qos_save_regs[0][i]);
  138. regmap_write(pd->qos_regmap[i],
  139. QOS_MODE,
  140. pd->qos_save_regs[1][i]);
  141. regmap_write(pd->qos_regmap[i],
  142. QOS_BANDWIDTH,
  143. pd->qos_save_regs[2][i]);
  144. regmap_write(pd->qos_regmap[i],
  145. QOS_SATURATION,
  146. pd->qos_save_regs[3][i]);
  147. regmap_write(pd->qos_regmap[i],
  148. QOS_EXTCONTROL,
  149. pd->qos_save_regs[4][i]);
  150. }
  151. return 0;
  152. }
  153. static bool rockchip_pmu_domain_is_on(struct rockchip_pm_domain *pd)
  154. {
  155. struct rockchip_pmu *pmu = pd->pmu;
  156. unsigned int val;
  157. /* check idle status for idle-only domains */
  158. if (pd->info->status_mask == 0)
  159. return !rockchip_pmu_domain_is_idle(pd);
  160. regmap_read(pmu->regmap, pmu->info->status_offset, &val);
  161. /* 1'b0: power on, 1'b1: power off */
  162. return !(val & pd->info->status_mask);
  163. }
  164. static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
  165. bool on)
  166. {
  167. struct rockchip_pmu *pmu = pd->pmu;
  168. if (pd->info->pwr_mask == 0)
  169. return;
  170. regmap_update_bits(pmu->regmap, pmu->info->pwr_offset,
  171. pd->info->pwr_mask, on ? 0 : -1U);
  172. dsb(sy);
  173. while (rockchip_pmu_domain_is_on(pd) != on)
  174. cpu_relax();
  175. }
  176. static int rockchip_pd_power(struct rockchip_pm_domain *pd, bool power_on)
  177. {
  178. int i;
  179. mutex_lock(&pd->pmu->mutex);
  180. if (rockchip_pmu_domain_is_on(pd) != power_on) {
  181. for (i = 0; i < pd->num_clks; i++)
  182. clk_enable(pd->clks[i]);
  183. if (!power_on) {
  184. rockchip_pmu_save_qos(pd);
  185. /* if powering down, idle request to NIU first */
  186. rockchip_pmu_set_idle_request(pd, true);
  187. }
  188. rockchip_do_pmu_set_power_domain(pd, power_on);
  189. if (power_on) {
  190. /* if powering up, leave idle mode */
  191. rockchip_pmu_set_idle_request(pd, false);
  192. rockchip_pmu_restore_qos(pd);
  193. }
  194. for (i = pd->num_clks - 1; i >= 0; i--)
  195. clk_disable(pd->clks[i]);
  196. }
  197. mutex_unlock(&pd->pmu->mutex);
  198. return 0;
  199. }
  200. static int rockchip_pd_power_on(struct generic_pm_domain *domain)
  201. {
  202. struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
  203. return rockchip_pd_power(pd, true);
  204. }
  205. static int rockchip_pd_power_off(struct generic_pm_domain *domain)
  206. {
  207. struct rockchip_pm_domain *pd = to_rockchip_pd(domain);
  208. return rockchip_pd_power(pd, false);
  209. }
  210. static int rockchip_pd_attach_dev(struct generic_pm_domain *genpd,
  211. struct device *dev)
  212. {
  213. struct clk *clk;
  214. int i;
  215. int error;
  216. dev_dbg(dev, "attaching to power domain '%s'\n", genpd->name);
  217. error = pm_clk_create(dev);
  218. if (error) {
  219. dev_err(dev, "pm_clk_create failed %d\n", error);
  220. return error;
  221. }
  222. i = 0;
  223. while ((clk = of_clk_get(dev->of_node, i++)) && !IS_ERR(clk)) {
  224. dev_dbg(dev, "adding clock '%pC' to list of PM clocks\n", clk);
  225. error = pm_clk_add_clk(dev, clk);
  226. if (error) {
  227. dev_err(dev, "pm_clk_add_clk failed %d\n", error);
  228. clk_put(clk);
  229. pm_clk_destroy(dev);
  230. return error;
  231. }
  232. }
  233. return 0;
  234. }
  235. static void rockchip_pd_detach_dev(struct generic_pm_domain *genpd,
  236. struct device *dev)
  237. {
  238. dev_dbg(dev, "detaching from power domain '%s'\n", genpd->name);
  239. pm_clk_destroy(dev);
  240. }
  241. static bool rockchip_active_wakeup(struct device *dev)
  242. {
  243. struct generic_pm_domain *genpd;
  244. struct rockchip_pm_domain *pd;
  245. genpd = pd_to_genpd(dev->pm_domain);
  246. pd = container_of(genpd, struct rockchip_pm_domain, genpd);
  247. return pd->info->active_wakeup;
  248. }
  249. static int rockchip_pm_add_one_domain(struct rockchip_pmu *pmu,
  250. struct device_node *node)
  251. {
  252. const struct rockchip_domain_info *pd_info;
  253. struct rockchip_pm_domain *pd;
  254. struct device_node *qos_node;
  255. struct clk *clk;
  256. int clk_cnt;
  257. int i, j;
  258. u32 id;
  259. int error;
  260. error = of_property_read_u32(node, "reg", &id);
  261. if (error) {
  262. dev_err(pmu->dev,
  263. "%s: failed to retrieve domain id (reg): %d\n",
  264. node->name, error);
  265. return -EINVAL;
  266. }
  267. if (id >= pmu->info->num_domains) {
  268. dev_err(pmu->dev, "%s: invalid domain id %d\n",
  269. node->name, id);
  270. return -EINVAL;
  271. }
  272. pd_info = &pmu->info->domain_info[id];
  273. if (!pd_info) {
  274. dev_err(pmu->dev, "%s: undefined domain id %d\n",
  275. node->name, id);
  276. return -EINVAL;
  277. }
  278. clk_cnt = of_count_phandle_with_args(node, "clocks", "#clock-cells");
  279. pd = devm_kzalloc(pmu->dev,
  280. sizeof(*pd) + clk_cnt * sizeof(pd->clks[0]),
  281. GFP_KERNEL);
  282. if (!pd)
  283. return -ENOMEM;
  284. pd->info = pd_info;
  285. pd->pmu = pmu;
  286. for (i = 0; i < clk_cnt; i++) {
  287. clk = of_clk_get(node, i);
  288. if (IS_ERR(clk)) {
  289. error = PTR_ERR(clk);
  290. dev_err(pmu->dev,
  291. "%s: failed to get clk at index %d: %d\n",
  292. node->name, i, error);
  293. goto err_out;
  294. }
  295. error = clk_prepare(clk);
  296. if (error) {
  297. dev_err(pmu->dev,
  298. "%s: failed to prepare clk %pC (index %d): %d\n",
  299. node->name, clk, i, error);
  300. clk_put(clk);
  301. goto err_out;
  302. }
  303. pd->clks[pd->num_clks++] = clk;
  304. dev_dbg(pmu->dev, "added clock '%pC' to domain '%s'\n",
  305. clk, node->name);
  306. }
  307. pd->num_qos = of_count_phandle_with_args(node, "pm_qos",
  308. NULL);
  309. if (pd->num_qos > 0) {
  310. pd->qos_regmap = devm_kcalloc(pmu->dev, pd->num_qos,
  311. sizeof(*pd->qos_regmap),
  312. GFP_KERNEL);
  313. if (!pd->qos_regmap) {
  314. error = -ENOMEM;
  315. goto err_out;
  316. }
  317. for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
  318. pd->qos_save_regs[j] = devm_kcalloc(pmu->dev,
  319. pd->num_qos,
  320. sizeof(u32),
  321. GFP_KERNEL);
  322. if (!pd->qos_save_regs[j]) {
  323. error = -ENOMEM;
  324. goto err_out;
  325. }
  326. }
  327. for (j = 0; j < pd->num_qos; j++) {
  328. qos_node = of_parse_phandle(node, "pm_qos", j);
  329. if (!qos_node) {
  330. error = -ENODEV;
  331. goto err_out;
  332. }
  333. pd->qos_regmap[j] = syscon_node_to_regmap(qos_node);
  334. if (IS_ERR(pd->qos_regmap[j])) {
  335. error = -ENODEV;
  336. of_node_put(qos_node);
  337. goto err_out;
  338. }
  339. of_node_put(qos_node);
  340. }
  341. }
  342. error = rockchip_pd_power(pd, true);
  343. if (error) {
  344. dev_err(pmu->dev,
  345. "failed to power on domain '%s': %d\n",
  346. node->name, error);
  347. goto err_out;
  348. }
  349. pd->genpd.name = node->name;
  350. pd->genpd.power_off = rockchip_pd_power_off;
  351. pd->genpd.power_on = rockchip_pd_power_on;
  352. pd->genpd.attach_dev = rockchip_pd_attach_dev;
  353. pd->genpd.detach_dev = rockchip_pd_detach_dev;
  354. pd->genpd.dev_ops.active_wakeup = rockchip_active_wakeup;
  355. pd->genpd.flags = GENPD_FLAG_PM_CLK;
  356. pm_genpd_init(&pd->genpd, NULL, false);
  357. pmu->genpd_data.domains[id] = &pd->genpd;
  358. return 0;
  359. err_out:
  360. while (--i >= 0) {
  361. clk_unprepare(pd->clks[i]);
  362. clk_put(pd->clks[i]);
  363. }
  364. return error;
  365. }
  366. static void rockchip_pm_remove_one_domain(struct rockchip_pm_domain *pd)
  367. {
  368. int i;
  369. for (i = 0; i < pd->num_clks; i++) {
  370. clk_unprepare(pd->clks[i]);
  371. clk_put(pd->clks[i]);
  372. }
  373. /* protect the zeroing of pm->num_clks */
  374. mutex_lock(&pd->pmu->mutex);
  375. pd->num_clks = 0;
  376. mutex_unlock(&pd->pmu->mutex);
  377. /* devm will free our memory */
  378. }
  379. static void rockchip_pm_domain_cleanup(struct rockchip_pmu *pmu)
  380. {
  381. struct generic_pm_domain *genpd;
  382. struct rockchip_pm_domain *pd;
  383. int i;
  384. for (i = 0; i < pmu->genpd_data.num_domains; i++) {
  385. genpd = pmu->genpd_data.domains[i];
  386. if (genpd) {
  387. pd = to_rockchip_pd(genpd);
  388. rockchip_pm_remove_one_domain(pd);
  389. }
  390. }
  391. /* devm will free our memory */
  392. }
  393. static void rockchip_configure_pd_cnt(struct rockchip_pmu *pmu,
  394. u32 domain_reg_offset,
  395. unsigned int count)
  396. {
  397. /* First configure domain power down transition count ... */
  398. regmap_write(pmu->regmap, domain_reg_offset, count);
  399. /* ... and then power up count. */
  400. regmap_write(pmu->regmap, domain_reg_offset + 4, count);
  401. }
  402. static int rockchip_pm_add_subdomain(struct rockchip_pmu *pmu,
  403. struct device_node *parent)
  404. {
  405. struct device_node *np;
  406. struct generic_pm_domain *child_domain, *parent_domain;
  407. int error;
  408. for_each_child_of_node(parent, np) {
  409. u32 idx;
  410. error = of_property_read_u32(parent, "reg", &idx);
  411. if (error) {
  412. dev_err(pmu->dev,
  413. "%s: failed to retrieve domain id (reg): %d\n",
  414. parent->name, error);
  415. goto err_out;
  416. }
  417. parent_domain = pmu->genpd_data.domains[idx];
  418. error = rockchip_pm_add_one_domain(pmu, np);
  419. if (error) {
  420. dev_err(pmu->dev, "failed to handle node %s: %d\n",
  421. np->name, error);
  422. goto err_out;
  423. }
  424. error = of_property_read_u32(np, "reg", &idx);
  425. if (error) {
  426. dev_err(pmu->dev,
  427. "%s: failed to retrieve domain id (reg): %d\n",
  428. np->name, error);
  429. goto err_out;
  430. }
  431. child_domain = pmu->genpd_data.domains[idx];
  432. error = pm_genpd_add_subdomain(parent_domain, child_domain);
  433. if (error) {
  434. dev_err(pmu->dev, "%s failed to add subdomain %s: %d\n",
  435. parent_domain->name, child_domain->name, error);
  436. goto err_out;
  437. } else {
  438. dev_dbg(pmu->dev, "%s add subdomain: %s\n",
  439. parent_domain->name, child_domain->name);
  440. }
  441. rockchip_pm_add_subdomain(pmu, np);
  442. }
  443. return 0;
  444. err_out:
  445. of_node_put(np);
  446. return error;
  447. }
  448. static int rockchip_pm_domain_probe(struct platform_device *pdev)
  449. {
  450. struct device *dev = &pdev->dev;
  451. struct device_node *np = dev->of_node;
  452. struct device_node *node;
  453. struct device *parent;
  454. struct rockchip_pmu *pmu;
  455. const struct of_device_id *match;
  456. const struct rockchip_pmu_info *pmu_info;
  457. int error;
  458. if (!np) {
  459. dev_err(dev, "device tree node not found\n");
  460. return -ENODEV;
  461. }
  462. match = of_match_device(dev->driver->of_match_table, dev);
  463. if (!match || !match->data) {
  464. dev_err(dev, "missing pmu data\n");
  465. return -EINVAL;
  466. }
  467. pmu_info = match->data;
  468. pmu = devm_kzalloc(dev,
  469. sizeof(*pmu) +
  470. pmu_info->num_domains * sizeof(pmu->domains[0]),
  471. GFP_KERNEL);
  472. if (!pmu)
  473. return -ENOMEM;
  474. pmu->dev = &pdev->dev;
  475. mutex_init(&pmu->mutex);
  476. pmu->info = pmu_info;
  477. pmu->genpd_data.domains = pmu->domains;
  478. pmu->genpd_data.num_domains = pmu_info->num_domains;
  479. parent = dev->parent;
  480. if (!parent) {
  481. dev_err(dev, "no parent for syscon devices\n");
  482. return -ENODEV;
  483. }
  484. pmu->regmap = syscon_node_to_regmap(parent->of_node);
  485. if (IS_ERR(pmu->regmap)) {
  486. dev_err(dev, "no regmap available\n");
  487. return PTR_ERR(pmu->regmap);
  488. }
  489. /*
  490. * Configure power up and down transition delays for CORE
  491. * and GPU domains.
  492. */
  493. rockchip_configure_pd_cnt(pmu, pmu_info->core_pwrcnt_offset,
  494. pmu_info->core_power_transition_time);
  495. rockchip_configure_pd_cnt(pmu, pmu_info->gpu_pwrcnt_offset,
  496. pmu_info->gpu_power_transition_time);
  497. error = -ENODEV;
  498. for_each_available_child_of_node(np, node) {
  499. error = rockchip_pm_add_one_domain(pmu, node);
  500. if (error) {
  501. dev_err(dev, "failed to handle node %s: %d\n",
  502. node->name, error);
  503. of_node_put(node);
  504. goto err_out;
  505. }
  506. error = rockchip_pm_add_subdomain(pmu, node);
  507. if (error < 0) {
  508. dev_err(dev, "failed to handle subdomain node %s: %d\n",
  509. node->name, error);
  510. of_node_put(node);
  511. goto err_out;
  512. }
  513. }
  514. if (error) {
  515. dev_dbg(dev, "no power domains defined\n");
  516. goto err_out;
  517. }
  518. of_genpd_add_provider_onecell(np, &pmu->genpd_data);
  519. return 0;
  520. err_out:
  521. rockchip_pm_domain_cleanup(pmu);
  522. return error;
  523. }
  524. static const struct rockchip_domain_info rk3288_pm_domains[] = {
  525. [RK3288_PD_VIO] = DOMAIN_RK3288(7, 7, 4, false),
  526. [RK3288_PD_HEVC] = DOMAIN_RK3288(14, 10, 9, false),
  527. [RK3288_PD_VIDEO] = DOMAIN_RK3288(8, 8, 3, false),
  528. [RK3288_PD_GPU] = DOMAIN_RK3288(9, 9, 2, false),
  529. };
  530. static const struct rockchip_domain_info rk3368_pm_domains[] = {
  531. [RK3368_PD_PERI] = DOMAIN_RK3368(13, 12, 6, true),
  532. [RK3368_PD_VIO] = DOMAIN_RK3368(15, 14, 8, false),
  533. [RK3368_PD_VIDEO] = DOMAIN_RK3368(14, 13, 7, false),
  534. [RK3368_PD_GPU_0] = DOMAIN_RK3368(16, 15, 2, false),
  535. [RK3368_PD_GPU_1] = DOMAIN_RK3368(17, 16, 2, false),
  536. };
  537. static const struct rockchip_domain_info rk3399_pm_domains[] = {
  538. [RK3399_PD_TCPD0] = DOMAIN_RK3399(8, 8, -1, false),
  539. [RK3399_PD_TCPD1] = DOMAIN_RK3399(9, 9, -1, false),
  540. [RK3399_PD_CCI] = DOMAIN_RK3399(10, 10, -1, true),
  541. [RK3399_PD_CCI0] = DOMAIN_RK3399(-1, -1, 15, true),
  542. [RK3399_PD_CCI1] = DOMAIN_RK3399(-1, -1, 16, true),
  543. [RK3399_PD_PERILP] = DOMAIN_RK3399(11, 11, 1, true),
  544. [RK3399_PD_PERIHP] = DOMAIN_RK3399(12, 12, 2, true),
  545. [RK3399_PD_CENTER] = DOMAIN_RK3399(13, 13, 14, true),
  546. [RK3399_PD_VIO] = DOMAIN_RK3399(14, 14, 17, false),
  547. [RK3399_PD_GPU] = DOMAIN_RK3399(15, 15, 0, false),
  548. [RK3399_PD_VCODEC] = DOMAIN_RK3399(16, 16, 3, false),
  549. [RK3399_PD_VDU] = DOMAIN_RK3399(17, 17, 4, false),
  550. [RK3399_PD_RGA] = DOMAIN_RK3399(18, 18, 5, false),
  551. [RK3399_PD_IEP] = DOMAIN_RK3399(19, 19, 6, false),
  552. [RK3399_PD_VO] = DOMAIN_RK3399(20, 20, -1, false),
  553. [RK3399_PD_VOPB] = DOMAIN_RK3399(-1, -1, 7, false),
  554. [RK3399_PD_VOPL] = DOMAIN_RK3399(-1, -1, 8, false),
  555. [RK3399_PD_ISP0] = DOMAIN_RK3399(22, 22, 9, false),
  556. [RK3399_PD_ISP1] = DOMAIN_RK3399(23, 23, 10, false),
  557. [RK3399_PD_HDCP] = DOMAIN_RK3399(24, 24, 11, false),
  558. [RK3399_PD_GMAC] = DOMAIN_RK3399(25, 25, 23, true),
  559. [RK3399_PD_EMMC] = DOMAIN_RK3399(26, 26, 24, true),
  560. [RK3399_PD_USB3] = DOMAIN_RK3399(27, 27, 12, true),
  561. [RK3399_PD_EDP] = DOMAIN_RK3399(28, 28, 22, false),
  562. [RK3399_PD_GIC] = DOMAIN_RK3399(29, 29, 27, true),
  563. [RK3399_PD_SD] = DOMAIN_RK3399(30, 30, 28, true),
  564. [RK3399_PD_SDIOAUDIO] = DOMAIN_RK3399(31, 31, 29, true),
  565. };
  566. static const struct rockchip_pmu_info rk3288_pmu = {
  567. .pwr_offset = 0x08,
  568. .status_offset = 0x0c,
  569. .req_offset = 0x10,
  570. .idle_offset = 0x14,
  571. .ack_offset = 0x14,
  572. .core_pwrcnt_offset = 0x34,
  573. .gpu_pwrcnt_offset = 0x3c,
  574. .core_power_transition_time = 24, /* 1us */
  575. .gpu_power_transition_time = 24, /* 1us */
  576. .num_domains = ARRAY_SIZE(rk3288_pm_domains),
  577. .domain_info = rk3288_pm_domains,
  578. };
  579. static const struct rockchip_pmu_info rk3368_pmu = {
  580. .pwr_offset = 0x0c,
  581. .status_offset = 0x10,
  582. .req_offset = 0x3c,
  583. .idle_offset = 0x40,
  584. .ack_offset = 0x40,
  585. .core_pwrcnt_offset = 0x48,
  586. .gpu_pwrcnt_offset = 0x50,
  587. .core_power_transition_time = 24,
  588. .gpu_power_transition_time = 24,
  589. .num_domains = ARRAY_SIZE(rk3368_pm_domains),
  590. .domain_info = rk3368_pm_domains,
  591. };
  592. static const struct rockchip_pmu_info rk3399_pmu = {
  593. .pwr_offset = 0x14,
  594. .status_offset = 0x18,
  595. .req_offset = 0x60,
  596. .idle_offset = 0x64,
  597. .ack_offset = 0x68,
  598. .core_pwrcnt_offset = 0x9c,
  599. .gpu_pwrcnt_offset = 0xa4,
  600. .core_power_transition_time = 24,
  601. .gpu_power_transition_time = 24,
  602. .num_domains = ARRAY_SIZE(rk3399_pm_domains),
  603. .domain_info = rk3399_pm_domains,
  604. };
  605. static const struct of_device_id rockchip_pm_domain_dt_match[] = {
  606. {
  607. .compatible = "rockchip,rk3288-power-controller",
  608. .data = (void *)&rk3288_pmu,
  609. },
  610. {
  611. .compatible = "rockchip,rk3368-power-controller",
  612. .data = (void *)&rk3368_pmu,
  613. },
  614. {
  615. .compatible = "rockchip,rk3399-power-controller",
  616. .data = (void *)&rk3399_pmu,
  617. },
  618. { /* sentinel */ },
  619. };
  620. static struct platform_driver rockchip_pm_domain_driver = {
  621. .probe = rockchip_pm_domain_probe,
  622. .driver = {
  623. .name = "rockchip-pm-domain",
  624. .of_match_table = rockchip_pm_domain_dt_match,
  625. /*
  626. * We can't forcibly eject devices form power domain,
  627. * so we can't really remove power domains once they
  628. * were added.
  629. */
  630. .suppress_bind_attrs = true,
  631. },
  632. };
  633. static int __init rockchip_pm_domain_drv_register(void)
  634. {
  635. return platform_driver_register(&rockchip_pm_domain_driver);
  636. }
  637. postcore_initcall(rockchip_pm_domain_drv_register);