s5m8767.c 26 KB

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  1. /*
  2. * s5m8767.c
  3. *
  4. * Copyright (c) 2011 Samsung Electronics Co., Ltd
  5. * http://www.samsung.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. *
  12. */
  13. #include <linux/err.h>
  14. #include <linux/of_gpio.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/regulator/driver.h>
  18. #include <linux/regulator/machine.h>
  19. #include <linux/mfd/samsung/core.h>
  20. #include <linux/mfd/samsung/s5m8767.h>
  21. #include <linux/regulator/of_regulator.h>
  22. #include <linux/regmap.h>
  23. #define S5M8767_OPMODE_NORMAL_MODE 0x1
  24. struct s5m8767_info {
  25. struct device *dev;
  26. struct sec_pmic_dev *iodev;
  27. int num_regulators;
  28. struct sec_opmode_data *opmode;
  29. int ramp_delay;
  30. bool buck2_ramp;
  31. bool buck3_ramp;
  32. bool buck4_ramp;
  33. bool buck2_gpiodvs;
  34. bool buck3_gpiodvs;
  35. bool buck4_gpiodvs;
  36. u8 buck2_vol[8];
  37. u8 buck3_vol[8];
  38. u8 buck4_vol[8];
  39. int buck_gpios[3];
  40. int buck_ds[3];
  41. int buck_gpioindex;
  42. };
  43. struct sec_voltage_desc {
  44. int max;
  45. int min;
  46. int step;
  47. };
  48. static const struct sec_voltage_desc buck_voltage_val1 = {
  49. .max = 2225000,
  50. .min = 650000,
  51. .step = 6250,
  52. };
  53. static const struct sec_voltage_desc buck_voltage_val2 = {
  54. .max = 1600000,
  55. .min = 600000,
  56. .step = 6250,
  57. };
  58. static const struct sec_voltage_desc buck_voltage_val3 = {
  59. .max = 3000000,
  60. .min = 750000,
  61. .step = 12500,
  62. };
  63. static const struct sec_voltage_desc ldo_voltage_val1 = {
  64. .max = 3950000,
  65. .min = 800000,
  66. .step = 50000,
  67. };
  68. static const struct sec_voltage_desc ldo_voltage_val2 = {
  69. .max = 2375000,
  70. .min = 800000,
  71. .step = 25000,
  72. };
  73. static const struct sec_voltage_desc *reg_voltage_map[] = {
  74. [S5M8767_LDO1] = &ldo_voltage_val2,
  75. [S5M8767_LDO2] = &ldo_voltage_val2,
  76. [S5M8767_LDO3] = &ldo_voltage_val1,
  77. [S5M8767_LDO4] = &ldo_voltage_val1,
  78. [S5M8767_LDO5] = &ldo_voltage_val1,
  79. [S5M8767_LDO6] = &ldo_voltage_val2,
  80. [S5M8767_LDO7] = &ldo_voltage_val2,
  81. [S5M8767_LDO8] = &ldo_voltage_val2,
  82. [S5M8767_LDO9] = &ldo_voltage_val1,
  83. [S5M8767_LDO10] = &ldo_voltage_val1,
  84. [S5M8767_LDO11] = &ldo_voltage_val1,
  85. [S5M8767_LDO12] = &ldo_voltage_val1,
  86. [S5M8767_LDO13] = &ldo_voltage_val1,
  87. [S5M8767_LDO14] = &ldo_voltage_val1,
  88. [S5M8767_LDO15] = &ldo_voltage_val2,
  89. [S5M8767_LDO16] = &ldo_voltage_val1,
  90. [S5M8767_LDO17] = &ldo_voltage_val1,
  91. [S5M8767_LDO18] = &ldo_voltage_val1,
  92. [S5M8767_LDO19] = &ldo_voltage_val1,
  93. [S5M8767_LDO20] = &ldo_voltage_val1,
  94. [S5M8767_LDO21] = &ldo_voltage_val1,
  95. [S5M8767_LDO22] = &ldo_voltage_val1,
  96. [S5M8767_LDO23] = &ldo_voltage_val1,
  97. [S5M8767_LDO24] = &ldo_voltage_val1,
  98. [S5M8767_LDO25] = &ldo_voltage_val1,
  99. [S5M8767_LDO26] = &ldo_voltage_val1,
  100. [S5M8767_LDO27] = &ldo_voltage_val1,
  101. [S5M8767_LDO28] = &ldo_voltage_val1,
  102. [S5M8767_BUCK1] = &buck_voltage_val1,
  103. [S5M8767_BUCK2] = &buck_voltage_val2,
  104. [S5M8767_BUCK3] = &buck_voltage_val2,
  105. [S5M8767_BUCK4] = &buck_voltage_val2,
  106. [S5M8767_BUCK5] = &buck_voltage_val1,
  107. [S5M8767_BUCK6] = &buck_voltage_val1,
  108. [S5M8767_BUCK7] = &buck_voltage_val3,
  109. [S5M8767_BUCK8] = &buck_voltage_val3,
  110. [S5M8767_BUCK9] = &buck_voltage_val3,
  111. };
  112. static unsigned int s5m8767_opmode_reg[][4] = {
  113. /* {OFF, ON, LOWPOWER, SUSPEND} */
  114. /* LDO1 ... LDO28 */
  115. {0x0, 0x3, 0x2, 0x1}, /* LDO1 */
  116. {0x0, 0x3, 0x2, 0x1},
  117. {0x0, 0x3, 0x2, 0x1},
  118. {0x0, 0x0, 0x0, 0x0},
  119. {0x0, 0x3, 0x2, 0x1}, /* LDO5 */
  120. {0x0, 0x3, 0x2, 0x1},
  121. {0x0, 0x3, 0x2, 0x1},
  122. {0x0, 0x3, 0x2, 0x1},
  123. {0x0, 0x3, 0x2, 0x1},
  124. {0x0, 0x3, 0x2, 0x1}, /* LDO10 */
  125. {0x0, 0x3, 0x2, 0x1},
  126. {0x0, 0x3, 0x2, 0x1},
  127. {0x0, 0x3, 0x2, 0x1},
  128. {0x0, 0x3, 0x2, 0x1},
  129. {0x0, 0x3, 0x2, 0x1}, /* LDO15 */
  130. {0x0, 0x3, 0x2, 0x1},
  131. {0x0, 0x3, 0x2, 0x1},
  132. {0x0, 0x0, 0x0, 0x0},
  133. {0x0, 0x3, 0x2, 0x1},
  134. {0x0, 0x3, 0x2, 0x1}, /* LDO20 */
  135. {0x0, 0x3, 0x2, 0x1},
  136. {0x0, 0x3, 0x2, 0x1},
  137. {0x0, 0x0, 0x0, 0x0},
  138. {0x0, 0x3, 0x2, 0x1},
  139. {0x0, 0x3, 0x2, 0x1}, /* LDO25 */
  140. {0x0, 0x3, 0x2, 0x1},
  141. {0x0, 0x3, 0x2, 0x1},
  142. {0x0, 0x3, 0x2, 0x1}, /* LDO28 */
  143. /* BUCK1 ... BUCK9 */
  144. {0x0, 0x3, 0x1, 0x1}, /* BUCK1 */
  145. {0x0, 0x3, 0x1, 0x1},
  146. {0x0, 0x3, 0x1, 0x1},
  147. {0x0, 0x3, 0x1, 0x1},
  148. {0x0, 0x3, 0x2, 0x1}, /* BUCK5 */
  149. {0x0, 0x3, 0x1, 0x1},
  150. {0x0, 0x3, 0x1, 0x1},
  151. {0x0, 0x3, 0x1, 0x1},
  152. {0x0, 0x3, 0x1, 0x1}, /* BUCK9 */
  153. };
  154. static int s5m8767_get_register(struct s5m8767_info *s5m8767, int reg_id,
  155. int *reg, int *enable_ctrl)
  156. {
  157. int i;
  158. unsigned int mode;
  159. switch (reg_id) {
  160. case S5M8767_LDO1 ... S5M8767_LDO2:
  161. *reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  162. break;
  163. case S5M8767_LDO3 ... S5M8767_LDO28:
  164. *reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  165. break;
  166. case S5M8767_BUCK1:
  167. *reg = S5M8767_REG_BUCK1CTRL1;
  168. break;
  169. case S5M8767_BUCK2 ... S5M8767_BUCK4:
  170. *reg = S5M8767_REG_BUCK2CTRL + (reg_id - S5M8767_BUCK2) * 9;
  171. break;
  172. case S5M8767_BUCK5:
  173. *reg = S5M8767_REG_BUCK5CTRL1;
  174. break;
  175. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  176. *reg = S5M8767_REG_BUCK6CTRL1 + (reg_id - S5M8767_BUCK6) * 2;
  177. break;
  178. default:
  179. return -EINVAL;
  180. }
  181. for (i = 0; i < s5m8767->num_regulators; i++) {
  182. if (s5m8767->opmode[i].id == reg_id) {
  183. mode = s5m8767->opmode[i].mode;
  184. break;
  185. }
  186. }
  187. if (i >= s5m8767->num_regulators)
  188. return -EINVAL;
  189. *enable_ctrl = s5m8767_opmode_reg[reg_id][mode] << S5M8767_ENCTRL_SHIFT;
  190. return 0;
  191. }
  192. static int s5m8767_get_vsel_reg(int reg_id, struct s5m8767_info *s5m8767)
  193. {
  194. int reg;
  195. switch (reg_id) {
  196. case S5M8767_LDO1 ... S5M8767_LDO2:
  197. reg = S5M8767_REG_LDO1CTRL + (reg_id - S5M8767_LDO1);
  198. break;
  199. case S5M8767_LDO3 ... S5M8767_LDO28:
  200. reg = S5M8767_REG_LDO3CTRL + (reg_id - S5M8767_LDO3);
  201. break;
  202. case S5M8767_BUCK1:
  203. reg = S5M8767_REG_BUCK1CTRL2;
  204. break;
  205. case S5M8767_BUCK2:
  206. reg = S5M8767_REG_BUCK2DVS1;
  207. if (s5m8767->buck2_gpiodvs)
  208. reg += s5m8767->buck_gpioindex;
  209. break;
  210. case S5M8767_BUCK3:
  211. reg = S5M8767_REG_BUCK3DVS1;
  212. if (s5m8767->buck3_gpiodvs)
  213. reg += s5m8767->buck_gpioindex;
  214. break;
  215. case S5M8767_BUCK4:
  216. reg = S5M8767_REG_BUCK4DVS1;
  217. if (s5m8767->buck4_gpiodvs)
  218. reg += s5m8767->buck_gpioindex;
  219. break;
  220. case S5M8767_BUCK5:
  221. reg = S5M8767_REG_BUCK5CTRL2;
  222. break;
  223. case S5M8767_BUCK6 ... S5M8767_BUCK9:
  224. reg = S5M8767_REG_BUCK6CTRL2 + (reg_id - S5M8767_BUCK6) * 2;
  225. break;
  226. default:
  227. return -EINVAL;
  228. }
  229. return reg;
  230. }
  231. static int s5m8767_convert_voltage_to_sel(const struct sec_voltage_desc *desc,
  232. int min_vol)
  233. {
  234. int selector = 0;
  235. if (desc == NULL)
  236. return -EINVAL;
  237. if (min_vol > desc->max)
  238. return -EINVAL;
  239. if (min_vol < desc->min)
  240. min_vol = desc->min;
  241. selector = DIV_ROUND_UP(min_vol - desc->min, desc->step);
  242. if (desc->min + desc->step * selector > desc->max)
  243. return -EINVAL;
  244. return selector;
  245. }
  246. static inline int s5m8767_set_high(struct s5m8767_info *s5m8767)
  247. {
  248. int temp_index = s5m8767->buck_gpioindex;
  249. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  250. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  251. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  252. return 0;
  253. }
  254. static inline int s5m8767_set_low(struct s5m8767_info *s5m8767)
  255. {
  256. int temp_index = s5m8767->buck_gpioindex;
  257. gpio_set_value(s5m8767->buck_gpios[2], temp_index & 0x1);
  258. gpio_set_value(s5m8767->buck_gpios[1], (temp_index >> 1) & 0x1);
  259. gpio_set_value(s5m8767->buck_gpios[0], (temp_index >> 2) & 0x1);
  260. return 0;
  261. }
  262. static int s5m8767_set_voltage_sel(struct regulator_dev *rdev,
  263. unsigned selector)
  264. {
  265. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  266. int reg_id = rdev_get_id(rdev);
  267. int old_index, index = 0;
  268. u8 *buck234_vol = NULL;
  269. switch (reg_id) {
  270. case S5M8767_LDO1 ... S5M8767_LDO28:
  271. break;
  272. case S5M8767_BUCK1 ... S5M8767_BUCK6:
  273. if (reg_id == S5M8767_BUCK2 && s5m8767->buck2_gpiodvs)
  274. buck234_vol = &s5m8767->buck2_vol[0];
  275. else if (reg_id == S5M8767_BUCK3 && s5m8767->buck3_gpiodvs)
  276. buck234_vol = &s5m8767->buck3_vol[0];
  277. else if (reg_id == S5M8767_BUCK4 && s5m8767->buck4_gpiodvs)
  278. buck234_vol = &s5m8767->buck4_vol[0];
  279. break;
  280. case S5M8767_BUCK7 ... S5M8767_BUCK8:
  281. return -EINVAL;
  282. case S5M8767_BUCK9:
  283. break;
  284. default:
  285. return -EINVAL;
  286. }
  287. /* buck234_vol != NULL means to control buck234 voltage via DVS GPIO */
  288. if (buck234_vol) {
  289. while (*buck234_vol != selector) {
  290. buck234_vol++;
  291. index++;
  292. }
  293. old_index = s5m8767->buck_gpioindex;
  294. s5m8767->buck_gpioindex = index;
  295. if (index > old_index)
  296. return s5m8767_set_high(s5m8767);
  297. else
  298. return s5m8767_set_low(s5m8767);
  299. } else {
  300. return regulator_set_voltage_sel_regmap(rdev, selector);
  301. }
  302. }
  303. static int s5m8767_set_voltage_time_sel(struct regulator_dev *rdev,
  304. unsigned int old_sel,
  305. unsigned int new_sel)
  306. {
  307. struct s5m8767_info *s5m8767 = rdev_get_drvdata(rdev);
  308. const struct sec_voltage_desc *desc;
  309. int reg_id = rdev_get_id(rdev);
  310. desc = reg_voltage_map[reg_id];
  311. if ((old_sel < new_sel) && s5m8767->ramp_delay)
  312. return DIV_ROUND_UP(desc->step * (new_sel - old_sel),
  313. s5m8767->ramp_delay * 1000);
  314. return 0;
  315. }
  316. static struct regulator_ops s5m8767_ops = {
  317. .list_voltage = regulator_list_voltage_linear,
  318. .is_enabled = regulator_is_enabled_regmap,
  319. .enable = regulator_enable_regmap,
  320. .disable = regulator_disable_regmap,
  321. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  322. .set_voltage_sel = s5m8767_set_voltage_sel,
  323. .set_voltage_time_sel = s5m8767_set_voltage_time_sel,
  324. };
  325. static struct regulator_ops s5m8767_buck78_ops = {
  326. .list_voltage = regulator_list_voltage_linear,
  327. .is_enabled = regulator_is_enabled_regmap,
  328. .enable = regulator_enable_regmap,
  329. .disable = regulator_disable_regmap,
  330. .get_voltage_sel = regulator_get_voltage_sel_regmap,
  331. .set_voltage_sel = regulator_set_voltage_sel_regmap,
  332. };
  333. #define s5m8767_regulator_desc(_name) { \
  334. .name = #_name, \
  335. .id = S5M8767_##_name, \
  336. .ops = &s5m8767_ops, \
  337. .type = REGULATOR_VOLTAGE, \
  338. .owner = THIS_MODULE, \
  339. }
  340. #define s5m8767_regulator_buck78_desc(_name) { \
  341. .name = #_name, \
  342. .id = S5M8767_##_name, \
  343. .ops = &s5m8767_buck78_ops, \
  344. .type = REGULATOR_VOLTAGE, \
  345. .owner = THIS_MODULE, \
  346. }
  347. static struct regulator_desc regulators[] = {
  348. s5m8767_regulator_desc(LDO1),
  349. s5m8767_regulator_desc(LDO2),
  350. s5m8767_regulator_desc(LDO3),
  351. s5m8767_regulator_desc(LDO4),
  352. s5m8767_regulator_desc(LDO5),
  353. s5m8767_regulator_desc(LDO6),
  354. s5m8767_regulator_desc(LDO7),
  355. s5m8767_regulator_desc(LDO8),
  356. s5m8767_regulator_desc(LDO9),
  357. s5m8767_regulator_desc(LDO10),
  358. s5m8767_regulator_desc(LDO11),
  359. s5m8767_regulator_desc(LDO12),
  360. s5m8767_regulator_desc(LDO13),
  361. s5m8767_regulator_desc(LDO14),
  362. s5m8767_regulator_desc(LDO15),
  363. s5m8767_regulator_desc(LDO16),
  364. s5m8767_regulator_desc(LDO17),
  365. s5m8767_regulator_desc(LDO18),
  366. s5m8767_regulator_desc(LDO19),
  367. s5m8767_regulator_desc(LDO20),
  368. s5m8767_regulator_desc(LDO21),
  369. s5m8767_regulator_desc(LDO22),
  370. s5m8767_regulator_desc(LDO23),
  371. s5m8767_regulator_desc(LDO24),
  372. s5m8767_regulator_desc(LDO25),
  373. s5m8767_regulator_desc(LDO26),
  374. s5m8767_regulator_desc(LDO27),
  375. s5m8767_regulator_desc(LDO28),
  376. s5m8767_regulator_desc(BUCK1),
  377. s5m8767_regulator_desc(BUCK2),
  378. s5m8767_regulator_desc(BUCK3),
  379. s5m8767_regulator_desc(BUCK4),
  380. s5m8767_regulator_desc(BUCK5),
  381. s5m8767_regulator_desc(BUCK6),
  382. s5m8767_regulator_buck78_desc(BUCK7),
  383. s5m8767_regulator_buck78_desc(BUCK8),
  384. s5m8767_regulator_desc(BUCK9),
  385. };
  386. /*
  387. * Enable GPIO control over BUCK9 in regulator_config for that regulator.
  388. */
  389. static void s5m8767_regulator_config_ext_control(struct s5m8767_info *s5m8767,
  390. struct sec_regulator_data *rdata,
  391. struct regulator_config *config)
  392. {
  393. int i, mode = 0;
  394. if (rdata->id != S5M8767_BUCK9)
  395. return;
  396. /* Check if opmode for regulator matches S5M8767_ENCTRL_USE_GPIO */
  397. for (i = 0; i < s5m8767->num_regulators; i++) {
  398. const struct sec_opmode_data *opmode = &s5m8767->opmode[i];
  399. if (opmode->id == rdata->id) {
  400. mode = s5m8767_opmode_reg[rdata->id][opmode->mode];
  401. break;
  402. }
  403. }
  404. if (mode != S5M8767_ENCTRL_USE_GPIO) {
  405. dev_warn(s5m8767->dev,
  406. "ext-control for %s: mismatched op_mode (%x), ignoring\n",
  407. rdata->reg_node->name, mode);
  408. return;
  409. }
  410. if (!gpio_is_valid(rdata->ext_control_gpio)) {
  411. dev_warn(s5m8767->dev,
  412. "ext-control for %s: GPIO not valid, ignoring\n",
  413. rdata->reg_node->name);
  414. return;
  415. }
  416. config->ena_gpio = rdata->ext_control_gpio;
  417. config->ena_gpio_flags = GPIOF_OUT_INIT_HIGH;
  418. }
  419. /*
  420. * Turn on GPIO control over BUCK9.
  421. */
  422. static int s5m8767_enable_ext_control(struct s5m8767_info *s5m8767,
  423. struct regulator_dev *rdev)
  424. {
  425. int id = rdev_get_id(rdev);
  426. int ret, reg, enable_ctrl;
  427. if (id != S5M8767_BUCK9)
  428. return -EINVAL;
  429. ret = s5m8767_get_register(s5m8767, id, &reg, &enable_ctrl);
  430. if (ret)
  431. return ret;
  432. return regmap_update_bits(s5m8767->iodev->regmap_pmic,
  433. reg, S5M8767_ENCTRL_MASK,
  434. S5M8767_ENCTRL_USE_GPIO << S5M8767_ENCTRL_SHIFT);
  435. }
  436. #ifdef CONFIG_OF
  437. static int s5m8767_pmic_dt_parse_dvs_gpio(struct sec_pmic_dev *iodev,
  438. struct sec_platform_data *pdata,
  439. struct device_node *pmic_np)
  440. {
  441. int i, gpio;
  442. for (i = 0; i < 3; i++) {
  443. gpio = of_get_named_gpio(pmic_np,
  444. "s5m8767,pmic-buck-dvs-gpios", i);
  445. if (!gpio_is_valid(gpio)) {
  446. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  447. return -EINVAL;
  448. }
  449. pdata->buck_gpios[i] = gpio;
  450. }
  451. return 0;
  452. }
  453. static int s5m8767_pmic_dt_parse_ds_gpio(struct sec_pmic_dev *iodev,
  454. struct sec_platform_data *pdata,
  455. struct device_node *pmic_np)
  456. {
  457. int i, gpio;
  458. for (i = 0; i < 3; i++) {
  459. gpio = of_get_named_gpio(pmic_np,
  460. "s5m8767,pmic-buck-ds-gpios", i);
  461. if (!gpio_is_valid(gpio)) {
  462. dev_err(iodev->dev, "invalid gpio[%d]: %d\n", i, gpio);
  463. return -EINVAL;
  464. }
  465. pdata->buck_ds[i] = gpio;
  466. }
  467. return 0;
  468. }
  469. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  470. struct sec_platform_data *pdata)
  471. {
  472. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  473. struct device_node *pmic_np, *regulators_np, *reg_np;
  474. struct sec_regulator_data *rdata;
  475. struct sec_opmode_data *rmode;
  476. unsigned int i, dvs_voltage_nr = 8, ret;
  477. pmic_np = iodev->dev->of_node;
  478. if (!pmic_np) {
  479. dev_err(iodev->dev, "could not find pmic sub-node\n");
  480. return -ENODEV;
  481. }
  482. regulators_np = of_get_child_by_name(pmic_np, "regulators");
  483. if (!regulators_np) {
  484. dev_err(iodev->dev, "could not find regulators sub-node\n");
  485. return -EINVAL;
  486. }
  487. /* count the number of regulators to be supported in pmic */
  488. pdata->num_regulators = of_get_child_count(regulators_np);
  489. rdata = devm_kzalloc(&pdev->dev, sizeof(*rdata) *
  490. pdata->num_regulators, GFP_KERNEL);
  491. if (!rdata)
  492. return -ENOMEM;
  493. rmode = devm_kzalloc(&pdev->dev, sizeof(*rmode) *
  494. pdata->num_regulators, GFP_KERNEL);
  495. if (!rmode)
  496. return -ENOMEM;
  497. pdata->regulators = rdata;
  498. pdata->opmode = rmode;
  499. for_each_child_of_node(regulators_np, reg_np) {
  500. for (i = 0; i < ARRAY_SIZE(regulators); i++)
  501. if (!of_node_cmp(reg_np->name, regulators[i].name))
  502. break;
  503. if (i == ARRAY_SIZE(regulators)) {
  504. dev_warn(iodev->dev,
  505. "don't know how to configure regulator %s\n",
  506. reg_np->name);
  507. continue;
  508. }
  509. rdata->ext_control_gpio = of_get_named_gpio(reg_np,
  510. "s5m8767,pmic-ext-control-gpios", 0);
  511. rdata->id = i;
  512. rdata->initdata = of_get_regulator_init_data(
  513. &pdev->dev, reg_np,
  514. &regulators[i]);
  515. rdata->reg_node = reg_np;
  516. rdata++;
  517. rmode->id = i;
  518. if (of_property_read_u32(reg_np, "op_mode",
  519. &rmode->mode)) {
  520. dev_warn(iodev->dev,
  521. "no op_mode property property at %s\n",
  522. reg_np->full_name);
  523. rmode->mode = S5M8767_OPMODE_NORMAL_MODE;
  524. }
  525. rmode++;
  526. }
  527. of_node_put(regulators_np);
  528. if (of_get_property(pmic_np, "s5m8767,pmic-buck2-uses-gpio-dvs", NULL)) {
  529. pdata->buck2_gpiodvs = true;
  530. if (of_property_read_u32_array(pmic_np,
  531. "s5m8767,pmic-buck2-dvs-voltage",
  532. pdata->buck2_voltage, dvs_voltage_nr)) {
  533. dev_err(iodev->dev, "buck2 voltages not specified\n");
  534. return -EINVAL;
  535. }
  536. }
  537. if (of_get_property(pmic_np, "s5m8767,pmic-buck3-uses-gpio-dvs", NULL)) {
  538. pdata->buck3_gpiodvs = true;
  539. if (of_property_read_u32_array(pmic_np,
  540. "s5m8767,pmic-buck3-dvs-voltage",
  541. pdata->buck3_voltage, dvs_voltage_nr)) {
  542. dev_err(iodev->dev, "buck3 voltages not specified\n");
  543. return -EINVAL;
  544. }
  545. }
  546. if (of_get_property(pmic_np, "s5m8767,pmic-buck4-uses-gpio-dvs", NULL)) {
  547. pdata->buck4_gpiodvs = true;
  548. if (of_property_read_u32_array(pmic_np,
  549. "s5m8767,pmic-buck4-dvs-voltage",
  550. pdata->buck4_voltage, dvs_voltage_nr)) {
  551. dev_err(iodev->dev, "buck4 voltages not specified\n");
  552. return -EINVAL;
  553. }
  554. }
  555. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  556. pdata->buck4_gpiodvs) {
  557. ret = s5m8767_pmic_dt_parse_dvs_gpio(iodev, pdata, pmic_np);
  558. if (ret)
  559. return -EINVAL;
  560. if (of_property_read_u32(pmic_np,
  561. "s5m8767,pmic-buck-default-dvs-idx",
  562. &pdata->buck_default_idx)) {
  563. pdata->buck_default_idx = 0;
  564. } else {
  565. if (pdata->buck_default_idx >= 8) {
  566. pdata->buck_default_idx = 0;
  567. dev_info(iodev->dev,
  568. "invalid value for default dvs index, use 0\n");
  569. }
  570. }
  571. }
  572. ret = s5m8767_pmic_dt_parse_ds_gpio(iodev, pdata, pmic_np);
  573. if (ret)
  574. return -EINVAL;
  575. if (of_get_property(pmic_np, "s5m8767,pmic-buck2-ramp-enable", NULL))
  576. pdata->buck2_ramp_enable = true;
  577. if (of_get_property(pmic_np, "s5m8767,pmic-buck3-ramp-enable", NULL))
  578. pdata->buck3_ramp_enable = true;
  579. if (of_get_property(pmic_np, "s5m8767,pmic-buck4-ramp-enable", NULL))
  580. pdata->buck4_ramp_enable = true;
  581. if (pdata->buck2_ramp_enable || pdata->buck3_ramp_enable
  582. || pdata->buck4_ramp_enable) {
  583. if (of_property_read_u32(pmic_np, "s5m8767,pmic-buck-ramp-delay",
  584. &pdata->buck_ramp_delay))
  585. pdata->buck_ramp_delay = 0;
  586. }
  587. return 0;
  588. }
  589. #else
  590. static int s5m8767_pmic_dt_parse_pdata(struct platform_device *pdev,
  591. struct sec_platform_data *pdata)
  592. {
  593. return 0;
  594. }
  595. #endif /* CONFIG_OF */
  596. static int s5m8767_pmic_probe(struct platform_device *pdev)
  597. {
  598. struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
  599. struct sec_platform_data *pdata = iodev->pdata;
  600. struct regulator_config config = { };
  601. struct s5m8767_info *s5m8767;
  602. int i, ret, buck_init;
  603. if (!pdata) {
  604. dev_err(pdev->dev.parent, "Platform data not supplied\n");
  605. return -ENODEV;
  606. }
  607. if (iodev->dev->of_node) {
  608. ret = s5m8767_pmic_dt_parse_pdata(pdev, pdata);
  609. if (ret)
  610. return ret;
  611. }
  612. if (pdata->buck2_gpiodvs) {
  613. if (pdata->buck3_gpiodvs || pdata->buck4_gpiodvs) {
  614. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  615. return -EINVAL;
  616. }
  617. }
  618. if (pdata->buck3_gpiodvs) {
  619. if (pdata->buck2_gpiodvs || pdata->buck4_gpiodvs) {
  620. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  621. return -EINVAL;
  622. }
  623. }
  624. if (pdata->buck4_gpiodvs) {
  625. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs) {
  626. dev_err(&pdev->dev, "S5M8767 GPIO DVS NOT VALID\n");
  627. return -EINVAL;
  628. }
  629. }
  630. s5m8767 = devm_kzalloc(&pdev->dev, sizeof(struct s5m8767_info),
  631. GFP_KERNEL);
  632. if (!s5m8767)
  633. return -ENOMEM;
  634. s5m8767->dev = &pdev->dev;
  635. s5m8767->iodev = iodev;
  636. s5m8767->num_regulators = pdata->num_regulators;
  637. platform_set_drvdata(pdev, s5m8767);
  638. s5m8767->buck_gpioindex = pdata->buck_default_idx;
  639. s5m8767->buck2_gpiodvs = pdata->buck2_gpiodvs;
  640. s5m8767->buck3_gpiodvs = pdata->buck3_gpiodvs;
  641. s5m8767->buck4_gpiodvs = pdata->buck4_gpiodvs;
  642. s5m8767->buck_gpios[0] = pdata->buck_gpios[0];
  643. s5m8767->buck_gpios[1] = pdata->buck_gpios[1];
  644. s5m8767->buck_gpios[2] = pdata->buck_gpios[2];
  645. s5m8767->buck_ds[0] = pdata->buck_ds[0];
  646. s5m8767->buck_ds[1] = pdata->buck_ds[1];
  647. s5m8767->buck_ds[2] = pdata->buck_ds[2];
  648. s5m8767->ramp_delay = pdata->buck_ramp_delay;
  649. s5m8767->buck2_ramp = pdata->buck2_ramp_enable;
  650. s5m8767->buck3_ramp = pdata->buck3_ramp_enable;
  651. s5m8767->buck4_ramp = pdata->buck4_ramp_enable;
  652. s5m8767->opmode = pdata->opmode;
  653. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  654. pdata->buck2_init);
  655. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK2DVS2,
  656. buck_init);
  657. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  658. pdata->buck3_init);
  659. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK3DVS2,
  660. buck_init);
  661. buck_init = s5m8767_convert_voltage_to_sel(&buck_voltage_val2,
  662. pdata->buck4_init);
  663. regmap_write(s5m8767->iodev->regmap_pmic, S5M8767_REG_BUCK4DVS2,
  664. buck_init);
  665. for (i = 0; i < 8; i++) {
  666. if (s5m8767->buck2_gpiodvs) {
  667. s5m8767->buck2_vol[i] =
  668. s5m8767_convert_voltage_to_sel(
  669. &buck_voltage_val2,
  670. pdata->buck2_voltage[i]);
  671. }
  672. if (s5m8767->buck3_gpiodvs) {
  673. s5m8767->buck3_vol[i] =
  674. s5m8767_convert_voltage_to_sel(
  675. &buck_voltage_val2,
  676. pdata->buck3_voltage[i]);
  677. }
  678. if (s5m8767->buck4_gpiodvs) {
  679. s5m8767->buck4_vol[i] =
  680. s5m8767_convert_voltage_to_sel(
  681. &buck_voltage_val2,
  682. pdata->buck4_voltage[i]);
  683. }
  684. }
  685. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  686. pdata->buck4_gpiodvs) {
  687. if (!gpio_is_valid(pdata->buck_gpios[0]) ||
  688. !gpio_is_valid(pdata->buck_gpios[1]) ||
  689. !gpio_is_valid(pdata->buck_gpios[2])) {
  690. dev_err(&pdev->dev, "GPIO NOT VALID\n");
  691. return -EINVAL;
  692. }
  693. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[0],
  694. "S5M8767 SET1");
  695. if (ret)
  696. return ret;
  697. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[1],
  698. "S5M8767 SET2");
  699. if (ret)
  700. return ret;
  701. ret = devm_gpio_request(&pdev->dev, pdata->buck_gpios[2],
  702. "S5M8767 SET3");
  703. if (ret)
  704. return ret;
  705. /* SET1 GPIO */
  706. gpio_direction_output(pdata->buck_gpios[0],
  707. (s5m8767->buck_gpioindex >> 2) & 0x1);
  708. /* SET2 GPIO */
  709. gpio_direction_output(pdata->buck_gpios[1],
  710. (s5m8767->buck_gpioindex >> 1) & 0x1);
  711. /* SET3 GPIO */
  712. gpio_direction_output(pdata->buck_gpios[2],
  713. (s5m8767->buck_gpioindex >> 0) & 0x1);
  714. }
  715. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[0], "S5M8767 DS2");
  716. if (ret)
  717. return ret;
  718. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[1], "S5M8767 DS3");
  719. if (ret)
  720. return ret;
  721. ret = devm_gpio_request(&pdev->dev, pdata->buck_ds[2], "S5M8767 DS4");
  722. if (ret)
  723. return ret;
  724. /* DS2 GPIO */
  725. gpio_direction_output(pdata->buck_ds[0], 0x0);
  726. /* DS3 GPIO */
  727. gpio_direction_output(pdata->buck_ds[1], 0x0);
  728. /* DS4 GPIO */
  729. gpio_direction_output(pdata->buck_ds[2], 0x0);
  730. if (pdata->buck2_gpiodvs || pdata->buck3_gpiodvs ||
  731. pdata->buck4_gpiodvs) {
  732. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  733. S5M8767_REG_BUCK2CTRL, 1 << 1,
  734. (pdata->buck2_gpiodvs) ? (1 << 1) : (0 << 1));
  735. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  736. S5M8767_REG_BUCK3CTRL, 1 << 1,
  737. (pdata->buck3_gpiodvs) ? (1 << 1) : (0 << 1));
  738. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  739. S5M8767_REG_BUCK4CTRL, 1 << 1,
  740. (pdata->buck4_gpiodvs) ? (1 << 1) : (0 << 1));
  741. }
  742. /* Initialize GPIO DVS registers */
  743. for (i = 0; i < 8; i++) {
  744. if (s5m8767->buck2_gpiodvs) {
  745. regmap_write(s5m8767->iodev->regmap_pmic,
  746. S5M8767_REG_BUCK2DVS1 + i,
  747. s5m8767->buck2_vol[i]);
  748. }
  749. if (s5m8767->buck3_gpiodvs) {
  750. regmap_write(s5m8767->iodev->regmap_pmic,
  751. S5M8767_REG_BUCK3DVS1 + i,
  752. s5m8767->buck3_vol[i]);
  753. }
  754. if (s5m8767->buck4_gpiodvs) {
  755. regmap_write(s5m8767->iodev->regmap_pmic,
  756. S5M8767_REG_BUCK4DVS1 + i,
  757. s5m8767->buck4_vol[i]);
  758. }
  759. }
  760. if (s5m8767->buck2_ramp)
  761. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  762. S5M8767_REG_DVSRAMP, 0x08, 0x08);
  763. if (s5m8767->buck3_ramp)
  764. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  765. S5M8767_REG_DVSRAMP, 0x04, 0x04);
  766. if (s5m8767->buck4_ramp)
  767. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  768. S5M8767_REG_DVSRAMP, 0x02, 0x02);
  769. if (s5m8767->buck2_ramp || s5m8767->buck3_ramp
  770. || s5m8767->buck4_ramp) {
  771. unsigned int val;
  772. switch (s5m8767->ramp_delay) {
  773. case 5:
  774. val = S5M8767_DVS_BUCK_RAMP_5;
  775. break;
  776. case 10:
  777. val = S5M8767_DVS_BUCK_RAMP_10;
  778. break;
  779. case 25:
  780. val = S5M8767_DVS_BUCK_RAMP_25;
  781. break;
  782. case 50:
  783. val = S5M8767_DVS_BUCK_RAMP_50;
  784. break;
  785. case 100:
  786. val = S5M8767_DVS_BUCK_RAMP_100;
  787. break;
  788. default:
  789. val = S5M8767_DVS_BUCK_RAMP_10;
  790. }
  791. regmap_update_bits(s5m8767->iodev->regmap_pmic,
  792. S5M8767_REG_DVSRAMP,
  793. S5M8767_DVS_BUCK_RAMP_MASK,
  794. val << S5M8767_DVS_BUCK_RAMP_SHIFT);
  795. }
  796. for (i = 0; i < pdata->num_regulators; i++) {
  797. const struct sec_voltage_desc *desc;
  798. int id = pdata->regulators[i].id;
  799. int enable_reg, enable_val;
  800. struct regulator_dev *rdev;
  801. desc = reg_voltage_map[id];
  802. if (desc) {
  803. regulators[id].n_voltages =
  804. (desc->max - desc->min) / desc->step + 1;
  805. regulators[id].min_uV = desc->min;
  806. regulators[id].uV_step = desc->step;
  807. regulators[id].vsel_reg =
  808. s5m8767_get_vsel_reg(id, s5m8767);
  809. if (id < S5M8767_BUCK1)
  810. regulators[id].vsel_mask = 0x3f;
  811. else
  812. regulators[id].vsel_mask = 0xff;
  813. ret = s5m8767_get_register(s5m8767, id, &enable_reg,
  814. &enable_val);
  815. if (ret) {
  816. dev_err(s5m8767->dev, "error reading registers\n");
  817. return ret;
  818. }
  819. regulators[id].enable_reg = enable_reg;
  820. regulators[id].enable_mask = S5M8767_ENCTRL_MASK;
  821. regulators[id].enable_val = enable_val;
  822. }
  823. config.dev = s5m8767->dev;
  824. config.init_data = pdata->regulators[i].initdata;
  825. config.driver_data = s5m8767;
  826. config.regmap = iodev->regmap_pmic;
  827. config.of_node = pdata->regulators[i].reg_node;
  828. config.ena_gpio = -EINVAL;
  829. config.ena_gpio_flags = 0;
  830. config.ena_gpio_initialized = true;
  831. if (gpio_is_valid(pdata->regulators[i].ext_control_gpio))
  832. s5m8767_regulator_config_ext_control(s5m8767,
  833. &pdata->regulators[i], &config);
  834. rdev = devm_regulator_register(&pdev->dev, &regulators[id],
  835. &config);
  836. if (IS_ERR(rdev)) {
  837. ret = PTR_ERR(rdev);
  838. dev_err(s5m8767->dev, "regulator init failed for %d\n",
  839. id);
  840. return ret;
  841. }
  842. if (gpio_is_valid(pdata->regulators[i].ext_control_gpio)) {
  843. ret = s5m8767_enable_ext_control(s5m8767, rdev);
  844. if (ret < 0) {
  845. dev_err(s5m8767->dev,
  846. "failed to enable gpio control over %s: %d\n",
  847. rdev->desc->name, ret);
  848. return ret;
  849. }
  850. }
  851. }
  852. return 0;
  853. }
  854. static const struct platform_device_id s5m8767_pmic_id[] = {
  855. { "s5m8767-pmic", 0},
  856. { },
  857. };
  858. MODULE_DEVICE_TABLE(platform, s5m8767_pmic_id);
  859. static struct platform_driver s5m8767_pmic_driver = {
  860. .driver = {
  861. .name = "s5m8767-pmic",
  862. },
  863. .probe = s5m8767_pmic_probe,
  864. .id_table = s5m8767_pmic_id,
  865. };
  866. static int __init s5m8767_pmic_init(void)
  867. {
  868. return platform_driver_register(&s5m8767_pmic_driver);
  869. }
  870. subsys_initcall(s5m8767_pmic_init);
  871. static void __exit s5m8767_pmic_exit(void)
  872. {
  873. platform_driver_unregister(&s5m8767_pmic_driver);
  874. }
  875. module_exit(s5m8767_pmic_exit);
  876. /* Module information */
  877. MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
  878. MODULE_DESCRIPTION("SAMSUNG S5M8767 Regulator Driver");
  879. MODULE_LICENSE("GPL");