at91-sama5d2_shdwc.c 8.4 KB

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  1. /*
  2. * Atmel SAMA5D2-Compatible Shutdown Controller (SHDWC) driver.
  3. * Found on some SoCs as the sama5d2 (obviously).
  4. *
  5. * Copyright (C) 2015 Atmel Corporation,
  6. * Nicolas Ferre <nicolas.ferre@atmel.com>
  7. *
  8. * Evolved from driver at91-poweroff.c.
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without any
  12. * warranty of any kind, whether express or implied.
  13. *
  14. * TODO:
  15. * - addition to status of other wake-up inputs [1 - 15]
  16. * - Analog Comparator wake-up alarm
  17. * - Serial RX wake-up alarm
  18. * - low power debouncer
  19. */
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <linux/module.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/printk.h>
  27. #include <soc/at91/at91sam9_ddrsdr.h>
  28. #define SLOW_CLOCK_FREQ 32768
  29. #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
  30. #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
  31. #define AT91_SHDW_KEY (0xa5UL << 24) /* KEY Password */
  32. #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
  33. #define AT91_SHDW_WKUPDBC_SHIFT 24
  34. #define AT91_SHDW_WKUPDBC_MASK GENMASK(31, 16)
  35. #define AT91_SHDW_WKUPDBC(x) (((x) << AT91_SHDW_WKUPDBC_SHIFT) \
  36. & AT91_SHDW_WKUPDBC_MASK)
  37. #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
  38. #define AT91_SHDW_WKUPIS_SHIFT 16
  39. #define AT91_SHDW_WKUPIS_MASK GENMASK(31, 16)
  40. #define AT91_SHDW_WKUPIS(x) ((1 << (x)) << AT91_SHDW_WKUPIS_SHIFT \
  41. & AT91_SHDW_WKUPIS_MASK)
  42. #define AT91_SHDW_WUIR 0x0c /* Shutdown Wake-up Inputs Register */
  43. #define AT91_SHDW_WKUPEN_MASK GENMASK(15, 0)
  44. #define AT91_SHDW_WKUPEN(x) ((1 << (x)) & AT91_SHDW_WKUPEN_MASK)
  45. #define AT91_SHDW_WKUPT_SHIFT 16
  46. #define AT91_SHDW_WKUPT_MASK GENMASK(31, 16)
  47. #define AT91_SHDW_WKUPT(x) ((1 << (x)) << AT91_SHDW_WKUPT_SHIFT \
  48. & AT91_SHDW_WKUPT_MASK)
  49. #define SHDW_WK_PIN(reg, cfg) ((reg) & AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
  50. #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1)
  51. #define SHDW_RTCWKEN(cfg) (1 << ((cfg)->mr_rtcwk_shift))
  52. #define DBC_PERIOD_US(x) DIV_ROUND_UP_ULL((1000000 * (x)), \
  53. SLOW_CLOCK_FREQ)
  54. struct shdwc_config {
  55. u8 wkup_pin_input;
  56. u8 mr_rtcwk_shift;
  57. u8 sr_rtcwk_shift;
  58. };
  59. struct shdwc {
  60. struct shdwc_config *cfg;
  61. void __iomem *at91_shdwc_base;
  62. };
  63. /*
  64. * Hold configuration here, cannot be more than one instance of the driver
  65. * since pm_power_off itself is global.
  66. */
  67. static struct shdwc *at91_shdwc;
  68. static struct clk *sclk;
  69. static void __iomem *mpddrc_base;
  70. static const unsigned long long sdwc_dbc_period[] = {
  71. 0, 3, 32, 512, 4096, 32768,
  72. };
  73. static void __init at91_wakeup_status(struct platform_device *pdev)
  74. {
  75. struct shdwc *shdw = platform_get_drvdata(pdev);
  76. u32 reg;
  77. char *reason = "unknown";
  78. reg = readl(shdw->at91_shdwc_base + AT91_SHDW_SR);
  79. dev_dbg(&pdev->dev, "%s: status = %#x\n", __func__, reg);
  80. /* Simple power-on, just bail out */
  81. if (!reg)
  82. return;
  83. if (SHDW_WK_PIN(reg, shdw->cfg))
  84. reason = "WKUP pin";
  85. else if (SHDW_RTCWK(reg, shdw->cfg))
  86. reason = "RTC";
  87. pr_info("AT91: Wake-Up source: %s\n", reason);
  88. }
  89. static void at91_poweroff(void)
  90. {
  91. writel(AT91_SHDW_KEY | AT91_SHDW_SHDW,
  92. at91_shdwc->at91_shdwc_base + AT91_SHDW_CR);
  93. }
  94. static void at91_lpddr_poweroff(void)
  95. {
  96. asm volatile(
  97. /* Align to cache lines */
  98. ".balign 32\n\t"
  99. /* Ensure AT91_SHDW_CR is in the TLB by reading it */
  100. " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  101. /* Power down SDRAM0 */
  102. " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
  103. /* Shutdown CPU */
  104. " str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  105. " b .\n\t"
  106. :
  107. : "r" (mpddrc_base),
  108. "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
  109. "r" (at91_shdwc->at91_shdwc_base),
  110. "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
  111. : "r0");
  112. }
  113. static u32 at91_shdwc_debouncer_value(struct platform_device *pdev,
  114. u32 in_period_us)
  115. {
  116. int i;
  117. int max_idx = ARRAY_SIZE(sdwc_dbc_period) - 1;
  118. unsigned long long period_us;
  119. unsigned long long max_period_us = DBC_PERIOD_US(sdwc_dbc_period[max_idx]);
  120. if (in_period_us > max_period_us) {
  121. dev_warn(&pdev->dev,
  122. "debouncer period %u too big, reduced to %llu us\n",
  123. in_period_us, max_period_us);
  124. return max_idx;
  125. }
  126. for (i = max_idx - 1; i > 0; i--) {
  127. period_us = DBC_PERIOD_US(sdwc_dbc_period[i]);
  128. dev_dbg(&pdev->dev, "%s: ref[%d] = %llu\n",
  129. __func__, i, period_us);
  130. if (in_period_us > period_us)
  131. break;
  132. }
  133. return i + 1;
  134. }
  135. static u32 at91_shdwc_get_wakeup_input(struct platform_device *pdev,
  136. struct device_node *np)
  137. {
  138. struct device_node *cnp;
  139. u32 wk_input_mask;
  140. u32 wuir = 0;
  141. u32 wk_input;
  142. for_each_child_of_node(np, cnp) {
  143. if (of_property_read_u32(cnp, "reg", &wk_input)) {
  144. dev_warn(&pdev->dev, "reg property is missing for %s\n",
  145. cnp->full_name);
  146. continue;
  147. }
  148. wk_input_mask = 1 << wk_input;
  149. if (!(wk_input_mask & AT91_SHDW_WKUPEN_MASK)) {
  150. dev_warn(&pdev->dev,
  151. "wake-up input %d out of bounds ignore\n",
  152. wk_input);
  153. continue;
  154. }
  155. wuir |= wk_input_mask;
  156. if (of_property_read_bool(cnp, "atmel,wakeup-active-high"))
  157. wuir |= AT91_SHDW_WKUPT(wk_input);
  158. dev_dbg(&pdev->dev, "%s: (child %d) wuir = %#x\n",
  159. __func__, wk_input, wuir);
  160. }
  161. return wuir;
  162. }
  163. static void at91_shdwc_dt_configure(struct platform_device *pdev)
  164. {
  165. struct shdwc *shdw = platform_get_drvdata(pdev);
  166. struct device_node *np = pdev->dev.of_node;
  167. u32 mode = 0, tmp, input;
  168. if (!np) {
  169. dev_err(&pdev->dev, "device node not found\n");
  170. return;
  171. }
  172. if (!of_property_read_u32(np, "debounce-delay-us", &tmp))
  173. mode |= AT91_SHDW_WKUPDBC(at91_shdwc_debouncer_value(pdev, tmp));
  174. if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
  175. mode |= SHDW_RTCWKEN(shdw->cfg);
  176. dev_dbg(&pdev->dev, "%s: mode = %#x\n", __func__, mode);
  177. writel(mode, shdw->at91_shdwc_base + AT91_SHDW_MR);
  178. input = at91_shdwc_get_wakeup_input(pdev, np);
  179. writel(input, shdw->at91_shdwc_base + AT91_SHDW_WUIR);
  180. }
  181. static const struct shdwc_config sama5d2_shdwc_config = {
  182. .wkup_pin_input = 0,
  183. .mr_rtcwk_shift = 17,
  184. .sr_rtcwk_shift = 5,
  185. };
  186. static const struct of_device_id at91_shdwc_of_match[] = {
  187. {
  188. .compatible = "atmel,sama5d2-shdwc",
  189. .data = &sama5d2_shdwc_config,
  190. }, {
  191. /*sentinel*/
  192. }
  193. };
  194. MODULE_DEVICE_TABLE(of, at91_shdwc_of_match);
  195. static int __init at91_shdwc_probe(struct platform_device *pdev)
  196. {
  197. struct resource *res;
  198. const struct of_device_id *match;
  199. struct device_node *np;
  200. u32 ddr_type;
  201. int ret;
  202. if (!pdev->dev.of_node)
  203. return -ENODEV;
  204. at91_shdwc = devm_kzalloc(&pdev->dev, sizeof(*at91_shdwc), GFP_KERNEL);
  205. if (!at91_shdwc)
  206. return -ENOMEM;
  207. platform_set_drvdata(pdev, at91_shdwc);
  208. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  209. at91_shdwc->at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
  210. if (IS_ERR(at91_shdwc->at91_shdwc_base)) {
  211. dev_err(&pdev->dev, "Could not map reset controller address\n");
  212. return PTR_ERR(at91_shdwc->at91_shdwc_base);
  213. }
  214. match = of_match_node(at91_shdwc_of_match, pdev->dev.of_node);
  215. at91_shdwc->cfg = (struct shdwc_config *)(match->data);
  216. sclk = devm_clk_get(&pdev->dev, NULL);
  217. if (IS_ERR(sclk))
  218. return PTR_ERR(sclk);
  219. ret = clk_prepare_enable(sclk);
  220. if (ret) {
  221. dev_err(&pdev->dev, "Could not enable slow clock\n");
  222. return ret;
  223. }
  224. at91_wakeup_status(pdev);
  225. at91_shdwc_dt_configure(pdev);
  226. pm_power_off = at91_poweroff;
  227. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
  228. if (!np)
  229. return 0;
  230. mpddrc_base = of_iomap(np, 0);
  231. of_node_put(np);
  232. if (!mpddrc_base)
  233. return 0;
  234. ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) & AT91_DDRSDRC_MD;
  235. if ((ddr_type == AT91_DDRSDRC_MD_LPDDR2) ||
  236. (ddr_type == AT91_DDRSDRC_MD_LPDDR3))
  237. pm_power_off = at91_lpddr_poweroff;
  238. else
  239. iounmap(mpddrc_base);
  240. return 0;
  241. }
  242. static int __exit at91_shdwc_remove(struct platform_device *pdev)
  243. {
  244. struct shdwc *shdw = platform_get_drvdata(pdev);
  245. if (pm_power_off == at91_poweroff ||
  246. pm_power_off == at91_lpddr_poweroff)
  247. pm_power_off = NULL;
  248. /* Reset values to disable wake-up features */
  249. writel(0, shdw->at91_shdwc_base + AT91_SHDW_MR);
  250. writel(0, shdw->at91_shdwc_base + AT91_SHDW_WUIR);
  251. clk_disable_unprepare(sclk);
  252. return 0;
  253. }
  254. static struct platform_driver at91_shdwc_driver = {
  255. .remove = __exit_p(at91_shdwc_remove),
  256. .driver = {
  257. .name = "at91-shdwc",
  258. .of_match_table = at91_shdwc_of_match,
  259. },
  260. };
  261. module_platform_driver_probe(at91_shdwc_driver, at91_shdwc_probe);
  262. MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
  263. MODULE_DESCRIPTION("Atmel shutdown controller driver");
  264. MODULE_LICENSE("GPL v2");