at91-poweroff.c 6.1 KB

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  1. /*
  2. * Atmel AT91 SAM9 SoCs reset code
  3. *
  4. * Copyright (C) 2007 Atmel Corporation.
  5. * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  6. * Copyright (C) 2014 Free Electrons
  7. *
  8. * This file is licensed under the terms of the GNU General Public
  9. * License version 2. This program is licensed "as is" without any
  10. * warranty of any kind, whether express or implied.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/io.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/of_address.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/printk.h>
  19. #include <soc/at91/at91sam9_ddrsdr.h>
  20. #define AT91_SHDW_CR 0x00 /* Shut Down Control Register */
  21. #define AT91_SHDW_SHDW BIT(0) /* Shut Down command */
  22. #define AT91_SHDW_KEY (0xa5 << 24) /* KEY Password */
  23. #define AT91_SHDW_MR 0x04 /* Shut Down Mode Register */
  24. #define AT91_SHDW_WKMODE0 GENMASK(2, 0) /* Wake-up 0 Mode Selection */
  25. #define AT91_SHDW_CPTWK0_MAX 0xf /* Maximum Counter On Wake Up 0 */
  26. #define AT91_SHDW_CPTWK0 (AT91_SHDW_CPTWK0_MAX << 4) /* Counter On Wake Up 0 */
  27. #define AT91_SHDW_CPTWK0_(x) ((x) << 4)
  28. #define AT91_SHDW_RTTWKEN BIT(16) /* Real Time Timer Wake-up Enable */
  29. #define AT91_SHDW_RTCWKEN BIT(17) /* Real Time Clock Wake-up Enable */
  30. #define AT91_SHDW_SR 0x08 /* Shut Down Status Register */
  31. #define AT91_SHDW_WAKEUP0 BIT(0) /* Wake-up 0 Status */
  32. #define AT91_SHDW_RTTWK BIT(16) /* Real-time Timer Wake-up */
  33. #define AT91_SHDW_RTCWK BIT(17) /* Real-time Clock Wake-up [SAM9RL] */
  34. enum wakeup_type {
  35. AT91_SHDW_WKMODE0_NONE = 0,
  36. AT91_SHDW_WKMODE0_HIGH = 1,
  37. AT91_SHDW_WKMODE0_LOW = 2,
  38. AT91_SHDW_WKMODE0_ANYLEVEL = 3,
  39. };
  40. static const char *shdwc_wakeup_modes[] = {
  41. [AT91_SHDW_WKMODE0_NONE] = "none",
  42. [AT91_SHDW_WKMODE0_HIGH] = "high",
  43. [AT91_SHDW_WKMODE0_LOW] = "low",
  44. [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
  45. };
  46. static void __iomem *at91_shdwc_base;
  47. static struct clk *sclk;
  48. static void __iomem *mpddrc_base;
  49. static void __init at91_wakeup_status(void)
  50. {
  51. u32 reg = readl(at91_shdwc_base + AT91_SHDW_SR);
  52. char *reason = "unknown";
  53. /* Simple power-on, just bail out */
  54. if (!reg)
  55. return;
  56. if (reg & AT91_SHDW_RTTWK)
  57. reason = "RTT";
  58. else if (reg & AT91_SHDW_RTCWK)
  59. reason = "RTC";
  60. pr_info("AT91: Wake-Up source: %s\n", reason);
  61. }
  62. static void at91_poweroff(void)
  63. {
  64. writel(AT91_SHDW_KEY | AT91_SHDW_SHDW, at91_shdwc_base + AT91_SHDW_CR);
  65. }
  66. static void at91_lpddr_poweroff(void)
  67. {
  68. asm volatile(
  69. /* Align to cache lines */
  70. ".balign 32\n\t"
  71. /* Ensure AT91_SHDW_CR is in the TLB by reading it */
  72. " ldr r6, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  73. /* Power down SDRAM0 */
  74. " str %1, [%0, #" __stringify(AT91_DDRSDRC_LPR) "]\n\t"
  75. /* Shutdown CPU */
  76. " str %3, [%2, #" __stringify(AT91_SHDW_CR) "]\n\t"
  77. " b .\n\t"
  78. :
  79. : "r" (mpddrc_base),
  80. "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
  81. "r" (at91_shdwc_base),
  82. "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
  83. : "r0");
  84. }
  85. static int at91_poweroff_get_wakeup_mode(struct device_node *np)
  86. {
  87. const char *pm;
  88. unsigned int i;
  89. int err;
  90. err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
  91. if (err < 0)
  92. return AT91_SHDW_WKMODE0_ANYLEVEL;
  93. for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
  94. if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
  95. return i;
  96. return -ENODEV;
  97. }
  98. static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
  99. {
  100. struct device_node *np = pdev->dev.of_node;
  101. int wakeup_mode;
  102. u32 mode = 0, tmp;
  103. wakeup_mode = at91_poweroff_get_wakeup_mode(np);
  104. if (wakeup_mode < 0) {
  105. dev_warn(&pdev->dev, "shdwc unknown wakeup mode\n");
  106. return;
  107. }
  108. if (!of_property_read_u32(np, "atmel,wakeup-counter", &tmp)) {
  109. if (tmp > AT91_SHDW_CPTWK0_MAX) {
  110. dev_warn(&pdev->dev,
  111. "shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
  112. tmp, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
  113. tmp = AT91_SHDW_CPTWK0_MAX;
  114. }
  115. mode |= AT91_SHDW_CPTWK0_(tmp);
  116. }
  117. if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
  118. mode |= AT91_SHDW_RTCWKEN;
  119. if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
  120. mode |= AT91_SHDW_RTTWKEN;
  121. writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR);
  122. }
  123. static int __init at91_poweroff_probe(struct platform_device *pdev)
  124. {
  125. struct resource *res;
  126. struct device_node *np;
  127. u32 ddr_type;
  128. int ret;
  129. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  130. at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
  131. if (IS_ERR(at91_shdwc_base)) {
  132. dev_err(&pdev->dev, "Could not map reset controller address\n");
  133. return PTR_ERR(at91_shdwc_base);
  134. }
  135. sclk = devm_clk_get(&pdev->dev, NULL);
  136. if (IS_ERR(sclk))
  137. return PTR_ERR(sclk);
  138. ret = clk_prepare_enable(sclk);
  139. if (ret) {
  140. dev_err(&pdev->dev, "Could not enable slow clock\n");
  141. return ret;
  142. }
  143. at91_wakeup_status();
  144. if (pdev->dev.of_node)
  145. at91_poweroff_dt_set_wakeup_mode(pdev);
  146. pm_power_off = at91_poweroff;
  147. np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
  148. if (!np)
  149. return 0;
  150. mpddrc_base = of_iomap(np, 0);
  151. of_node_put(np);
  152. if (!mpddrc_base)
  153. return 0;
  154. ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) & AT91_DDRSDRC_MD;
  155. if ((ddr_type == AT91_DDRSDRC_MD_LPDDR2) ||
  156. (ddr_type == AT91_DDRSDRC_MD_LPDDR3))
  157. pm_power_off = at91_lpddr_poweroff;
  158. else
  159. iounmap(mpddrc_base);
  160. return 0;
  161. }
  162. static int __exit at91_poweroff_remove(struct platform_device *pdev)
  163. {
  164. if (pm_power_off == at91_poweroff ||
  165. pm_power_off == at91_lpddr_poweroff)
  166. pm_power_off = NULL;
  167. clk_disable_unprepare(sclk);
  168. return 0;
  169. }
  170. static const struct of_device_id at91_ramc_of_match[] = {
  171. { .compatible = "atmel,sama5d3-ddramc", },
  172. { /* sentinel */ }
  173. };
  174. static const struct of_device_id at91_poweroff_of_match[] = {
  175. { .compatible = "atmel,at91sam9260-shdwc", },
  176. { .compatible = "atmel,at91sam9rl-shdwc", },
  177. { .compatible = "atmel,at91sam9x5-shdwc", },
  178. { /*sentinel*/ }
  179. };
  180. static struct platform_driver at91_poweroff_driver = {
  181. .remove = __exit_p(at91_poweroff_remove),
  182. .driver = {
  183. .name = "at91-poweroff",
  184. .of_match_table = at91_poweroff_of_match,
  185. },
  186. };
  187. module_platform_driver_probe(at91_poweroff_driver, at91_poweroff_probe);
  188. MODULE_AUTHOR("Atmel Corporation");
  189. MODULE_DESCRIPTION("Shutdown driver for Atmel SoCs");
  190. MODULE_LICENSE("GPL v2");